From dda8c1a22d592b0f0ccc267d81c787aee75a2ca3 Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Sun, 22 Sep 2024 14:00:03 -0700 Subject: [PATCH 1/7] Refactor STM32H7 linker scripts --- .../drivers/emac/TARGET_STM/stm32xx_emac.cpp | 93 +++---- platform/mbed_lib.json | 3 + .../TARGET_STM32H723xG/CMakeLists.txt | 4 - .../TARGET_STM32H725xE/CMakeLists.txt | 4 - .../TARGET_WIO_H725AE/CMakeLists.txt | 1 - .../TARGET_WIO_H725AE/system_clock_override.c | 118 --------- .../TARGET_STM32H725xE/cmsis_nvic.h | 1 - .../TARGET_STM32H735xG/CMakeLists.txt | 4 - .../TOOLCHAIN_GCC_ARM/stm32h735xg.ld | 203 --------------- .../TARGET_STM32H735xG/cmsis_nvic.h | 3 +- .../TARGET_STM32H743xI/CMakeLists.txt | 4 - .../TOOLCHAIN_GCC_ARM/STM32H743xI.ld | 236 ------------------ .../TARGET_STM32H750xB/CMakeLists.txt | 4 - .../TOOLCHAIN_GCC_ARM/stm32h750xb.ld | 203 --------------- .../TARGET_STM32H753xI/CMakeLists.txt | 4 - .../TOOLCHAIN_GCC_ARM/stm32h753xi.ld | 220 ---------------- .../TARGET_STM32H7A3xIQ/CMakeLists.txt | 4 - .../TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld | 207 --------------- .../TARGET_STM32H7B3xIQ/CMakeLists.txt | 4 - .../TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld | 203 --------------- .../linker_scripts/CMakeLists.txt | 4 +- .../CMakeLists.txt | 10 + .../STM32H743_H72x.ld} | 115 ++++----- .../CM4/STM32H745_H747_CM4.ld | 68 +++-- .../CM7/STM32H745_H747_CM7.ld | 96 ++++--- .../STM32H7Ax_FAMILY/CMakeLists.txt | 6 + .../STM32H7Ax_FAMILY/STM32H7Ax.ld} | 140 +++++------ .../stm32_eth_region_size_calcs.h | 51 ++++ targets/targets.json5 | 205 ++++++--------- 29 files changed, 418 insertions(+), 1800 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/system_clock_override.c delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/stm32h735xg.ld delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/stm32h750xb.ld delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/stm32h753xi.ld delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld delete mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld create mode 100644 targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt rename targets/TARGET_STM/TARGET_STM32H7/{TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/stm32h725xe.ld => linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld} (68%) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/CMakeLists.txt rename targets/TARGET_STM/TARGET_STM32H7/{TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld => linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld} (68%) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/linker_scripts/stm32_eth_region_size_calcs.h diff --git a/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp b/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp index daddbf1167b..13c9e66a1d6 100644 --- a/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp +++ b/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp @@ -27,10 +27,12 @@ #include "netsocket/nsapi_types.h" #include "platform/mbed_power_mgmt.h" #include "platform/mbed_error.h" +#include "CacheAlignedBuffer.h" #include "stm32xx_emac_config.h" #include "stm32xx_emac.h" + #include "mbed-trace/mbed_trace.h" #if defined(ETH_IP_VERSION_V2) @@ -59,6 +61,7 @@ #include "lan8742/lan8742.h" #include "lwip/memp.h" #include "lwip/api.h" +#include "linker_scripts/stm32_eth_region_size_calcs.h" #endif using namespace std::chrono; @@ -75,46 +78,19 @@ using namespace std::chrono; #define STM_ETH_MTU_SIZE 1500 #define STM_ETH_IF_NAME "st" -#ifndef ETH_IP_VERSION_V2 - -#if defined (__ICCARM__) /*!< IAR Compiler */ -#pragma data_alignment=4 -#endif -__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx DMA Descriptor */ - -#if defined (__ICCARM__) /*!< IAR Compiler */ -#pragma data_alignment=4 -#endif -__ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END; /* Ethernet Tx DMA Descriptor */ - -#if defined (__ICCARM__) /*!< IAR Compiler */ -#pragma data_alignment=4 -#endif -__ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */ - -#if defined (__ICCARM__) /*!< IAR Compiler */ -#pragma data_alignment=4 -#endif -__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */ - -#else // ETH_IP_VERSION_V2 - -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#define ETH_RX_DESC_CNT MBED_CONF_STM32_EMAC_ETH_RXBUFNB +#define ETH_TX_DESC_CNT MBED_CONF_STM32_EMAC_ETH_TXBUFNB -#pragma location=0x30040000 -ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ -#pragma location=0x30040100 -ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ -#pragma location=0x30040400 -uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */ +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".EthDescriptors"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".EthDescriptors"))); /* Ethernet Tx DMA Descriptors */ -#elif defined ( __GNUC__ ) /* GCC & ARMC6*/ +// Rx buffer addresses need to be aligned 4 bytes and to cache lines because we cache invalidate the buffers after receiving them. +mbed::StaticCacheAlignedBuffer Rx_Buff[ETH_RX_DESC_CNT] __attribute__((section(".EthBuffers"))); /* Ethernet Receive Buffers */ -ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ -ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ -uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE] __attribute__((section(".RxArraySection"))); /* Ethernet Receive Buffers */ +// Tx buffers just need to be aligned to the nearest 4 bytes. +uint32_t Tx_Buff[ETH_TX_DESC_CNT][ETH_MAX_PACKET_SIZE / sizeof(uint32_t)] __attribute__((section(".EthBuffers"))); -#endif +#if defined(ETH_IP_VERSION_V2) static lan8742_Object_t LAN8742; @@ -206,6 +182,12 @@ bool _phy_is_up(int32_t phy_state) return phy_state > LAN8742_STATUS_LINK_DOWN; } +// Integer log2 of an integer. +// from https://stackoverflow.com/questions/994593/how-to-do-an-integer-log2-in-c +static inline uint32_t log2i(uint32_t x) { + return sizeof(uint32_t) * 8 - __builtin_clz(x) - 1; +} + static void MPU_Config(void) { MPU_Region_InitTypeDef MPU_InitStruct; @@ -214,34 +196,23 @@ static void MPU_Config(void) HAL_MPU_Disable(); /* Configure the MPU attributes as Device not cacheable - for ETH DMA descriptors */ + for ETH DMA descriptors. The linker script puts these into their own + cordoned off, power-of-2 sized region. */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.BaseAddress = 0x30040000; - MPU_InitStruct.Size = MPU_REGION_SIZE_1KB; MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; - MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.Number = 4; // Mbed OS MPU config can use regions 0 through 3 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; MPU_InitStruct.SubRegionDisable = 0x00; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; - HAL_MPU_ConfigRegion(&MPU_InitStruct); + extern uint8_t __eth_descriptors_start[0]; // <-- defined in linker script + MPU_InitStruct.BaseAddress = reinterpret_cast(__eth_descriptors_start); - /* Configure the MPU attributes as Cacheable write through - for LwIP RAM heap which contains the Tx buffers */ - MPU_InitStruct.Enable = MPU_REGION_ENABLE; - MPU_InitStruct.BaseAddress = 0x30044000; - MPU_InitStruct.Size = MPU_REGION_SIZE_16KB; - MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; - MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; - MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; - MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; - MPU_InitStruct.Number = MPU_REGION_NUMBER1; - MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; - MPU_InitStruct.SubRegionDisable = 0x00; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + // Use a logarithm to calculate the region size + MPU_InitStruct.Size = log2i(STM32_DMA_DESCRIP_REGION_SIZE) - 1; HAL_MPU_ConfigRegion(&MPU_InitStruct); @@ -341,7 +312,7 @@ bool STM32_EMAC::low_level_init_successful() } /* Initialize Rx Descriptors list: Chain Mode */ - if (HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB) != HAL_OK) { + if (HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, Rx_Buff[0].data(), ETH_RXBUFNB) != HAL_OK) { tr_error("HAL_ETH_DMARxDescListInit issue"); return false; } @@ -399,7 +370,7 @@ bool STM32_EMAC::low_level_init_successful() TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; for (idx = 0; idx < ETH_RX_DESC_CNT; idx++) { - HAL_ETH_DescAssignMemory(&EthHandle, idx, Rx_Buff[idx], NULL); + HAL_ETH_DescAssignMemory(&EthHandle, idx, reinterpret_cast(Rx_Buff[idx].data()), NULL); } tr_info("low_level_init_successful"); @@ -534,6 +505,12 @@ bool STM32_EMAC::link_out(emac_mem_buf_t *buf) Txbuffer[i].next = NULL; } +#if defined(__DCACHE_PRESENT) + // For chips with a cache, we need to evict the Tx data from cache to main memory. + // This ensures that the DMA controller can see the most up-to-date copy of the data. + SCB_CleanDCache_by_Addr(Txbuffer[i].buffer, Txbuffer[i].len); +#endif + i++; } @@ -661,7 +638,7 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf) /* Build Rx descriptor to be ready for next data reception */ HAL_ETH_BuildRxDescriptors(&EthHandle); -#if !(defined(DUAL_CORE) && defined(CORE_CM4)) +#if defined(__DCACHE_PRESENT) /* Invalidate data cache for ETH Rx Buffers */ SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, frameLength); #endif diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json index 12481a50210..2bfefa4e7b5 100644 --- a/platform/mbed_lib.json +++ b/platform/mbed_lib.json @@ -243,6 +243,9 @@ "MTS_DRAGONFLY_L471QG": { "crash-capture-enabled": true, "fatal-error-auto-reboot-enabled": true + }, + "MCU_STM32H7": { + "crash-capture-enabled": true } } } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt index 9b262670180..56726b29df8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt @@ -5,10 +5,8 @@ add_subdirectory(TARGET_NUCLEO_H723ZG EXCLUDE_FROM_ALL) if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h723xg.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h723xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h723xg.sct) endif() add_library(mbed-stm32h723xg INTERFACE) @@ -23,6 +21,4 @@ target_sources(mbed-stm32h723xg ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32h723xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h723xg INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/CMakeLists.txt index fb055f26a51..d7c858d1100 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/CMakeLists.txt @@ -5,10 +5,8 @@ add_subdirectory(TARGET_WIO_H725AE EXCLUDE_FROM_ALL) if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h725xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h725xe.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h725xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h725xe.sct) endif() add_library(mbed-stm32h725xe INTERFACE) @@ -23,6 +21,4 @@ target_sources(mbed-stm32h725xe ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32h725xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h725xe INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/CMakeLists.txt index 67bfdd66a82..701f273928a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/CMakeLists.txt @@ -6,7 +6,6 @@ add_library(mbed-wio-h725ae INTERFACE) target_sources(mbed-wio-h725ae INTERFACE PeripheralPins.c - system_clock_override.c ) target_include_directories(mbed-wio-h725ae diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/system_clock_override.c deleted file mode 100644 index b78f35d1198..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TARGET_WIO_H725AE/system_clock_override.c +++ /dev/null @@ -1,118 +0,0 @@ -/* mbed Microcontroller Library - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * - * Copyright (c) 2015-2021 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** - * This file configures the system clock as follows: - *-------------------------------------------------------------------- - * System clock source | USE_PLL_HSE_XTAL (external 25 MHz xtal) - *-------------------------------------------------------------------- - * SYSCLK(MHz) | 550 - * AHBCLK (MHz) | 275 - * APB1CLK (MHz) | 137.5 - * APB2CLK (MHz) | 137.5 - * APB3CLK (MHz) | 137.5 - * APB4CLK (MHz) | 137.5 - * USB capable (48 MHz) | YES - *-------------------------------------------------------------------- -**/ - -#include "stm32h7xx.h" -#include "mbed_error.h" - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - default 25MHz) - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE() -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - -#if !defined(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY) - /** Supply configuration update enable - */ - HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); -#endif - - /** Configure the main internal regulator output voltage - */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; -#if HSE_VALUE==25000000 - RCC_OscInitStruct.PLL.PLLM = 2; - RCC_OscInitStruct.PLL.PLLN = 44; - RCC_OscInitStruct.PLL.PLLP = 1; - RCC_OscInitStruct.PLL.PLLQ = 5; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLFRACN = 0; -#else -#error Unsupported externall clock value, check HSE_VALUE define -#endif - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - return 0; // FAIL - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) - { - return 0; // FAIL - } - -#if DEVICE_USBDEVICE - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - return 0; // FAIL - } - - HAL_PWREx_EnableUSBVoltageDetector(); -#endif /* DEVICE_USBDEVICE */ - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) */ - - - diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/cmsis_nvic.h index 05a41ecee71..65a1d222020 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/cmsis_nvic.h @@ -19,5 +19,4 @@ #define NVIC_NUM_VECTORS 180 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_BANK_SRAM_DTC_START - #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/CMakeLists.txt index 3ec917d33d8..1f4e60dd809 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h735xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h735xg.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h735xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h735xg.sct) endif() add_library(mbed-stm32h735xg INTERFACE) @@ -21,6 +19,4 @@ target_sources(mbed-stm32h735xg ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32h735xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h735xg INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/stm32h735xg.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/stm32h735xg.ld deleted file mode 100644 index 5f479936c85..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/stm32h735xg.ld +++ /dev/null @@ -1,203 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/cmsis_nvic.h index 7a89564f452..65a1d222020 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/cmsis_nvic.h @@ -18,6 +18,5 @@ #define MBED_CMSIS_NVIC_H #define NVIC_NUM_VECTORS 180 -#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START - +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_BANK_SRAM_DTC_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/CMakeLists.txt index 1d97c5a782b..aae9befa134 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/CMakeLists.txt @@ -5,10 +5,8 @@ add_subdirectory(TARGET_NUCLEO_H743ZI2 EXCLUDE_FROM_ALL) if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h743xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/STM32H743xI.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h743xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h743xI.sct) endif() add_library(mbed-stm32h743xi INTERFACE) @@ -23,6 +21,4 @@ target_include_directories(mbed-stm32h743xi . ) -mbed_set_linker_script(mbed-stm32h743xi ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h743xi INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld deleted file mode 100644 index 62fadc887a3..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld +++ /dev/null @@ -1,236 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -M_CRASH_DATA_RAM_SIZE = 0x100; - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - DTCMRAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_ADDRESS + VECTORS_SIZE, LENGTH = 128K - VECTORS_SIZE - RAM (xrw) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE - RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K - RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K - ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .crash_data_ram : - { - . = ALIGN(8); - __CRASH_DATA_RAM__ = .; - __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ - KEEP(*(.keep.crash_data_ram)) - *(.m_crash_data_ram) /* This is a user defined section */ - . += M_CRASH_DATA_RAM_SIZE; - . = ALIGN(8); - __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > DTCMRAM - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - .lwip_sec (NOLOAD) : { - . = ABSOLUTE(0x30040000); - *(.RxDecripSection) - - . = ABSOLUTE(0x30040100); - *(.TxDecripSection) - - . = ABSOLUTE(0x30040400); - *(.RxArraySection) - - . = ABSOLUTE(0x30044000); - *(.ethusbram) - - } >RAM_D2 AT> FLASH -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/CMakeLists.txt index da5979ac9e0..aed25c38be8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h750xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h750xb.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h750xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h750xb.sct) endif() add_library(mbed-stm32h750xb INTERFACE) @@ -21,6 +19,4 @@ target_sources(mbed-stm32h750xb ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32h750xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h750xb INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/stm32h750xb.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/stm32h750xb.ld deleted file mode 100644 index 5f479936c85..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/stm32h750xb.ld +++ /dev/null @@ -1,203 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/CMakeLists.txt index 42eed028ac8..d89bf45ed8e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h753xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h753xi.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h753xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h753xi.sct) endif() add_library(mbed-stm32h753xi INTERFACE) @@ -21,6 +19,4 @@ target_sources(mbed-stm32h753xi ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32h753xi ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h753xi INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/stm32h753xi.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/stm32h753xi.ld deleted file mode 100644 index 198b8f71d72..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/stm32h753xi.ld +++ /dev/null @@ -1,220 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE - RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K - RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - .lwip_sec (NOLOAD) : { - . = ABSOLUTE(0x30040000); - *(.RxDecripSection) - - . = ABSOLUTE(0x30040100); - *(.TxDecripSection) - - . = ABSOLUTE(0x30040400); - *(.RxArraySection) - - . = ABSOLUTE(0x30044000); - *(.ethusbram) - - } >RAM_D2 AT> FLASH -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/CMakeLists.txt index f16a4d350cf..eba60520f86 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/CMakeLists.txt @@ -5,10 +5,8 @@ add_subdirectory(TARGET_NUCLEO_H7A3ZI_Q EXCLUDE_FROM_ALL) if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h7a3xxq.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h7a3xxq.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h7a3xxq.sct) endif() add_library(mbed-stm32h7a3xiq INTERFACE) @@ -24,6 +22,4 @@ target_include_directories(mbed-stm32h7a3xiq . ) -mbed_set_linker_script(mbed-stm32h7a3xiq ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h7a3xiq INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld deleted file mode 100644 index 919077ec530..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld +++ /dev/null @@ -1,207 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - DTCMRAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_ADDRESS + VECTORS_SIZE, LENGTH = 128K - VECTORS_SIZE - RAM (xrw) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K - RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K - ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/CMakeLists.txt index 79325fa9b33..daeebeef9b4 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/CMakeLists.txt @@ -3,10 +3,8 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h7b3xxq.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h7b3xxq.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32h7b3xiq.sct) endif() add_library(mbed-stm32h7b3xiq INTERFACE) @@ -21,6 +19,4 @@ target_sources(mbed-stm32h7b3xiq ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32h7b3xiq ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h7b3xiq INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld deleted file mode 100644 index 5f479936c85..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld +++ /dev/null @@ -1,203 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/CMakeLists.txt index d292a06ac76..9477b74a098 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/CMakeLists.txt @@ -1,4 +1,6 @@ # Copyright (c) 2024 Jamie Smith # SPDX-License-Identifier: Apache-2.0 -add_subdirectory(STM32H745_47_FAMILY) \ No newline at end of file +add_subdirectory(STM32H7Ax_FAMILY) +add_subdirectory(STM32H745_47_FAMILY) +add_subdirectory(STM32H743_STM32H72x_FAMILIES) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt new file mode 100644 index 00000000000..62d614aa269 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-stm32h743xi STM32H743_H72x.ld) + mbed_set_linker_script(mbed-stm32h723xg STM32H743_H72x.ld) + mbed_set_linker_script(mbed-stm32h725xe STM32H743_H72x.ld) + mbed_set_linker_script(mbed-stm32h735xg STM32H743_H72x.ld) + mbed_set_linker_script(mbed-stm32h750xb STM32H743_H72x.ld) + mbed_set_linker_script(mbed-stm32h753xi STM32H743_H72x.ld) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/stm32h725xe.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld similarity index 68% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/stm32h725xe.ld rename to targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld index 5a84b0645b2..4c25ce56e48 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/stm32h725xe.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/STM32H743_H72x.ld @@ -15,16 +15,8 @@ ****************************************************************************** */ -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif +#include "cmsis_nvic.h" +#include "../stm32_eth_region_size_calcs.h" M_CRASH_DATA_RAM_SIZE = 0x100; @@ -38,17 +30,15 @@ STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; /* Round up MBED_VECTTABLE_RAM_SIZE to 8 bytes */ #define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) -#define MBED_RAM0_START (MBED_RAM_START + MBED_VECTTABLE_RAM_SIZE) -#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE) MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - SRAM_DTC (xrw) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE - SRAM (xrw) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE - SRAM_LOWER (xrw) : ORIGIN = 0x30000000, LENGTH = 32K - SRAM_UPPER (xrw) : ORIGIN = 0x38000000, LENGTH = 16K - SRAM_ITC (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = MBED_CONFIGURED_ROM_BANK_IROM1_SIZE + SRAM_DTC (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START + MBED_VECTTABLE_RAM_SIZE, LENGTH = MBED_RAM_BANK_SRAM_DTC_SIZE - MBED_VECTTABLE_RAM_SIZE + SRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D1_START, LENGTH = MBED_RAM_BANK_SRAM_D1_SIZE + SRAM_D2 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D2_START, LENGTH = MBED_RAM_BANK_SRAM_D2_SIZE + SRAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE + SRAM_ITC (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE } /* Linker script to place sections and symbol values. Should be used together @@ -124,6 +114,7 @@ SECTIONS __etext = .; _sidata = .; + /* Put crash data in the otherwise unused D3 SRAM */ .crash_data_ram : { . = ALIGN(8); @@ -134,36 +125,7 @@ SECTIONS . += M_CRASH_DATA_RAM_SIZE; . = ALIGN(8); __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > SRAM_UPPER - - /* .stack section doesn't contains any symbols. It is only - * used for linker to reserve space for the isr stack section - * WARNING: .stack should come immediately after the last secure memory - * section. This provides stack overflow detection. */ - .stack (NOLOAD): - { - __StackLimit = .; - *(.stack*); - . += STACK_SIZE - (. - __StackLimit); - } > SRAM_DTC - - /* Set stack top to end of SRAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ADDR(.stack) + SIZEOF(.stack); - _estack = __StackTop; - __StackLimit = ADDR(.stack); - PROVIDE(__stack = __StackTop); - - /* Place holder for additional heap */ - .heap_0 (COPY): - { - __mbed_sbrk_start_0 = .; - . += (ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - .); - __mbed_krbs_start_0 = .; - } > SRAM_DTC - - /* Check if heap exceeds SRAM_DTC */ - ASSERT(__mbed_krbs_start_0 <= (ORIGIN(SRAM_DTC)+LENGTH(SRAM_DTC)), "Heap is too big for SRAM_DTC") + } > SRAM_D3 .data : AT (__etext) { @@ -200,9 +162,6 @@ SECTIONS } > SRAM - /* Check if data exceeds SRAM */ - ASSERT(__data_end__ <= (ORIGIN(SRAM)+LENGTH(SRAM)), "data is too big for SRAM") - /* Uninitialized data section * This region is not initialized by the C/C++ library and can be used to * store state across soft reboots. */ @@ -215,7 +174,7 @@ SECTIONS . = ALIGN(32); __uninitialized_end = .; } > SRAM - + .bss : { . = ALIGN(8); @@ -228,20 +187,54 @@ SECTIONS _ebss = .; } > SRAM - /* Check if bss exceeds SRAM */ - ASSERT(__bss_end__ <= (ORIGIN(SRAM)+LENGTH(SRAM)), "bss is too big for SRAM") - .heap (COPY): { __end__ = .; - end = __end__; - __mbed_sbrk_start = .; + PROVIDE(end = .); + PROVIDE(__mbed_sbrk_start = .); *(.heap*) - . += (ORIGIN(SRAM) + LENGTH(SRAM) - .); - __mbed_krbs_start = .; + . = ORIGIN(SRAM) + LENGTH(SRAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__mbed_krbs_start = .); __HeapLimit = .; } > SRAM - /* Check if data + heap exceeds SRAM limit */ - ASSERT(__HeapLimit <= (ORIGIN(SRAM)+LENGTH(SRAM)), "Heap is too big for SRAM") + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + /* Set stack top to end of SRAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds SRAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region SRAM overflowed with stack") + + /* Ethernet DMA descriptors should be at the start of SRAM_D2 because they need an MPU region + and because the CM4 and CM7 have to agree on their location.*/ + .eth_descriptors (NOLOAD) : { + ASSERT(. == ORIGIN(SRAM_D2), "Eth Descriptors region must be at the start of SRAM_D2"); + PROVIDE(__eth_descriptors_start = .); + *(.EthDescriptors) + . = __eth_descriptors_start + STM32_DMA_DESCRIP_REGION_SIZE; + } >SRAM_D2 + + /* Ethernet buffers are recommended to be in SRAM_D2 but don't need any special MPU region. */ + .eth_buffers (NOLOAD) : { + *(.EthBuffers) + } >SRAM_D2 + + /* Use the rest of DTCM as additional heap */ + .heap_0 (COPY): + { + PROVIDE(__mbed_sbrk_start_0 = .); + . += (ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - .); + PROVIDE(__mbed_krbs_start_0 = .); + } > SRAM_DTC } diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/STM32H745_H747_CM4.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/STM32H745_H747_CM4.ld index 074a5955d87..02a3cf703c9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/STM32H745_H747_CM4.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM4/STM32H745_H747_CM4.ld @@ -16,6 +16,9 @@ */ #include "cmsis_nvic.h" +#include "../../stm32_eth_region_size_calcs.h" + +M_CRASH_DATA_RAM_SIZE = 0x100; #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) /* This value is normally defined by the tools @@ -23,17 +26,17 @@ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 #endif -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +/* Round up MBED_VECTTABLE_RAM_SIZE to 8 bytes */ +#define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) MEMORY { - FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_START, LENGTH = MBED_CONFIGURED_ROM_SIZE - DTCMRAM (rwx) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START + VECTORS_SIZE, LENGTH = 128K - MBED_RAM_BANK_SRAM_DTC_SIZE - RAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D1_START, LENGTH = MBED_RAM_BANK_SRAM_D1_SIZE - RAM_D2 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D2_START, LENGTH = MBED_RAM_BANK_SRAM_D2_SIZE - RAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE - ITCMRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = MBED_CONFIGURED_ROM_BANK_IROM1_SIZE + SRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D1_START, LENGTH = MBED_RAM_BANK_SRAM_D1_SIZE + SRAM_D2 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D2_START, LENGTH = MBED_RAM_BANK_SRAM_D2_SIZE + SRAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE } /* Linker script to place sections and symbol values. Should be used together @@ -107,6 +110,16 @@ SECTIONS __exidx_end = .; __etext = .; + + /* Ethernet DMA descriptors should be at the start of SRAM_D2 because they need an MPU region + and because the CM4 and CM7 have to agree on their location.*/ + .eth_descriptors (NOLOAD) : { + ASSERT(. == ORIGIN(SRAM_D2), "Eth Descriptors region must be at the start of SRAM_D2"); + PROVIDE(__eth_descriptors_start = .); + *(.EthDescriptors) + . = __eth_descriptors_start + STM32_DMA_DESCRIP_REGION_SIZE; + } >SRAM_D2 + _sidata = .; .data : AT (__etext) @@ -142,7 +155,7 @@ SECTIONS __data_end__ = .; _edata = .; - } > RAM_D2 + } > SRAM_D2 /* Uninitialized data section * This region is not initialized by the C/C++ library and can be used to @@ -155,7 +168,7 @@ SECTIONS KEEP(*(.keep.uninitialized)) . = ALIGN(32); __uninitialized_end = .; - } > RAM_D2 + } > SRAM_D2 .bss : { @@ -167,24 +180,25 @@ SECTIONS . = ALIGN(8); __bss_end__ = .; _ebss = .; - } > RAM_D2 + } > SRAM_D2 .heap (COPY): { __end__ = .; PROVIDE(end = .); + PROVIDE(__mbed_sbrk_start = .); *(.heap*) - . = ORIGIN(RAM_D2) + LENGTH(RAM_D2) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + . = ORIGIN(SRAM_D2) + LENGTH(SRAM_D2) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__mbed_krbs_start = .); __HeapLimit = .; - } > RAM_D2 - + } > SRAM_D2 /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ .stack_dummy (COPY): { *(.stack*) - } > RAM_D2 + } > SRAM_D2 /* Set stack top to end of RAM_D2, and stack limit move down by * size of stack_dummy section */ @@ -193,6 +207,26 @@ SECTIONS __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; PROVIDE(__stack = __StackTop); - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + /* Check if data + heap + stack exceeds SRAM_D2 limit */ + ASSERT(__StackLimit >= __HeapLimit, "region SRAM_D2 overflowed with stack") + + /* Put crash data in the otherwise unused D3 SRAM */ + .crash_data_ram : + { + /* Advance forward by 1 crash data ram size so that we don't overwrite the CM7's crash data */ + . += M_CRASH_DATA_RAM_SIZE; + + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > SRAM_D3 + + /* Ethernet buffers are recommended to be in SRAM_D2 but don't need any special MPU region. */ + .eth_buffers (NOLOAD) : { + *(.EthBuffers) + } >SRAM_D2 } diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld index 57c2dc9e043..f875636dc17 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H745_47_FAMILY/CM7/STM32H745_H747_CM7.ld @@ -16,6 +16,9 @@ */ #include "cmsis_nvic.h" +#include "../../stm32_eth_region_size_calcs.h" + +M_CRASH_DATA_RAM_SIZE = 0x100; #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) /* This value is normally defined by the tools @@ -23,21 +26,23 @@ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 #endif -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +/* Round up MBED_VECTTABLE_RAM_SIZE to 8 bytes */ +#define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) MEMORY { - FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_START, LENGTH = MBED_CONFIGURED_ROM_SIZE - DTCMRAM (rwx) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START + VECTORS_SIZE, LENGTH = 128K - MBED_RAM_BANK_SRAM_DTC_SIZE - RAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D1_START, LENGTH = MBED_RAM_BANK_SRAM_D1_SIZE - RAM_D2 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D2_START, LENGTH = MBED_RAM_BANK_SRAM_D2_SIZE - RAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE - ITCMRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = MBED_CONFIGURED_ROM_BANK_IROM1_SIZE + SRAM_DTC (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START + MBED_VECTTABLE_RAM_SIZE, LENGTH = MBED_RAM_BANK_SRAM_DTC_SIZE - MBED_VECTTABLE_RAM_SIZE + SRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D1_START, LENGTH = MBED_RAM_BANK_SRAM_D1_SIZE + SRAM_D2 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D2_START, LENGTH = MBED_RAM_BANK_SRAM_D2_SIZE + SRAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE + SRAM_ITC (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE } /* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. + * with other linker script that defines memory regions FLASH and SRAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * @@ -142,7 +147,7 @@ SECTIONS __data_end__ = .; _edata = .; - } > RAM + } > SRAM /* Uninitialized data section * This region is not initialized by the C/C++ library and can be used to @@ -155,7 +160,7 @@ SECTIONS KEEP(*(.keep.uninitialized)) . = ALIGN(32); __uninitialized_end = .; - } > RAM + } > SRAM .bss : { @@ -167,16 +172,18 @@ SECTIONS . = ALIGN(8); __bss_end__ = .; _ebss = .; - } > RAM + } > SRAM .heap (COPY): { __end__ = .; PROVIDE(end = .); + PROVIDE(__mbed_sbrk_start = .); *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + . = ORIGIN(SRAM) + LENGTH(SRAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__mbed_krbs_start = .); __HeapLimit = .; - } > RAM + } > SRAM /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign @@ -184,30 +191,51 @@ SECTIONS .stack_dummy (COPY): { *(.stack*) - } > RAM + } > SRAM - /* Set stack top to end of RAM, and stack limit move down by + /* Set stack top to end of SRAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); _estack = __StackTop; __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; PROVIDE(__stack = __StackTop); - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - .lwip_sec (NOLOAD) : { - . = ABSOLUTE(0x10040000); - *(.RxDecripSection) - - . = ABSOLUTE(0x10040100); - *(.TxDecripSection) - - . = ABSOLUTE(0x10040400); - *(.RxArraySection) - - . = ABSOLUTE(0x10044000); - *(.ethusbram) - - } >RAM_D2 AT> FLASH + /* Check if data + heap + stack exceeds SRAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region SRAM overflowed with stack") + + /* Ethernet DMA descriptors should be at the start of SRAM_D2 because they need an MPU region + and because the CM4 and CM7 have to agree on their location.*/ + .eth_descriptors (NOLOAD) : { + ASSERT(. == ORIGIN(SRAM_D2), "Eth Descriptors region must be at the start of SRAM_D2"); + PROVIDE(__eth_descriptors_start = .); + *(.EthDescriptors) + . = __eth_descriptors_start + STM32_DMA_DESCRIP_REGION_SIZE; + } >SRAM_D2 + + /* Ethernet buffers are recommended to be in SRAM_D2 but not required to be, so we will + put them in SRAM since SRAM2 is used by the CM4 */ + .eth_buffers (NOLOAD) : { + *(.EthBuffers) + } >SRAM + + /* Put crash data in the otherwise unused D3 SRAM */ + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > SRAM_D3 + + /* Use the rest of DTCM as additional heap */ + .heap_0 (COPY): + { + PROVIDE(__mbed_sbrk_start_0 = .); + . += (ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - .); + PROVIDE(__mbed_krbs_start_0 = .); + } > SRAM_DTC } diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/CMakeLists.txt new file mode 100644 index 00000000000..6d52456d32a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-stm32h7a3xiq STM32H7Ax.ld) + mbed_set_linker_script(mbed-stm32h7b3xiq STM32H7Ax.ld) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld similarity index 68% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld rename to targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld index bf7b2159999..fbb3793f311 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H7Ax_FAMILY/STM32H7Ax.ld @@ -15,16 +15,8 @@ ****************************************************************************** */ -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif +#include "cmsis_nvic.h" +#include "../stm32_eth_region_size_calcs.h" M_CRASH_DATA_RAM_SIZE = 0x100; @@ -38,21 +30,19 @@ STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; /* Round up MBED_VECTTABLE_RAM_SIZE to 8 bytes */ #define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) -#define MBED_RAM0_START (MBED_RAM_START + MBED_VECTTABLE_RAM_SIZE) -#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE) MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - SRAM_DTC (xrw) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE - SRAM (xrw) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE - SRAM_LOWER (xrw) : ORIGIN = 0x30000000, LENGTH = 32K - SRAM_UPPER (xrw) : ORIGIN = 0x38000000, LENGTH = 16K - SRAM_ITC (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_IROM1_START, LENGTH = MBED_CONFIGURED_ROM_BANK_IROM1_SIZE + SRAM_DTC (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_DTC_START + MBED_VECTTABLE_RAM_SIZE, LENGTH = MBED_RAM_BANK_SRAM_DTC_SIZE - MBED_VECTTABLE_RAM_SIZE + SRAM (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_AHB_START, LENGTH = MBED_RAM_BANK_SRAM_AHB_SIZE + SRAM_AXI (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_AXI_START, LENGTH = MBED_RAM_BANK_SRAM_AXI_SIZE + SRAM_D3 (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_D3_START, LENGTH = MBED_RAM_BANK_SRAM_D3_SIZE + SRAM_ITC (xrw) : ORIGIN = MBED_RAM_BANK_SRAM_ITC_START, LENGTH = MBED_RAM_BANK_SRAM_ITC_SIZE } /* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. + * with other linker script that defines memory regions FLASH and SRAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * @@ -123,48 +113,7 @@ SECTIONS __etext = .; _sidata = .; - - .crash_data_ram : - { - . = ALIGN(8); - __CRASH_DATA_RAM__ = .; - __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ - KEEP(*(.keep.crash_data_ram)) - *(.m_crash_data_ram) /* This is a user defined section */ - . += M_CRASH_DATA_RAM_SIZE; - . = ALIGN(8); - __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > SRAM_UPPER - - /* .stack section doesn't contains any symbols. It is only - * used for linker to reserve space for the isr stack section - * WARNING: .stack should come immediately after the last secure memory - * section. This provides stack overflow detection. */ - .stack (NOLOAD): - { - __StackLimit = .; - *(.stack*); - . += STACK_SIZE - (. - __StackLimit); - } > SRAM_DTC - - /* Set stack top to end of SRAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ADDR(.stack) + SIZEOF(.stack); - _estack = __StackTop; - __StackLimit = ADDR(.stack); - PROVIDE(__stack = __StackTop); - - /* Place holder for additional heap */ - .heap_0 (COPY): - { - __mbed_sbrk_start_0 = .; - . += (ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - .); - __mbed_krbs_start_0 = .; - } > SRAM_DTC - - /* Check if heap exceeds SRAM_DTC */ - ASSERT(__mbed_krbs_start_0 <= (ORIGIN(SRAM_DTC)+LENGTH(SRAM_DTC)), "Heap is too big for SRAM_DTC") - + .data : AT (__etext) { __data_start__ = .; @@ -200,9 +149,6 @@ SECTIONS } > SRAM - /* Check if bss exceeds SRAM */ - ASSERT(__data_end__ <= (ORIGIN(SRAM)+LENGTH(SRAM)), ".data is too big for SRAM") - /* Uninitialized data section * This region is not initialized by the C/C++ library and can be used to * store state across soft reboots. */ @@ -215,7 +161,7 @@ SECTIONS . = ALIGN(32); __uninitialized_end = .; } > SRAM - + .bss : { . = ALIGN(8); @@ -228,20 +174,66 @@ SECTIONS _ebss = .; } > SRAM - /* Check if bss exceeds SRAM */ - ASSERT(__bss_end__ <= (ORIGIN(SRAM)+LENGTH(SRAM)), "BSS is too big for SRAM") - .heap (COPY): { __end__ = .; - end = __end__; - __mbed_sbrk_start = .; + PROVIDE(end = .); + PROVIDE(__mbed_sbrk_start = .); *(.heap*) - . += (ORIGIN(SRAM) + LENGTH(SRAM) - .); - __mbed_krbs_start = .; + . = ORIGIN(SRAM) + LENGTH(SRAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__mbed_krbs_start = .); __HeapLimit = .; } > SRAM - /* Check if data + heap exceeds SRAM limit */ - ASSERT(__HeapLimit <= (ORIGIN(SRAM)+LENGTH(SRAM)), "Heap is too big for SRAM") + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + /* Set stack top to end of SRAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds SRAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region SRAM overflowed with stack") + + /* Put crash data in the otherwise unused D3 SRAM */ + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > SRAM_D3 + + /* Ethernet DMA descriptors should be at the start of SRAM_AXI because they need an MPU region.*/ + .eth_descriptors (NOLOAD) : { + ASSERT(. == ORIGIN(SRAM_AXI), "Eth Descriptors region must be at the start of SRAM_D2"); + PROVIDE(__eth_descriptors_start = .); + *(.EthDescriptors) + . = __eth_descriptors_start + STM32_DMA_DESCRIP_REGION_SIZE; + } >SRAM_AXI + + /* Ethernet buffers are recommended to be in SRAM_AXI but don't need any special MPU region. */ + .eth_buffers (NOLOAD) : { + *(.EthBuffers) + } >SRAM_AXI + + /* Use the rest of DTCM as additional heap */ + .heap_0 (COPY): + { + PROVIDE(__mbed_sbrk_start_0 = .); + . += (ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - .); + PROVIDE(__mbed_krbs_start_0 = .); + } > SRAM_DTC } diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/stm32_eth_region_size_calcs.h b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/stm32_eth_region_size_calcs.h new file mode 100644 index 00000000000..16f3499be33 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/stm32_eth_region_size_calcs.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright (c) 2024 Jamie Smith + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file contains calculations for the size of the memory region used for the Ethernet buffer descriptors. + * This region must be a power-of-2 size so that it can be used as an MPU region. Also, in dual core + * CPUs, the CM4 and CM7 have to agree on its size so they don't define conflicting memory regions. + * + * So, this header has some fancy math to calculate it. Note that this header is included by + * linker scripts so it can only contain preprocessor code. + */ + +/* from here: https://stackoverflow.com/questions/22925016/rounding-up-to-powers-of-2-with-preprocessor-constants */ +#define POW2_CEIL(v) (1 + \ +(((((((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) | \ + ((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) >> 0x04))) | \ + ((((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) | \ + ((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) >> 0x04))) >> 0x02))) | \ + ((((((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) | \ + ((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) >> 0x04))) | \ + ((((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) | \ + ((((v) - 1) | (((v) - 1) >> 0x10) | \ + (((v) - 1) | (((v) - 1) >> 0x10) >> 0x08)) >> 0x04))) >> 0x02))) >> 0x01)))) + +/* Size of an ETH_DMADescTypeDef structure in bytes*/ +#define STM32_SIZEOF_ETH_DMA_DESCRIPTOR 24 + +/* Calculation of RAM size */ +#define STM32_TOTAL_DMA_DESCRIPTOR_RAM_NEEDED (STM32_SIZEOF_ETH_DMA_DESCRIPTOR * (MBED_CONF_STM32_EMAC_ETH_RXBUFNB + MBED_CONF_STM32_EMAC_ETH_TXBUFNB)) +#define STM32_DMA_DESCRIP_REGION_SIZE POW2_CEIL(STM32_TOTAL_DMA_DESCRIPTOR_RAM_NEEDED) \ No newline at end of file diff --git a/targets/targets.json5 b/targets/targets.json5 index 9a92265c647..2f738a12003 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3314,7 +3314,8 @@ "STM32H7_550MHZ" ], "macros_add": [ - "STM32H735xx" + "STM32H735xx", + "MBED_SPLIT_HEAP" ], "overrides": { "system_power_supply": "PWR_LDO_SUPPLY" @@ -3332,7 +3333,8 @@ "STM32H7_480MHZ" ], "macros_add": [ - "STM32H743xx" + "STM32H743xx", + "MBED_SPLIT_HEAP" ], "overrides": { "system_power_supply": "PWR_LDO_SUPPLY" @@ -3417,11 +3419,6 @@ "macros_add": [ "STM32H745xx" ], - "overrides": { - "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", - // Cannot enable overdrive mode because the default power supply is SMPS - "enable-overdrive-mode": 0 - }, "device_name": "STM32H745ZITx" }, "MCU_STM32H745xI_CM4": { @@ -3461,17 +3458,15 @@ } }, "macros_add": [ - "CORE_CM7" + "CORE_CM7", + "MBED_SPLIT_HEAP" ] }, - "NUCLEO_H745ZI_Q_CM7": { - "inherits": [ - "MCU_STM32H745xI_CM7" - ], - "extra_labels_add": [ "NUCLEO_H745ZI_Q" ], + "NUCLEO_H745ZI_Q": { "supported_form_factors": [ "ARDUINO_UNO" ], + "public": false, "config": { "d11_configuration": { "help": "Value: PB_5 for the default board configuration, PA_7 in case of solder bridge update (SB33 on/ SB35 off)", @@ -3481,47 +3476,24 @@ "usb_speed": { "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", "value": "USE_USB_OTG_FS" - } - }, - "device_has_add": [ - "USBDEVICE" - ], - "overrides": { - "network-default-interface-type": "ETHERNET" - }, - "image_url": "https://www.st.com/bin/ecommerce/api/image.PF262651.en.feature-description-include-personalized-no-cpn-medium.jpg" - }, - "NUCLEO_H745ZI_Q_CM4": { - "inherits": [ - "MCU_STM32H745xI_CM4" - ], - "extra_labels_add": [ "NUCLEO_H745ZI_Q" ], - "supported_form_factors": [ - "ARDUINO_UNO" - ], - "config": { - "d11_configuration": { - "help": "Value: PB_5 for the default board configuration, PA_7 in case of solder bridge update (SB33 on/ SB35 off)", - "value": "PB_5", - "macro_name": "STM32_D11_SPI_ETHERNET_PIN" }, - "usb_speed": { - "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", - "value": "USE_USB_OTG_FS" - } }, "device_has_add": [ "USBDEVICE" ], "overrides": { - "network-default-interface-type": "ETHERNET" + "network-default-interface-type": "ETHERNET", + "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", + // Cannot enable overdrive mode because the default power supply is SMPS + "enable-overdrive-mode": 0 }, "image_url": "https://www.st.com/bin/ecommerce/api/image.PF262651.en.feature-description-include-personalized-no-cpn-medium.jpg" }, - "NUCLEO_H745ZI_Q" : { - "inherits" : [ - "NUCLEO_H745ZI_Q_CM7" - ] + "NUCLEO_H745ZI_Q_CM7": { + inherits: ["MCU_STM32H745xI_CM7", "NUCLEO_H745ZI_Q"] + }, + "NUCLEO_H745ZI_Q_CM4": { + inherits: ["MCU_STM32H745xI_CM4", "NUCLEO_H745ZI_Q"] }, "MCU_STM32H747xI": { "inherits": [ @@ -3534,12 +3506,7 @@ ], "macros_add": [ "STM32H747xx" - ], - "overrides": { - "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", - // Cannot enable overdrive mode because the default power supply is SMPS - "enable-overdrive-mode": 0 - } + ] }, "MCU_STM32H747xI_CM7": { "inherits": [ @@ -3558,12 +3525,48 @@ } }, "macros_add": [ - "CORE_CM7" + "CORE_CM7", + "MBED_SPLIT_HEAP" ] }, + "MCU_STM32H747xI_CM4": { + "inherits": [ + "MCU_STM32H747xI" + ], + "public": false, + "extra_labels_add": [ + "STM32H747xI_CM4" + ], + "core": "Cortex-M4F", + "memory_bank_config": { + // Select flash bank 2 + "IROM1": { + "start": 0x08100000, + "size": 0x100000 + } + }, + "macros_add": [ + "CORE_CM4", + "MBED_MPU_CUSTOM" + ], + "device_has_remove": [ + "MPU" + ], + "OUTPUT_EXT": "hex" + }, + "DISCO_H747I": { + "image_url": "https://mm.digikey.com/Volume0/opasdata/d220001/medias/images/310/MFG_STM32H747I-DISCO.jpg", + "public": false, + "overrides": { + "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", + // Cannot enable overdrive mode because the default power supply is SMPS + "enable-overdrive-mode": 0 + } + }, "DISCO_H747I_CM7": { "inherits": [ - "MCU_STM32H747xI_CM7" + "MCU_STM32H747xI_CM7", + "DISCO_H747" ], "supported_form_factors": [ "ARDUINO_UNO", @@ -3583,39 +3586,12 @@ "detect_code": [ "0814" ], - "device_name": "STM32H747XIHx", - "image_url": "https://mm.digikey.com/Volume0/opasdata/d220001/medias/images/310/MFG_STM32H747I-DISCO.jpg" - }, - "DISCO_H747I": { - "inherits": [ - "DISCO_H747I_CM7" - ], - "image_url": "https://mm.digikey.com/Volume0/opasdata/d220001/medias/images/310/MFG_STM32H747I-DISCO.jpg" - }, - "MCU_STM32H747xI_CM4": { - "inherits": [ - "MCU_STM32H747xI" - ], - "public": false, - "extra_labels_add": [ - "STM32H747xI_CM4" - ], - "core": "Cortex-M4F", - "memory_bank_config": { - // Select flash bank 2 - "IROM1": { - "start": 0x08100000, - "size": 0x100000 - } - }, - "macros_add": [ - "CORE_CM4" - ], - "OUTPUT_EXT": "hex" + "device_name": "STM32H747XIHx" }, "DISCO_H747I_CM4": { "inherits": [ - "MCU_STM32H747xI_CM4" + "MCU_STM32H747xI_CM4", + "DISCO_H747" ], "extra_labels_add": [ "DISCO_H747I", @@ -3632,8 +3608,7 @@ "STMOD", "PMOD" ], - "device_name": "STM32H747XIHx", - "image_url": "https://mm.digikey.com/Volume0/opasdata/d220001/medias/images/310/MFG_STM32H747I-DISCO.jpg" + "device_name": "STM32H747XIHx" }, // Umbrella target for all Arduino boards that use an H747 chip "STM32H747_ARDUINO": { @@ -3694,42 +3669,10 @@ "image_url": "https://store.arduino.cc/cdn/shop/products/ABX00042_00.iso_1200x900.jpg?v=1675840144" }, "ARDUINO_PORTENTA_H7_M7": { - "inherits": ["ARDUINO_PORTENTA_H7"], - "core": "Cortex-M7FD", - "memory_bank_config": { - // Select flash bank 1 - "IROM1": { - "start": 0x08000000, - "size": 0x100000 - } - }, - "extra_labels_add": [ - "STM32H747xI_CM7" - ], - "macros_add": [ - "CORE_CM7" - ] + "inherits": ["ARDUINO_PORTENTA_H7", "MCU_STM32H747xI_CM7"], }, "ARDUINO_PORTENTA_H7_M4": { - "inherits": ["ARDUINO_PORTENTA_H7"], - "core": "Cortex-M4F", - "memory_bank_config": { - // Select flash bank 2 - "IROM1": { - "start": 0x08100000, - "size": 0x100000 - } - }, - "extra_labels_add": [ - "STM32H747xI_CM4" - ], - "macros_add": [ - "CORE_CM4", - "MBED_MPU_CUSTOM" - ], - "device_has_remove": [ - "MPU" - ] + "inherits": ["ARDUINO_PORTENTA_H7", "MCU_STM32H747xI_CM4"], }, "MCU_STM32H750xB": { "inherits": [ @@ -3742,7 +3685,8 @@ "STM32H7_480MHZ" ], "macros_add": [ - "STM32H750xx" + "STM32H750xx", + "MBED_SPLIT_HEAP" ], "overrides": { "system_power_supply": "PWR_LDO_SUPPLY" @@ -3760,7 +3704,8 @@ "STM32H7_480MHZ" ], "macros_add": [ - "STM32H753xx" + "STM32H753xx", + "MBED_SPLIT_HEAP" ], "overrides": { "system_power_supply": "PWR_LDO_SUPPLY" @@ -3777,14 +3722,10 @@ ], "macros_add": [ "STM32H7A3xxQ", - "STM32H7_280MHZ" + "STM32H7_280MHZ", + "MBED_SPLIT_HEAP" ], - "device_name": "STM32H7A3ZITxQ", - "overrides": { - "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", - // Cannot enable overdrive mode because the default power supply is SMPS - "enable-overdrive-mode": 0 - } + "device_name": "STM32H7A3ZITxQ" }, "NUCLEO_H7A3ZI_Q": { "inherits": [ @@ -3796,6 +3737,11 @@ "detect_code": [ "0860" ], + "overrides": { + "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", + // Cannot enable overdrive mode because the default power supply is SMPS + "enable-overdrive-mode": 0 + }, "image_url": "https://www.st.com/bin/ecommerce/api/image.PF267690.en.feature-description-include-personalized-no-cpn-medium.jpg" }, "MCU_STM32H7B3xIQ": { @@ -3809,7 +3755,8 @@ "STM32H7_280MHZ" ], "macros_add": [ - "STM32H7B3xxQ" + "STM32H7B3xxQ", + "MBED_SPLIT_HEAP" ], "device_name": "STM32H7B3ZITxQ", "overrides": { From 2d54aa565fbe0508d9269465ad8357056a712806 Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Sun, 22 Sep 2024 23:43:04 -0700 Subject: [PATCH 2/7] Fix tabs --- .../STM32H743_STM32H72x_FAMILIES/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt index 62d614aa269..05074c289a3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/linker_scripts/STM32H743_STM32H72x_FAMILIES/CMakeLists.txt @@ -1,8 +1,8 @@ # Copyright (c) 2024 Jamie Smith # SPDX-License-Identifier: Apache-2.0 if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") - mbed_set_linker_script(mbed-stm32h743xi STM32H743_H72x.ld) - mbed_set_linker_script(mbed-stm32h723xg STM32H743_H72x.ld) + mbed_set_linker_script(mbed-stm32h743xi STM32H743_H72x.ld) + mbed_set_linker_script(mbed-stm32h723xg STM32H743_H72x.ld) mbed_set_linker_script(mbed-stm32h725xe STM32H743_H72x.ld) mbed_set_linker_script(mbed-stm32h735xg STM32H743_H72x.ld) mbed_set_linker_script(mbed-stm32h750xb STM32H743_H72x.ld) From 077f48832f854a2fbbb67bbdd644c7e2e9e5dafc Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Thu, 11 Apr 2024 22:11:34 -0700 Subject: [PATCH 3/7] Start on Arduino Giga --- connectivity/lwipstack/mbed_lib.json | 2 +- .../TARGET_ARDUINO_NICLA_SENSE_ME/device.h | 24 +- .../TARGET_STM32H747_ARDUINO/CMakeLists.txt | 3 +- .../TARGET_ARDUINO_GIGA/CMakeLists.txt | 8 + .../TARGET_ARDUINO_GIGA/PinNames.h | 445 ++++++++++++++++++ targets/targets.json5 | 33 ++ .../upload_method_cfg/ARDUINO_GIGA_CM7.cmake | 53 +++ .../openocd_cfgs/stm32h747.cfg | 12 + 8 files changed, 577 insertions(+), 3 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/PinNames.h create mode 100644 targets/upload_method_cfg/ARDUINO_GIGA_CM7.cmake create mode 100644 targets/upload_method_cfg/openocd_cfgs/stm32h747.cfg diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index b39783b582a..85b3e17a04c 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -222,7 +222,7 @@ "MIMXRT105X": { "mem-size": 36560 }, - "PORTENTA_H7": { + "STM32H747_ARDUINO": { "mem-size": 16000 }, "FVP_MPS2_M3": { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h index 4ffd3337994..ee047587421 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h @@ -1,5 +1,8 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited +======= +/* + * Copyright 2024 Arduino SA * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,4 +22,23 @@ #include "objects.h" -#endif \ No newline at end of file +#endif +======= +#include "cyhal_system.h" + +#include "mbed_critical.h" + +uint32_t cyhal_system_critical_section_enter(void) +{ + bool were_interrupts_enabled = !core_util_in_critical_section(); + + core_util_critical_section_enter(); + + return were_interrupts_enabled; +} + +void cyhal_system_critical_section_exit(uint32_t old_state) +{ + (void)old_state; + core_util_critical_section_exit(); +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/CMakeLists.txt index 53b14507191..28947102162 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/CMakeLists.txt @@ -8,4 +8,5 @@ target_link_libraries(mbed-stm32h747-arduino INTERFACE mbed-stm32h747xi-cm7) target_sources(mbed-stm32h747-arduino INTERFACE PeripheralPins.c) -add_subdirectory(TARGET_ARDUINO_PORTENTA_H7) \ No newline at end of file +add_subdirectory(TARGET_ARDUINO_PORTENTA_H7) +add_subdirectory(TARGET_ARDUINO_GIGA) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/CMakeLists.txt new file mode 100644 index 00000000000..f01edcf7687 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/CMakeLists.txt @@ -0,0 +1,8 @@ +add_library(mbed-arduino-giga-cm7 INTERFACE) + +target_include_directories(mbed-arduino-giga-cm7 + INTERFACE + . +) + +target_link_libraries(mbed-arduino-giga-cm7 INTERFACE mbed-stm32h747-arduino) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/PinNames.h new file mode 100644 index 00000000000..0ca8f7cb1fd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747_ARDUINO/TARGET_ARDUINO_GIGA/PinNames.h @@ -0,0 +1,445 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +/* MBED TARGET LIST: GIGA */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUAL_PAD 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0C = PA_0 | DUAL_PAD, // dual pad + PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW + PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW + PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW + PA_1 = 0x01, + PA_1C = PA_1 | DUAL_PAD, // dual pad + PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW + PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW + PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW + PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | DUAL_PAD, // dual pad + PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW + PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW + PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW + PC_3 = 0x23, + PC_3C = PC_3 | DUAL_PAD, // dual pad + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW + PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + WL_REG_ON = PB_10, + WL_HOST_WAKE = PI_8, + WL_SDIO_0 = PC_8, + WL_SDIO_1 = PC_9, + WL_SDIO_2 = PC_10, + WL_SDIO_3 = PC_11, + WL_SDIO_CMD = PD_2, + WL_SDIO_CLK = PC_12, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PB_7, +#endif + + //Led mappings + LED_RED = PI_12, //Red + LED_GREEN = PJ_13, //Green + LED_BLUE = PE_3, //Blue + + CYBSP_BT_UART_RX = PA_8, + CYBSP_BT_UART_TX = PF_7, + CYBSP_BT_UART_RTS = PF_8, + CYBSP_BT_UART_CTS = PF_9, + + CYBSP_BT_POWER = PA_10, + CYBSP_BT_HOST_WAKE = PG_3, + CYBSP_BT_DEVICE_WAKE = PH_7, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = PD_11, + QSPI_FLASH1_IO1 = PD_12, + QSPI_FLASH1_IO2 = PE_2, + QSPI_FLASH1_IO3 = PF_6, + QSPI_FLASH1_SCK = PF_10, + QSPI_FLASH1_CSN = PG_6, + + /**** USB FS pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + + /**** USB HS pins ****/ + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** ETHERNET pins ****/ + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_CRS_DV = PA_7, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RX_CLK = PA_1, + ETH_TXD0 = PG_13, + ETH_TXD1 = PG_12, + ETH_TX_EN = PG_11, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_PVD_IN = PB_7, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED0_ALT0 = PC_1, + SYS_TRACED0_ALT1 = PG_13, + SYS_TRACED1 = PE_4, + SYS_TRACED1_ALT0 = PC_8, + SYS_TRACED1_ALT1 = PG_14, + SYS_TRACED2 = PE_5, + SYS_TRACED2_ALT0 = PD_2, + SYS_TRACED3 = PE_6, + SYS_TRACED3_ALT0 = PC_12, + SYS_TRGIO = PC_7, + SYS_WKUP0 = PA_0, + SYS_WKUP1 = PA_2, + SYS_WKUP2 = PC_13, + SYS_WKUP5 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 LED_RED +#define LED2 LED_GREEN +#define LED3 LED_BLUE +#define BUTTON1 PC_13 + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/targets/targets.json5 b/targets/targets.json5 index 2f738a12003..34dc5d46769 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3648,6 +3648,39 @@ }, "device_name": "STM32H747XIHx" }, + "ARDUINO_GIGA": { + public: false, + inherits: ["STM32H747_ARDUINO"], + overrides: { + system_power_supply: "PWR_LDO_SUPPLY", + "enable-overdrive-mode": 1, + clock_source: "USE_PLL_HSE_XTAL | USE_PLL_HSI", + "network-default-interface-type": "WIFI", + lpuart_clock_source: "USE_LPUART_CLK_HSI", + "hse_value": 16000000 + }, + macros_add: [ + "BT_UART_NO_3M_SUPPORT" + ], + components_add: [ + "QSPIF" + ], + "image_url": "https://store-usa.arduino.cc/cdn/shop/products/ABX00063_00.default_643x483.jpg?v=1677493878" + }, + "ARDUINO_GIGA_CM7": { + inherits: ["ARDUINO_GIGA"], + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size" : "0x100000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size" : "0x80000", + "extra_labels_add": [ + "STM32H747xI_CM7" + ], + "macros_add": [ + "CORE_CM7" + ] + }, "ARDUINO_PORTENTA_H7": { "public": false, "detect_code": ["0813"], diff --git a/targets/upload_method_cfg/ARDUINO_GIGA_CM7.cmake b/targets/upload_method_cfg/ARDUINO_GIGA_CM7.cmake new file mode 100644 index 00000000000..028b19a6225 --- /dev/null +++ b/targets/upload_method_cfg/ARDUINO_GIGA_CM7.cmake @@ -0,0 +1,53 @@ +# Mbed OS upload method configuration file for target ARDUINO_GIGA_CM7. +# To change any of these parameters from their default values, set them in your build script between where you +# include app.cmake and where you add mbed os as a subdirectory. + +# Notes: +# 1. To use this target with PyOCD, you need to install a pack: `pyocd pack install STM32H747XIHx`. +# You might also need to run `pyocd pack update` first. + +# General config parameters +# ------------------------------------------------------------- +set(UPLOAD_METHOD_DEFAULT MBED) + +# Config options for MBED +# ------------------------------------------------------------- + +set(MBED_UPLOAD_ENABLED TRUE) +set(MBED_RESET_BAUDRATE 115200) + +# Config options for JLINK +# ------------------------------------------------------------- + +set(JLINK_UPLOAD_ENABLED FALSE) +set(JLINK_CPU_NAME STM32H743ZI) +set(JLINK_CLOCK_SPEED 4000) +set(JLINK_UPLOAD_INTERFACE SWD) + +# Config options for PYOCD +# ------------------------------------------------------------- + +set(PYOCD_UPLOAD_ENABLED TRUE) +set(PYOCD_TARGET_NAME STM32H747XIHx) +set(PYOCD_CLOCK_SPEED 4000k) + +# Config options for OPENOCD +# ------------------------------------------------------------- + +set(OPENOCD_UPLOAD_ENABLED TRUE) +set(OPENOCD_CHIP_CONFIG_COMMANDS + -f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/stm32h747.cfg) + +# Config options for STM32Cube +# ------------------------------------------------------------- + +set(STM32CUBE_UPLOAD_ENABLED TRUE) +set(STM32CUBE_CONNECT_COMMAND -c port=SWD reset=HWrst) +set(STM32CUBE_GDBSERVER_ARGS --swd --initialize-reset --apid 0) + +# Config options for stlink +# ------------------------------------------------------------- + +set(STLINK_UPLOAD_ENABLED TRUE) +set(STLINK_LOAD_ADDRESS 0x8000000) +set(STLINK_ARGS --connect-under-reset) diff --git a/targets/upload_method_cfg/openocd_cfgs/stm32h747.cfg b/targets/upload_method_cfg/openocd_cfgs/stm32h747.cfg new file mode 100644 index 00000000000..5681ebd8dab --- /dev/null +++ b/targets/upload_method_cfg/openocd_cfgs/stm32h747.cfg @@ -0,0 +1,12 @@ +source [find interface/stlink-dap.cfg] +transport select dapdirect_swd + +# STM32H747xx devices are dual core (Cortex-M7 and Cortex-M4) +set DUAL_CORE 0 + +# enable CTI for cross halting both cores +set USE_CTI 0 + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only From 19762981cf1f2978862fb4fddbcd45f260082f2e Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Sat, 22 Jun 2024 14:06:14 -0700 Subject: [PATCH 4/7] Fix QSPI flash, add option to use DMA in circular mode --- .../COMPONENT_QSPIF/{mbed_lib.json => mbed_lib.json5} | 6 ++++++ targets/TARGET_STM/qspi_api.c | 4 ++-- targets/TARGET_STM/stm_dma_utils.c | 5 ++--- targets/TARGET_STM/stm_dma_utils.h | 5 +++-- targets/TARGET_STM/stm_spi_api.c | 4 ++-- targets/targets.json5 | 8 +++++++- 6 files changed, 22 insertions(+), 10 deletions(-) rename storage/blockdevice/COMPONENT_QSPIF/{mbed_lib.json => mbed_lib.json5} (88%) diff --git a/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json b/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json5 similarity index 88% rename from storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json rename to storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json5 index b8082723fe7..484cf77b702 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json +++ b/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json5 @@ -54,6 +54,12 @@ "MCU_LPC546XX": { "QSPI_MIN_READ_SIZE": "4", "QSPI_MIN_PROG_SIZE": "4" + }, + "ARDUINO_GIGA": { + "QSPI_POLARITY_MODE": "QSPIF_POLARITY_MODE_1", + // The flash on this board (AT25SF128A) is quite old and does not have reset information in its + // SFDP table. + "enable-and-reset": true } } } diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index c84a4b59ec1..5951162c6eb 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -234,7 +234,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm #else /* OCTOSPI */ qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st_command) { - debug_if(qspi_api_c_debug, "qspi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n", + debug_if(qspi_api_c_debug, "qspi_prepare_command In: instruction.value 0x%" PRIx8 " dummy_count 0x%" PRIx8 " address.bus_width 0x%x address.disabled %d address.value 0x%" PRIx32 " address.size %x\n", command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); // TODO: shift these around to get more dynamic mapping @@ -372,7 +372,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTy st_command->NbData = 0; - debug_if(qspi_api_c_debug, "qspi_prepare_command Out: InstructionMode %x Instruction %x AddressMode %x AddressSize %x Address %x DataMode %x\n", + debug_if(qspi_api_c_debug, "qspi_prepare_command Out: InstructionMode 0x%" PRIx32 " Instruction 0x%" PRIx32 " AddressMode 0x%" PRIx32 " AddressSize 0x%" PRIx32 " Address 0x%" PRIx32 " DataMode %" PRIx32 "\n", st_command->InstructionMode, st_command->Instruction, st_command->AddressMode, st_command->AddressSize, st_command->Address, st_command->DataMode); return QSPI_STATUS_OK; diff --git a/targets/TARGET_STM/stm_dma_utils.c b/targets/TARGET_STM/stm_dma_utils.c index c72dbaac12a..79df72a3799 100644 --- a/targets/TARGET_STM/stm_dma_utils.c +++ b/targets/TARGET_STM/stm_dma_utils.c @@ -572,7 +572,7 @@ DMA_HandleTypeDef *stm_get_dma_handle_for_link(DMALinkInfo const * dmaLink) } DMA_HandleTypeDef *stm_init_dma_link(const DMALinkInfo *dmaLink, uint32_t direction, bool periphInc, bool memInc, - uint8_t periphDataAlignment, uint8_t memDataAlignment){ + uint8_t periphDataAlignment, uint8_t memDataAlignment, uint32_t mode){ #ifdef DMA_IP_VERSION_V2 // Channels start from 1 in IP v2 only @@ -640,6 +640,7 @@ DMA_HandleTypeDef *stm_init_dma_link(const DMALinkInfo *dmaLink, uint32_t direct #endif dmaHandle->Init.Direction = direction; + dmaHandle->Init.Mode = mode; // IP v3 uses different fields for... basically everything in this struct #ifdef DMA_IP_VERSION_V3 @@ -761,8 +762,6 @@ DMA_HandleTypeDef *stm_init_dma_link(const DMALinkInfo *dmaLink, uint32_t direct #endif - dmaHandle->Init.Mode = DMA_NORMAL; - HAL_DMA_Init(dmaHandle); // Set up interrupt diff --git a/targets/TARGET_STM/stm_dma_utils.h b/targets/TARGET_STM/stm_dma_utils.h index 16a549bf0cd..c398818afef 100644 --- a/targets/TARGET_STM/stm_dma_utils.h +++ b/targets/TARGET_STM/stm_dma_utils.h @@ -122,12 +122,13 @@ DMA_HandleTypeDef * stm_get_dma_handle_for_link(DMALinkInfo const * dmaLink); * @param periphInc Whether the Peripheral address register should be incremented or not. * @param memInc Whether the Memory address register should be incremented or not. * @param periphDataAlignment Alignment value of the peripheral data. 1, 2, or 4. - * @param memDataAlignment \c DMA_MDATAALIGN_BYTE, \c DMA_MDATAALIGN_HALFWORD, or \c DMA_MDATAALIGN_WORD + * @param memDataAlignment Alignment value of the memory data. 1, 2, or 4. + * @param mode Mode of the DMA transaction. DMA_NORMAL, DMA_CIRCULAR, etc * * @return Pointer to DMA handle allocated by this module. * @return NULL if the DMA channel used by the link has already been allocated by something else. */ -DMA_HandleTypeDef * stm_init_dma_link(DMALinkInfo const * dmaLink, uint32_t direction, bool periphInc, bool memInc, uint8_t periphDataAlignment, uint8_t memDataAlignment); +DMA_HandleTypeDef * stm_init_dma_link(DMALinkInfo const * dmaLink, uint32_t direction, bool periphInc, bool memInc, uint8_t periphDataAlignment, uint8_t memDataAlignment, uint32_t mode); /** * @brief Free a DMA link. diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index e5a969f906f..d849a01d1ab 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -541,7 +541,7 @@ static void spi_init_tx_dma(struct spi_s * obj) DMALinkInfo const *dmaLink = &SPITxDMALinks[obj->spiIndex - 1]; // Initialize DMA channel - DMA_HandleTypeDef *dmaHandle = stm_init_dma_link(dmaLink, DMA_MEMORY_TO_PERIPH, false, true, 1, 1); + DMA_HandleTypeDef *dmaHandle = stm_init_dma_link(dmaLink, DMA_MEMORY_TO_PERIPH, false, true, 1, 1, DMA_NORMAL); if(dmaHandle == NULL) { @@ -574,7 +574,7 @@ static void spi_init_rx_dma(struct spi_s * obj) DMALinkInfo const *dmaLink = &SPIRxDMALinks[obj->spiIndex - 1]; // Initialize DMA channel - DMA_HandleTypeDef *dmaHandle = stm_init_dma_link(dmaLink, DMA_PERIPH_TO_MEMORY, false, true, 1, 1); + DMA_HandleTypeDef *dmaHandle = stm_init_dma_link(dmaLink, DMA_PERIPH_TO_MEMORY, false, true, 1, 1, DMA_NORMAL); if(dmaHandle == NULL) { diff --git a/targets/targets.json5 b/targets/targets.json5 index 34dc5d46769..5eaba82ee93 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3657,7 +3657,13 @@ clock_source: "USE_PLL_HSE_XTAL | USE_PLL_HSI", "network-default-interface-type": "WIFI", lpuart_clock_source: "USE_LPUART_CLK_HSI", - "hse_value": 16000000 + "hse_value": 16000000, + + // Arduino Giga connects the primary USB port (USB-C port) to the USB Full Speed pins. + // TODO eventually this needs to be runtime configurable so that the two USB ports + // can use different speeds. With the current setting, Mbed will not be able to use + // the host mode port as that port uses high speed. + "usb_speed": "USE_USB_OTG_FS", }, macros_add: [ "BT_UART_NO_3M_SUPPORT" From 443191c99e276a571398a33a52837ba99968b374 Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Mon, 29 Jul 2024 09:26:03 -0700 Subject: [PATCH 5/7] Fix wifi driver build, add an option to just include the wifi firmware in the image --- .../minimal-cyhal/CMakeLists.txt | 2 +- .../wiced_filesystem_setup.cpp | 3 +++ .../minimal-cyhal/cyhal_gpio.cpp | 2 +- .../minimal-cyhal/wiced_filesystem.h | 4 ++-- .../firmware/COMPONENT_4343W_FS/4343WA1_bin.c | 7 +++++- drivers/CMakeLists.txt | 2 +- .../cy_rtos_rtx_adapter/CMakeLists.txt | 2 +- .../TARGET_ARDUINO_NICLA_SENSE_ME/device.h | 24 +------------------ targets/targets.json5 | 4 ++++ 9 files changed, 20 insertions(+), 30 deletions(-) diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/CMakeLists.txt b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/CMakeLists.txt index d93dffad41d..96a009a5c27 100644 --- a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/CMakeLists.txt +++ b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/CMakeLists.txt @@ -16,7 +16,7 @@ add_library(mbed-minimal-cyhal STATIC target_include_directories(mbed-minimal-cyhal PUBLIC .) target_link_libraries(mbed-minimal-cyhal PUBLIC mbed-core-flags - mbed-cy-rtos-abstraction) + mbed-rtos-flags) # This is needed in order to make cybsp_wifi.h include cycfg.h target_compile_definitions(mbed-minimal-cyhal PUBLIC COMPONENT_CUSTOM_DESIGN_MODUS) diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/TARGET_STM32H7/TARGET_STM32H747_ARDUINO/wiced_filesystem_setup.cpp b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/TARGET_STM32H7/TARGET_STM32H747_ARDUINO/wiced_filesystem_setup.cpp index 2105cd368b7..067462d3673 100644 --- a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/TARGET_STM32H7/TARGET_STM32H747_ARDUINO/wiced_filesystem_setup.cpp +++ b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/TARGET_STM32H7/TARGET_STM32H747_ARDUINO/wiced_filesystem_setup.cpp @@ -58,6 +58,8 @@ MBED_WEAK wiced_result_t whd_firmware_check_hook(const char *mounted_name, int m return WICED_ERROR; } +wiced_filesystem_t resource_fs_handle = 0; + wiced_result_t wiced_filesystem_setup() { static QSPIFBlockDevice *qspi_bd = nullptr; @@ -82,6 +84,7 @@ wiced_result_t wiced_filesystem_setup() mbr_bd = new mbed::MBRBlockDevice(qspi_bd, WIFI_DEFAULT_PARTITION); if(mbr_bd->init() != mbed::BD_ERROR_OK) { + whd_firmware_check_hook(WIFI_DEFAULT_MOUNT_NAME, true); delete mbr_bd; mbr_bd = nullptr; return WICED_ERROR; diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/cyhal_gpio.cpp b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/cyhal_gpio.cpp index bdaec7df42c..1ea82d2e123 100644 --- a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/cyhal_gpio.cpp +++ b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/cyhal_gpio.cpp @@ -22,7 +22,7 @@ #include #include "cyhal.h" #include "cybsp.h" -#include "drivers/DigitalIn.h" +#include "drivers/DigitalOut.h" #include "drivers/InterruptIn.h" #include diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/wiced_filesystem.h b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/wiced_filesystem.h index 436e36701f1..b110ab43fdf 100644 --- a/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/wiced_filesystem.h +++ b/connectivity/drivers/wifi/COMPONENT_WHD/minimal-cyhal/wiced_filesystem.h @@ -76,9 +76,9 @@ typedef int wiced_file_t; */ typedef int wiced_filesystem_handle_type_t; -// Global "FS handle" object. Just here to match the WHD driver's expectations, we have one global +// Global "FS handle" object. Just here to match the WHD driver's expectations, we in fact have one global // filesystem object. -static wiced_filesystem_t resource_fs_handle = 0; +extern wiced_filesystem_t resource_fs_handle; /** * @brief Sets up the file system where the wifi module resources will be loaded from. diff --git a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c index ddaf0f7188f..08d3805da7d 100644 --- a/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c +++ b/connectivity/drivers/wifi/COMPONENT_WHD/wifi-host-driver/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c @@ -14,6 +14,7 @@ * limitations under the License. */ #include "wiced_resource.h" +#include "mbed-target-config.h" #if defined(CY_STORAGE_WIFI_DATA) CY_SECTION_WHD(CY_STORAGE_WIFI_DATA) __attribute__((used)) @@ -25489,5 +25490,9 @@ const unsigned char wifi_firmware_image_data[421098] = { 49, 45, 53, 97, 102, 99, 56, 99, 49, 101, 0, 254, 0, 68, 86, 73, 68, 32, 48, 49, 45, 101, 100, 48, 100, 55, 97, 53, 54 }; -resource_hnd_t wifi_firmware_image = { RESOURCE_IN_EXTERNAL_STORAGE, 421098, {.fs = { 0, "/wlan/4343WA1.BIN" }}}; +#if MBED_CONF_TARGET_WIFI_DRIVER_IN_QSPI_FLASH +resource_hnd_t wifi_firmware_image = { RESOURCE_IN_EXTERNAL_STORAGE, 421098, {.fs = { 0, "/wlan/4343WA1.BIN" }}}; +#else +const resource_hnd_t wifi_firmware_image = { RESOURCE_IN_MEMORY, 421098, {.mem = { (const char *) wifi_firmware_image_data }}}; +#endif diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index d74e1eb5937..ebd89bc7904 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -14,7 +14,7 @@ target_include_directories(mbed-core-flags . ./include ./include/drivers - ./include/drivers/internal + ./include/drivers/interfaces ) target_sources(mbed-core-sources diff --git a/features/frameworks/cy_rtos_rtx_adapter/CMakeLists.txt b/features/frameworks/cy_rtos_rtx_adapter/CMakeLists.txt index 0e61b65b2d4..c6e912759ca 100644 --- a/features/frameworks/cy_rtos_rtx_adapter/CMakeLists.txt +++ b/features/frameworks/cy_rtos_rtx_adapter/CMakeLists.txt @@ -19,6 +19,6 @@ else() # Build as part of the minimal CyHAL if it's enabled if(TARGET mbed-minimal-cyhal) target_sources(mbed-minimal-cyhal PRIVATE ${CY_RTOS_RTX_ADAPTER_SOURCES}) - target_include_directories(mbed-minimal-cyhal INTERFACE ${CY_RTOS_RTX_ADAPTER_INCLUDE_DIRS}) + target_include_directories(mbed-minimal-cyhal PUBLIC ${CY_RTOS_RTX_ADAPTER_INCLUDE_DIRS}) endif() endif() diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h index ee047587421..4ffd3337994 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_ARDUINO_NICLA_SENSE_ME/device.h @@ -1,8 +1,5 @@ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited -======= -/* - * Copyright 2024 Arduino SA * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,23 +19,4 @@ #include "objects.h" -#endif -======= -#include "cyhal_system.h" - -#include "mbed_critical.h" - -uint32_t cyhal_system_critical_section_enter(void) -{ - bool were_interrupts_enabled = !core_util_in_critical_section(); - - core_util_critical_section_enter(); - - return were_interrupts_enabled; -} - -void cyhal_system_critical_section_exit(uint32_t old_state) -{ - (void)old_state; - core_util_critical_section_exit(); -} +#endif \ No newline at end of file diff --git a/targets/targets.json5 b/targets/targets.json5 index 5eaba82ee93..0fbae633913 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3618,6 +3618,10 @@ "usb_speed": { "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", "value": "USE_USB_OTG_HS" + }, + "wifi_driver_in_qspi_flash": { + help: "If this is false, and wifi is used in the application, the wifi chip firmware will be included in the application firmware (+411kiB code size). If true, then the wifi firmware is loaded from the external QSPI flash instead, and you must install it using the Arduino IDE sketch for this purpose.", + value: false } }, "components_add": [ From 85e8d69dab8192dc97e319bffc781e6cea217223 Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Mon, 26 Aug 2024 09:18:22 -0700 Subject: [PATCH 6/7] Add memory bank config --- targets/targets.json5 | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/targets/targets.json5 b/targets/targets.json5 index 0fbae633913..46c2982fa29 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3680,10 +3680,13 @@ "ARDUINO_GIGA_CM7": { inherits: ["ARDUINO_GIGA"], "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size" : "0x100000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size" : "0x80000", + "memory_bank_config": { + // Select flash bank 1 + "IROM1": { + "start": 0x08000000, + "size": 0x100000 + } + }, "extra_labels_add": [ "STM32H747xI_CM7" ], From 3fdad83a0922936777dd4aa034e66a0a4e456591 Mon Sep 17 00:00:00 2001 From: Jamie Smith Date: Mon, 23 Sep 2024 09:11:40 -0700 Subject: [PATCH 7/7] Update targets JSON to new format for dual core devices --- targets/targets.json5 | 52 ++++++++++--------------------------------- 1 file changed, 12 insertions(+), 40 deletions(-) diff --git a/targets/targets.json5 b/targets/targets.json5 index 46c2982fa29..d19a712c1f6 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3561,20 +3561,13 @@ "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY", // Cannot enable overdrive mode because the default power supply is SMPS "enable-overdrive-mode": 0 - } - }, - "DISCO_H747I_CM7": { - "inherits": [ - "MCU_STM32H747xI_CM7", - "DISCO_H747" - ], + }, "supported_form_factors": [ "ARDUINO_UNO", "STMOD", "PMOD" ], "extra_labels_add": [ - "DISCO_H747I", "MT25QL512" ], "components_add": [ @@ -3588,27 +3581,17 @@ ], "device_name": "STM32H747XIHx" }, + "DISCO_H747I_CM7": { + "inherits": [ + "MCU_STM32H747xI_CM7", + "DISCO_H747" + ] + }, "DISCO_H747I_CM4": { "inherits": [ "MCU_STM32H747xI_CM4", "DISCO_H747" - ], - "extra_labels_add": [ - "DISCO_H747I", - "MT25QL512" - ], - "device_has_add": [ - "QSPI" - ], - "components_add": [ - "QSPIF" - ], - "supported_form_factors": [ - "ARDUINO_UNO", - "STMOD", - "PMOD" - ], - "device_name": "STM32H747XIHx" + ] }, // Umbrella target for all Arduino boards that use an H747 chip "STM32H747_ARDUINO": { @@ -3678,21 +3661,10 @@ "image_url": "https://store-usa.arduino.cc/cdn/shop/products/ABX00063_00.default_643x483.jpg?v=1677493878" }, "ARDUINO_GIGA_CM7": { - inherits: ["ARDUINO_GIGA"], - "core": "Cortex-M7FD", - "memory_bank_config": { - // Select flash bank 1 - "IROM1": { - "start": 0x08000000, - "size": 0x100000 - } - }, - "extra_labels_add": [ - "STM32H747xI_CM7" - ], - "macros_add": [ - "CORE_CM7" - ] + inherits: ["MCU_STM32H747xI_CM7", "ARDUINO_GIGA"], + }, + "ARDUINO_GIGA_CM4": { + inherits: ["MCU_STM32H747xI_CM4", "ARDUINO_GIGA"], }, "ARDUINO_PORTENTA_H7": { "public": false,