Adjust add instructions with constant to leverage indexed loads and stores

[vladimirradosavljevic]

EraVM indexed load and store instructions are doing post increment if we have add by 32 to the base address. To leverage indexed load and store instructions, we can try to find add instructions with constant and to adjust them by changing first operand to be the base address of the load or store instruction and second operand to be 32 constant, if that is feasible. In that case, indexed load and store instructions will be generated, and add instruction will be removed.
For the following case:

define i256 @test(i256 %a) {
entry:
  %add1 = add i256 %a, 1
  %inttoptr1 = inttoptr i256 %add1 to ptr addrspace(1)
  store i256 0, ptr addrspace(1) %inttoptr1, align 1
  br label %bb1

bb1:
  %add2 = add i256 %a, 33
  %inttoptr2 = inttoptr i256 %add2 to ptr addrspace(1)
  store i256 0, ptr addrspace(1) %inttoptr2, align 1
  ret i256 0
}

following assembly is generated:

test:                                   ; @test
; %bb.0:                                ; %entry
	add	1, r1, r2
	stm.h	r2, r0
	add	33, r1, r1
	stm.h	r1, r0
	add	r0, r0, r1
	ret

If we do the following (adjust %add2 to be add with 32 by changing %a operand to %add1):

define i256 @test(i256 %a) {
entry:
  %add1 = add i256 %a, 1
  %inttoptr1 = inttoptr i256 %add1 to ptr addrspace(1)
  store i256 0, ptr addrspace(1) %inttoptr1, align 1
  br label %bb1

bb1:
  %add2 = add i256 %add1, 32
  %inttoptr2 = inttoptr i256 %add2 to ptr addrspace(1)
  store i256 0, ptr addrspace(1) %inttoptr2, align 1
  ret i256 0
}

we can generate indexed store and get following assembly:

test:                                   ; @test
; %bb.0:                                ; %entry
	add	1, r1, r1
	stmi.h	r1, r0, r1
	stm.h	r1, r0
	add	r0, r0, r1
	ret

One option to do this is to create MIR pass that will do this transformation. Also, it would be good to check how to leverage DAG optimizations to generate POST_INC MemIndexedMode, like other architectures are doing (e.g. AArch64).