diff --git a/hdlagent/agent.py b/hdlagent/agent.py
index b96a5ec5..a38c18cb 100644
--- a/hdlagent/agent.py
+++ b/hdlagent/agent.py
@@ -866,7 +866,7 @@ def test_code_compile(self):
         # Run the compile command
         res = subprocess.run(command, capture_output=True, shell=True, text=True)
     
-        print(f"[DEBUG] test_code_compile: stdout = {res.stdout}")
+        # print(f"[DEBUG] test_code_compile: stdout = {res.stdout}")
         # print(f"[DEBUG] test_code_compile: stderr = {res.stderr}")
     
         errors = self.check_errors(res)
@@ -1036,7 +1036,6 @@ def tb_loop(self, prompt: str, iterations: int = 1, designer: 'Agent' = None, co
     def code_compilation_loop(self, prompt: str, lec_iteration: int = 0, iterations: int = 1):
         if not isinstance(self.code, Path):
             self.code = Path(self.code)
-        
         if lec_iteration == 0:
             current_query = self.get_compile_initial_instruction(prompt)
         else:
@@ -1048,9 +1047,10 @@ def code_compilation_loop(self, prompt: str, lec_iteration: int = 0, iterations:
             codeblock = self.query_model(self.compile_conversation, current_query, True)
             self.dump_codeblock(codeblock, self.code)
             compile_out = self.test_code_compile()
-            print(f"[DEBUG] test_code_compile returned: {compile_out}")
+            # print(f"[DEBUG] test_code_compile returned: {compile_out}")
             if compile_out is not None:
                 current_query = self.get_compile_iteration_instruction(compile_out)
+                # continue
             else:
                 return True, None
         return False, compile_out
@@ -1062,7 +1062,6 @@ def code_compilation_loop(self, prompt: str, lec_iteration: int = 0, iterations:
     # Intended use: user facing RTL generation
     def spec_run_loop(self, prompt: str, iterations: int = 1, continued: bool = False, update: bool = False):
         if not continued:   # Maintain conversation history when iterating over design
-            print("00000000reset all the counter here.")
             self.reset_conversations()
             self.reset_perf_counters()
         if update:
@@ -1071,7 +1070,6 @@ def spec_run_loop(self, prompt: str, iterations: int = 1, continued: bool = Fals
             return self.finish_run(failure_reason)
         # print(f"spec_run_loop (end): self.name = {self.name}")
         compiled, failure_reason = self.code_compilation_loop(prompt, 0, iterations)
-        print(f"/////////compiled=", compiled, "failure_reason=",failure_reason)
         # self.finish_run(failure_reason)
         # return self.finish_run(self.code_compilation_loop(prompt, 0, iterations)[1])
         return compiled
@@ -1145,21 +1143,13 @@ def lec_loop(self, prompt: str, compiled: bool = False, lec_iterations: int = 5,
                 prompt = self.get_lec_fail_instruction(self.prev_test_cases, failure_reason, lec_feedback_limit)
                 compiled, failure_reason = self.code_compilation_loop(prompt, i+1, compile_iterations)
                 #the new code has to compiled and see if it compiled or not if it compiled, it has to pass the lec agin
-                print("***********comipled:", compiled, "failure_reason:", failure_reason)
-                if compiled:
-                    #it means that after i lec loop it generate the code that pass the compilation and now it needs to pass the lec agein
-                    pass
-                else:
-                    print(f"[DEBUG] Compilation failed after:", i, "with this reasson:", failure_reason)
+                if not compiled:
                     return self.finish_run(failure_reason)
             else:
                 print("[DEBUG] LEC passed successfully.")
                 return self.finish_run(failure_reason)
             if i == lec_iterations - 1:
-                print("It has to be the last lec loop--------------")
-                lec_out = self.test_lec(gold, gate, lec_feedback_limit)
                 if lec_out is not None:
-                    print("last failure_reason:", failure_reason)
                     test_fail_count, failure_reason = lec_out.split('\n', 1)
                     return self.finish_run(failure_reason)
         return self.finish_run(failure_reason)
diff --git a/hdlagent/cli_agent.py b/hdlagent/cli_agent.py
index 794b676b..889a089f 100755
--- a/hdlagent/cli_agent.py
+++ b/hdlagent/cli_agent.py
@@ -89,8 +89,8 @@ def bench(args):
 
             for f in args.file_list:
                 my_handler.spec_run(target_spec=f, iterations=args.comp_limit)
-            # print(f"Processing YAML file: {yaml_file}")
-            return
+                print(f"Processing YAML file: {yaml_file}")
+            
         # print(f"Processing YAML file: {benchmark_file}")
         my_handler.spec_run(target_spec=benchmark_file, iterations=args.comp_limit)
 
diff --git a/sample/wb_converter.yaml b/sample/wb_converter.yaml
new file mode 100644
index 00000000..2742bdf6
--- /dev/null
+++ b/sample/wb_converter.yaml
@@ -0,0 +1,56 @@
+description: 'Develop a `wb_converter` module to interface between a Wishbone bus and a processing unit, supporting both instruction and data transactions. The module utilizes inputs such as `wb_clk_i` (clock signal), `wb_rst_i` (reset signal), `wbs_stb_i` (strobe signal indicating a valid transaction), `wbs_cyc_i` (cycle signal for bus transaction duration), `wbs_we_i` (write enable signal), `wbs_sel_i` (byte select signals), `wbs_dat_i` (input data from the bus), and `wbs_adr_i` (address input from the bus). It outputs `wbs_ack_o` (acknowledge signal), `wbs_dat_o` (data output for read operations), alongside custom interface signals: `load_recv_msg` (64-bit data for load operations), `load_recv_val` (validation signal for load operations), `instruction_recv_msg` (32-bit data for instruction operations), `instruction_recv_val` (validation signal for instruction operations), and `store_send_rdy` (readiness signal for store operations). Operational logic is as follows: for address `0x30000000`, forward `wbs_dat_i` to `instruction_recv_msg`; for addresses `>= 0x30000004`, adjust the address by subtracting `0x30000004` and use it to form `load_recv_msg` for data transactions, while setting `instruction_recv_msg` to indicate VSTORE (read operation) or VLOAD (write operation) based on `wbs_we_i`. Acknowledgments and data flow control are managed according to the address, operation type, and the processing unit''s readiness, ensuring smooth communication between the Wishbone bus and the processing unit. This module is crucial for data and instruction transaction management, adapting signals for appropriate handling based on the current operation, thereby facilitating effective data and instruction flow between the bus and the processing unit.        '
+interface: |-
+  module wb_converter (input wb_clk_i, input wb_rst_i, input wbs_stb_i, input wbs_cyc_i, input wbs_we_i, input [3:0] wbs_sel_i, input [31:0] wbs_dat_i, input [31:0] wbs_adr_i, output logic wbs_ack_o, output [31:0] wbs_dat_o, output logic [63:0] load_recv_msg, output logic load_recv_val, input load_recv_rdy, output logic [31:0] instruction_recv_msg, output logic instruction_recv_val, input instruction_recv_rdy, input [31:0] store_send_msg, input store_send_val, output logic store_send_rdy);
+bench_response: |-
+  module wb_converter (
+      input wb_clk_i,
+      input wb_rst_i,
+      input wbs_stb_i,
+      input wbs_cyc_i,
+      input wbs_we_i,
+      input [3:0] wbs_sel_i,
+      input [31:0] wbs_dat_i,
+      input [31:0] wbs_adr_i,
+      output logic wbs_ack_o,
+      output [31:0] wbs_dat_o,
+
+      output logic [63:0] load_recv_msg,
+      output logic load_recv_val,
+      input load_recv_rdy,
+
+      output logic [31:0] instruction_recv_msg,
+      output logic instruction_recv_val,
+      input instruction_recv_rdy,
+
+      input [31:0] store_send_msg,
+      input store_send_val,
+      output logic store_send_rdy
+  );
+
+      assign wbs_ack_o = wbs_cyc_i && wbs_stb_i && 
+                         ((wbs_adr_i == 32'h30000000 && instruction_recv_rdy) || 
+                         ((wbs_adr_i > 32'h30000000) && (!wbs_we_i && store_send_val && store_send_rdy)) ||
+                         ((wbs_adr_i > 32'h30000000) && wbs_we_i && load_recv_rdy && instruction_recv_rdy));
+      assign store_send_rdy = !wbs_we_i && wbs_cyc_i && wbs_stb_i && (wbs_adr_i > 32'h30000000);
+      assign wbs_dat_o = store_send_msg;
+
+      always_comb begin
+               load_recv_msg = 64'b0;
+          load_recv_val = 0;
+          instruction_recv_msg = 32'b0;
+          instruction_recv_val = 0;
+
+          if (wbs_adr_i == 32'h30000000) begin
+                         instruction_recv_msg = wbs_dat_i;
+              instruction_recv_val = wbs_cyc_i && wbs_stb_i;
+          end else if (wbs_adr_i > 32'h30000000) begin
+        load_recv_msg = {(wbs_adr_i - 32'h30000004) >> 2, wbs_dat_i};            load_recv_val = wbs_cyc_i && wbs_stb_i;
+              if (wbs_we_i) begin
+              instruction_recv_msg = {5'b00000, 27'b0};           end else begin
+                  instruction_recv_msg = {5'b00001, 27'b0};         end
+              instruction_recv_val = wbs_cyc_i && wbs_stb_i;
+          end
+      end
+
+  endmodule
+bench_stage: '1'