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[chip-test] sleep_pin_wake inconsistent flow between DV and SiVal #25426

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luismarques opened this issue Nov 27, 2024 · 0 comments
Open
1 of 3 tasks

[chip-test] sleep_pin_wake inconsistent flow between DV and SiVal #25426

luismarques opened this issue Nov 27, 2024 · 0 comments
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Component:ChipLevelTest Used to filter the chip-level test backlog

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luismarques commented Nov 27, 2024 •
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Test point name

chip_sw_sleep_pin_wake

Host side component

SystemVerilog+Rust

OpenTitanTool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation Targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

luismarques

Description

The test chip_sw_sleep_pin_wake has inconsistent flow between DV and SiVal. In DV, make the vseq choose the sequence and communicate it to the vseq via backdoor symbol overwrites (to the same variables that sival uses).

See #25365 (review)
@luismarques luismarques added the Component:ChipLevelTest Used to filter the chip-level test backlog label Nov 27, 2024
@luismarques luismarques self-assigned this Nov 27, 2024
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@luismarques