diff --git a/testfiles/tb/golden_files/all1_insta_all.vhdl b/testfiles/tb/golden_files/all1_insta_all.vhdl index 5ebd4df5..121fff7d 100644 --- a/testfiles/tb/golden_files/all1_insta_all.vhdl +++ b/testfiles/tb/golden_files/all1_insta_all.vhdl @@ -212,8 +212,13 @@ begin if rising_edge(clock) then if resetn = '0' then rd_req_d0 <= '0'; + rd_adr_d0 <= "0000000000000"; rd_ack <= '0'; + rd_data <= "00000000000000000000000000000000"; wr_req_d0 <= '0'; + wr_adr_d0 <= "0000000000000"; + wr_dat_d0 <= "00000000000000000000000000000000"; + wr_sel_d0 <= "00000000000000000000000000000000"; wr_ack <= '0'; else rd_req_d0 <= rd_req; diff --git a/testfiles/tb/golden_files/all1_insta_in,out.vhdl b/testfiles/tb/golden_files/all1_insta_in,out.vhdl index 5ebd4df5..121fff7d 100644 --- a/testfiles/tb/golden_files/all1_insta_in,out.vhdl +++ b/testfiles/tb/golden_files/all1_insta_in,out.vhdl @@ -212,8 +212,13 @@ begin if rising_edge(clock) then if resetn = '0' then rd_req_d0 <= '0'; + rd_adr_d0 <= "0000000000000"; rd_ack <= '0'; + rd_data <= "00000000000000000000000000000000"; wr_req_d0 <= '0'; + wr_adr_d0 <= "0000000000000"; + wr_dat_d0 <= "00000000000000000000000000000000"; + wr_sel_d0 <= "00000000000000000000000000000000"; wr_ack <= '0'; else rd_req_d0 <= rd_req; diff --git a/testfiles/tb/golden_files/all1_insta_in.vhdl b/testfiles/tb/golden_files/all1_insta_in.vhdl index 45b96bd5..17397d80 100644 --- a/testfiles/tb/golden_files/all1_insta_in.vhdl +++ b/testfiles/tb/golden_files/all1_insta_in.vhdl @@ -209,7 +209,11 @@ begin if rising_edge(clock) then if resetn = '0' then rd_req_d0 <= '0'; + rd_adr_d0 <= "0000000000000"; wr_req_d0 <= '0'; + wr_adr_d0 <= "0000000000000"; + wr_dat_d0 <= "00000000000000000000000000000000"; + wr_sel_d0 <= "00000000000000000000000000000000"; else rd_req_d0 <= rd_req; rd_adr_d0 <= rd_addr; diff --git a/testfiles/tb/golden_files/all1_insta_out.vhdl b/testfiles/tb/golden_files/all1_insta_out.vhdl index 109958a3..5a4ea425 100644 --- a/testfiles/tb/golden_files/all1_insta_out.vhdl +++ b/testfiles/tb/golden_files/all1_insta_out.vhdl @@ -206,6 +206,7 @@ begin if rising_edge(clock) then if resetn = '0' then rd_ack <= '0'; + rd_data <= "00000000000000000000000000000000"; wr_ack <= '0'; else rd_ack <= rd_ack_d0; diff --git a/testfiles/tb/golden_files/all1_insta_rd-in,wr-out.vhdl b/testfiles/tb/golden_files/all1_insta_rd-in,wr-out.vhdl index e319ac6c..17c229c1 100644 --- a/testfiles/tb/golden_files/all1_insta_rd-in,wr-out.vhdl +++ b/testfiles/tb/golden_files/all1_insta_rd-in,wr-out.vhdl @@ -206,6 +206,7 @@ begin if rising_edge(clock) then if resetn = '0' then rd_req_d0 <= '0'; + rd_adr_d0 <= "0000000000000"; wr_ack <= '0'; else rd_req_d0 <= rd_req; diff --git a/testfiles/tb/golden_files/all1_insta_rd-in.vhdl b/testfiles/tb/golden_files/all1_insta_rd-in.vhdl index 46b27d23..dc01878f 100644 --- a/testfiles/tb/golden_files/all1_insta_rd-in.vhdl +++ b/testfiles/tb/golden_files/all1_insta_rd-in.vhdl @@ -205,6 +205,7 @@ begin if rising_edge(clock) then if resetn = '0' then rd_req_d0 <= '0'; + rd_adr_d0 <= "0000000000000"; else rd_req_d0 <= rd_req; rd_adr_d0 <= rd_addr; diff --git a/testfiles/tb/golden_files/all1_insta_rd-out.vhdl b/testfiles/tb/golden_files/all1_insta_rd-out.vhdl index 526bb45f..34aeedcc 100644 --- a/testfiles/tb/golden_files/all1_insta_rd-out.vhdl +++ b/testfiles/tb/golden_files/all1_insta_rd-out.vhdl @@ -205,6 +205,7 @@ begin if rising_edge(clock) then if resetn = '0' then rd_ack <= '0'; + rd_data <= "00000000000000000000000000000000"; else rd_ack <= rd_ack_d0; rd_data <= rd_dat_d0; diff --git a/testfiles/tb/golden_files/all1_insta_rd.vhdl b/testfiles/tb/golden_files/all1_insta_rd.vhdl index 69217baa..fc55dee1 100644 --- a/testfiles/tb/golden_files/all1_insta_rd.vhdl +++ b/testfiles/tb/golden_files/all1_insta_rd.vhdl @@ -207,7 +207,9 @@ begin if rising_edge(clock) then if resetn = '0' then rd_req_d0 <= '0'; + rd_adr_d0 <= "0000000000000"; rd_ack <= '0'; + rd_data <= "00000000000000000000000000000000"; else rd_req_d0 <= rd_req; rd_adr_d0 <= rd_addr; diff --git a/testfiles/tb/golden_files/all1_insta_wr-in,rd-out.vhdl b/testfiles/tb/golden_files/all1_insta_wr-in,rd-out.vhdl index 6354106b..a64d77a5 100644 --- a/testfiles/tb/golden_files/all1_insta_wr-in,rd-out.vhdl +++ b/testfiles/tb/golden_files/all1_insta_wr-in,rd-out.vhdl @@ -209,7 +209,11 @@ begin if rising_edge(clock) then if resetn = '0' then rd_ack <= '0'; + rd_data <= "00000000000000000000000000000000"; wr_req_d0 <= '0'; + wr_adr_d0 <= "0000000000000"; + wr_dat_d0 <= "00000000000000000000000000000000"; + wr_sel_d0 <= "00000000000000000000000000000000"; else rd_ack <= rd_ack_d0; rd_data <= rd_dat_d0; diff --git a/testfiles/tb/golden_files/all1_insta_wr-in.vhdl b/testfiles/tb/golden_files/all1_insta_wr-in.vhdl index c9109ddc..244a041f 100644 --- a/testfiles/tb/golden_files/all1_insta_wr-in.vhdl +++ b/testfiles/tb/golden_files/all1_insta_wr-in.vhdl @@ -207,6 +207,9 @@ begin if rising_edge(clock) then if resetn = '0' then wr_req_d0 <= '0'; + wr_adr_d0 <= "0000000000000"; + wr_dat_d0 <= "00000000000000000000000000000000"; + wr_sel_d0 <= "00000000000000000000000000000000"; else wr_req_d0 <= wr_req; wr_adr_d0 <= wr_addr; diff --git a/testfiles/tb/golden_files/all1_insta_wr.vhdl b/testfiles/tb/golden_files/all1_insta_wr.vhdl index b017d5c3..6d090914 100644 --- a/testfiles/tb/golden_files/all1_insta_wr.vhdl +++ b/testfiles/tb/golden_files/all1_insta_wr.vhdl @@ -208,6 +208,9 @@ begin if rising_edge(clock) then if resetn = '0' then wr_req_d0 <= '0'; + wr_adr_d0 <= "0000000000000"; + wr_dat_d0 <= "00000000000000000000000000000000"; + wr_sel_d0 <= "00000000000000000000000000000000"; wr_ack <= '0'; else wr_req_d0 <= wr_req; diff --git a/testfiles/tb/golden_files/buserr_insta.vhdl b/testfiles/tb/golden_files/buserr_insta.vhdl index dfdcda48..375981a3 100644 --- a/testfiles/tb/golden_files/buserr_insta.vhdl +++ b/testfiles/tb/golden_files/buserr_insta.vhdl @@ -81,7 +81,10 @@ begin if resetn = '0' then rd_ack <= '0'; rd_err <= '0'; + rd_data <= "00000000000000000000000000000000"; wr_req_d0 <= '0'; + wr_adr_d0 <= "000"; + wr_dat_d0 <= "00000000000000000000000000000000"; else rd_ack <= rd_ack_d0; rd_err <= rd_err_d0; diff --git a/testfiles/tb/golden_files/wmask_insta.vhdl b/testfiles/tb/golden_files/wmask_insta.vhdl index e20033c8..8bd71f28 100644 --- a/testfiles/tb/golden_files/wmask_insta.vhdl +++ b/testfiles/tb/golden_files/wmask_insta.vhdl @@ -74,7 +74,11 @@ begin if rising_edge(clock) then if resetn = '0' then rd_ack <= '0'; + rd_data <= "00000000000000000000000000000000"; wr_req_d0 <= '0'; + wr_adr_d0 <= "0000"; + wr_dat_d0 <= "00000000000000000000000000000000"; + wr_sel_d0 <= "00000000000000000000000000000000"; else rd_ack <= rd_ack_d0; rd_data <= rd_dat_d0;