Redesign disassembly main loop

[logic]

Redesign the disassembly main loop.

Today, the main loop tracks instruction-by-instruction state (registers, upcoming delayed branches) across an entire consecutive sequence of code, until no further disassembly is reasonable (ie. a hard branch is encountered).

In order to parallelize disassembly, we need to be able to operate on an instruction-by-instruction basis without shared state; the work queue is initially seeded with known locations from the interrupt vector table as today, but rather than branch targets being the only things added to the queue, each "next instruction" is added, ie. an instruction is disassembled and added to the segment, any branch targets of the instruction are added to the work queue, and then the next instruction is added to the queue (unless it's not appropriate, such as when the end of a routine is reached).

This will require the work queue to store not only targets and references, but register contents.