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augustofg committed Jul 13, 2022
2 parents 336a7f5 + 1031ab3 commit 43196b7
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Showing 34 changed files with 965 additions and 9,424 deletions.
2 changes: 1 addition & 1 deletion hdl/ip_cores/CommsCtrlFPGA
Submodule CommsCtrlFPGA updated 1 files
+0 −4 rtl/fofb_cc_gtp7_if/rtl/vhdl/fofb_cc_gt_if.vhd
2 changes: 1 addition & 1 deletion hdl/ip_cores/infra-cores
Submodule infra-cores updated 55 files
+10 −0 .gitignore
+2 −1 modules/common/Manifest.py
+1 −0 modules/common/anti_windup_accumulator/Manifest.py
+106 −0 modules/common/anti_windup_accumulator/anti_windup_accumulator.vhd
+21 −0 modules/common/ifc_common_pkg.vhd
+2 −2 modules/wishbone/wb_acq_core/wbgen/acq_core.wb
+0 −2 modules/wishbone/wb_afc_diag/Manifest.py
+2 −0 platform/simulation/Manifest.py
+33 −0 platform/simulation/ila_t8_d256_s8192_cap.vhd
+35 −0 platform/simulation/vio_din2_w128_dout2_w128.vhd
+1 −0 platform/xilinx/artix7/chipscope/Manifest.py
+3 −0 platform/xilinx/artix7/chipscope/ila_t8_d256_s4096_cap/Manifest.py
+3,251 −0 platform/xilinx/artix7/chipscope/ila_t8_d256_s4096_cap/ila_t8_d256_s4096_cap.xci
+5 −0 syn/.gitattributes
+93 −0 syn/.gitignore
+0 −0 syn/.keepme
+20 −0 syn/afc_v3/test_trigger/rcv/Manifest.py
+11 −0 syn/afc_v3/test_trigger/rcv/build_bitstream_local.sh
+20 −0 syn/afc_v3/test_trigger/transm/Manifest.py
+11 −0 syn/afc_v3/test_trigger/transm/build_bitstream_local.sh
+20 −0 syn/afc_v4/test_trigger/rcv/Manifest.py
+11 −0 syn/afc_v4/test_trigger/rcv/build_bitstream_local.sh
+13 −0 syn/afc_v4/test_trigger/transm/Manifest.py
+11 −0 syn/afc_v4/test_trigger/transm/build_bitstream_local.sh
+9 −0 testbench/common/anti_windup_accumulator/Manifest.py
+198 −0 testbench/common/anti_windup_accumulator/anti_windup_accumulator_tb.vhd
+2 −0 testbench/common/anti_windup_accumulator/ghdl/.gitignore
+9 −0 testbench/common/anti_windup_accumulator/ghdl/Manifest.py
+0 −0 top/.keepme
+15 −0 top/afc_v3/test_trigger/rcv/Manifest.py
+50 −0 top/afc_v3/test_trigger/rcv/clk_gen.vhd
+158 −0 top/afc_v3/test_trigger/rcv/sm_counter.vhd
+134 −0 top/afc_v3/test_trigger/rcv/sm_states_rcv.vhd
+146 −0 top/afc_v3/test_trigger/rcv/sys_pll.vhd
+309 −0 top/afc_v3/test_trigger/rcv/test_trigger_rcv.vhd
+90 −0 top/afc_v3/test_trigger/rcv/test_trigger_rcv.xdc
+14 −0 top/afc_v3/test_trigger/transm/Manifest.py
+50 −0 top/afc_v3/test_trigger/transm/clk_gen.vhd
+109 −0 top/afc_v3/test_trigger/transm/sm_transm.vhd
+146 −0 top/afc_v3/test_trigger/transm/sys_pll.vhd
+262 −0 top/afc_v3/test_trigger/transm/test_trigger_transm.vhd
+63 −0 top/afc_v3/test_trigger/transm/test_trigger_transm.xdc
+15 −0 top/afc_v4/test_trigger/rcv/Manifest.py
+50 −0 top/afc_v4/test_trigger/rcv/clk_gen.vhd
+158 −0 top/afc_v4/test_trigger/rcv/sm_counter.vhd
+134 −0 top/afc_v4/test_trigger/rcv/sm_states_rcv.vhd
+146 −0 top/afc_v4/test_trigger/rcv/sys_pll.vhd
+311 −0 top/afc_v4/test_trigger/rcv/test_trigger_rcv.vhd
+146 −0 top/afc_v4/test_trigger/rcv/test_trigger_rcv.xdc
+14 −0 top/afc_v4/test_trigger/transm/Manifest.py
+50 −0 top/afc_v4/test_trigger/transm/clk_gen.vhd
+109 −0 top/afc_v4/test_trigger/transm/sm_transm.vhd
+146 −0 top/afc_v4/test_trigger/transm/sys_pll.vhd
+260 −0 top/afc_v4/test_trigger/transm/test_trigger_transm.vhd
+115 −0 top/afc_v4/test_trigger/transm/test_trigger_transm.xdc
2 changes: 1 addition & 1 deletion hdl/ip_cores/rtm-lamp-gw
Submodule rtm-lamp-gw updated 28 files
+102 −304 hdl/modules/rtm_lamp_pkg.vhd
+0 −1 hdl/modules/rtmlamp_ohwr/Manifest.py
+1 −3 hdl/modules/rtmlamp_ohwr/cheby/build_cheby.sh
+6,240 −1,996 hdl/modules/rtmlamp_ohwr/cheby/doc/wb_rtmlamp_ohwr_regs_wb.html
+198 −3,304 hdl/modules/rtmlamp_ohwr/cheby/rtmlamp_ohwr_regs.cheby
+97 −796 hdl/modules/rtmlamp_ohwr/cheby/wb_rtmlamp_ohwr_regs.h
+3,256 −3,486 hdl/modules/rtmlamp_ohwr/cheby/wb_rtmlamp_ohwr_regs.vhd
+94 −428 hdl/modules/rtmlamp_ohwr/rtmlamp_ohwr.vhd
+0 −325 hdl/modules/rtmlamp_ohwr/wb_rtmlamp_ohwr.vhd
+118 −513 hdl/modules/rtmlamp_ohwr/xwb_rtmlamp_ohwr.vhd
+345 −325 hdl/sim/regs/wb_rtmlamp_ohwr_reg_consts.vhd
+269 −253 hdl/sim/regs/wb_rtmlamp_ohwr_regs.vh
+0 −60 hdl/syn/afcv3_1_ref_design/Manifest.py
+0 −391 hdl/syn/afcv3_1_ref_design/afc.pins
+0 −208 hdl/syn/afcv3_1_ref_design/afcv3_1_rtm_lamp.xdc
+0 −82 hdl/syn/afcv3_1_ref_design/afcv3_1_rtm_lamp_ohwr.xdc
+0 −11 hdl/syn/afcv3_1_ref_design/build_bitstream_local.sh
+0 −11 hdl/syn/afcv3_1_ref_design/build_bitstream_remote.sh
+0 −17 hdl/syn/afcv3_1_ref_design/build_synthesis_sdb.sh
+0 −78 hdl/syn/afcv3_1_ref_design/rtm-lamp-ohwr.pins
+0 −250 hdl/syn/afcv3_1_ref_design/xdcgen.py
+3 −1 hdl/testbench/rtm_lamp/ghdl/Manifest.py
+38 −70 hdl/testbench/rtm_lamp/rtm_lamp_tb.vhd
+22 −43 hdl/testbench/xwb_rtmlamp_ohwr/xwb_rtmlamp_ohwr_glue.vhd
+22 −31 hdl/testbench/xwb_rtmlamp_ohwr/xwb_rtmlamp_ohwr_tb.vhd
+0 −16 hdl/top/afcv3_1_ref_design/Manifest.py
+0 −957 hdl/top/afcv3_1_ref_design/afcv3_1_rtm_lamp_ctrl.vhd
+30 −46 hdl/top/afcv4_ref_design/afcv4_rtm_lamp_ctrl.vhd
26 changes: 12 additions & 14 deletions hdl/modules/fofb_ctrl_pkg.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -536,6 +536,9 @@ package fofb_ctrl_pkg is
-- Number of channels
g_CHANNELS : natural := 8;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer; -- anti-windup lower limit

-- Wishbone parameters
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
Expand All @@ -559,13 +562,9 @@ package fofb_ctrl_pkg is
dcc_time_frame_start_i : in std_logic;
dcc_time_frame_end_i : in std_logic;

-- Result output array
sp_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);
sp_debug_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);

-- Valid output
sp_valid_o : out std_logic_vector(g_CHANNELS-1 downto 0);
sp_valid_debug_o : out std_logic_vector(g_CHANNELS-1 downto 0);
-- Setpoints
sp_arr_o : out t_fofb_processing_setpoints(g_CHANNELS-1 downto 0);
sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0);

---------------------------------------------------------------------------
-- Wishbone Control Interface signals
Expand Down Expand Up @@ -619,6 +618,9 @@ package fofb_ctrl_pkg is
-- Number of channels
g_CHANNELS : natural := 8;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer; -- anti-windup lower limit

-- Wishbone parameters
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
Expand All @@ -642,13 +644,9 @@ package fofb_ctrl_pkg is
dcc_time_frame_start_i : in std_logic;
dcc_time_frame_end_i : in std_logic;

-- Result output array
sp_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);
sp_debug_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);

-- Valid output
sp_valid_o : out std_logic_vector(g_CHANNELS-1 downto 0);
sp_valid_debug_o : out std_logic_vector(g_CHANNELS-1 downto 0);
-- Setpoints
sp_arr_o : out t_fofb_processing_setpoints(g_CHANNELS-1 downto 0);
sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0);

---------------------------------------------------------------------------
-- Wishbone Control Interface signals
Expand Down
35 changes: 18 additions & 17 deletions hdl/modules/fofb_processing/dot_prod_pkg.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,11 @@ use ieee.numeric_std.all;

package dot_prod_pkg is

-- Output array
type t_dot_prod_array_signed is array (natural range <>) of signed(16-1 downto 0);
-- fofb_processing output array
-- NOTE: c_Q_WIDTH must match with g_Q_WIDTH defined on
-- hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd
constant c_Q_WIDTH : natural := 16;
type t_fofb_processing_setpoints is array (natural range <>) of signed(c_Q_WIDTH-1 downto 0);

-- RAM data output array
type t_ram_data_out_array_logic_vector is array (natural range <>) of std_logic_vector(32-1 downto 0);
Expand Down Expand Up @@ -170,7 +173,10 @@ package dot_prod_pkg is
g_OUT_FIXED : natural := 26;

-- Extra bits for accumulator
g_EXTRA_WIDTH : natural := 4
g_EXTRA_WIDTH : natural := 4;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer -- anti-windup lower limit
);
port(
---------------------------------------------------------------------------
Expand All @@ -195,13 +201,9 @@ package dot_prod_pkg is
ram_write_enable_i : in std_logic;
ram_coeff_dat_o : out std_logic_vector(g_B_WIDTH-1 downto 0);

-- Result output array
-- Setpoint
sp_o : out signed(g_C_WIDTH-1 downto 0);
sp_debug_o : out signed(g_C_WIDTH-1 downto 0);

-- Valid output
sp_valid_o : out std_logic;
sp_valid_debug_o : out std_logic
sp_valid_o : out std_logic
);
end component fofb_processing_channel;

Expand Down Expand Up @@ -237,7 +239,10 @@ package dot_prod_pkg is
g_EXTRA_WIDTH : natural := 4;

-- Number of channels
g_CHANNELS : natural := 8
g_CHANNELS : natural := 8;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer -- anti-windup lower limit
);
port(
---------------------------------------------------------------------------
Expand All @@ -260,13 +265,9 @@ package dot_prod_pkg is
ram_write_enable_i : in std_logic;
ram_coeff_dat_o : out std_logic_vector(g_B_WIDTH-1 downto 0);

-- Result output array
sp_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);
sp_debug_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);

-- Valid output
sp_valid_o : out std_logic_vector(g_CHANNELS-1 downto 0);
sp_valid_debug_o : out std_logic_vector(g_CHANNELS-1 downto 0)
-- Setpoints
sp_arr_o : out t_fofb_processing_setpoints(g_CHANNELS-1 downto 0);
sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0)
);
end component fofb_processing;

Expand Down
26 changes: 13 additions & 13 deletions hdl/modules/fofb_processing/fofb_processing.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,10 @@ entity fofb_processing is
g_EXTRA_WIDTH : natural := 4;

-- Number of channels
g_CHANNELS : natural := 8
g_CHANNELS : natural := 8;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer -- anti-windup lower limit
);
port(
---------------------------------------------------------------------------
Expand All @@ -80,13 +83,9 @@ entity fofb_processing is
ram_write_enable_i : in std_logic;
ram_coeff_dat_o : out std_logic_vector(g_B_WIDTH-1 downto 0);

-- Result output array
sp_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);
sp_debug_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);

-- Valid output
sp_valid_o : out std_logic_vector(g_CHANNELS-1 downto 0);
sp_valid_debug_o : out std_logic_vector(g_CHANNELS-1 downto 0)
-- Setpoints
sp_arr_o : out t_fofb_processing_setpoints(g_CHANNELS-1 downto 0);
sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0)
);
end fofb_processing;

Expand Down Expand Up @@ -149,7 +148,10 @@ begin
-- Fixed point representation for output
g_OUT_FIXED => g_OUT_FIXED,
-- Extra bits for accumulator
g_EXTRA_WIDTH => g_EXTRA_WIDTH
g_EXTRA_WIDTH => g_EXTRA_WIDTH,

g_ANTI_WINDUP_UPPER_LIMIT => g_ANTI_WINDUP_UPPER_LIMIT, -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT => g_ANTI_WINDUP_LOWER_LIMIT -- anti-windup lower limit
)
port map
(
Expand All @@ -164,10 +166,8 @@ begin
ram_addr_i => aa_s,
ram_write_enable_i => wea_s(i),
ram_coeff_dat_o => ram_coeff_dat_s(i),
sp_o => sp_o(i),
sp_debug_o => sp_debug_o(i),
sp_valid_o => sp_valid_o(i),
sp_valid_debug_o => sp_valid_debug_o(i)
sp_o => sp_arr_o(i),
sp_valid_o => sp_valid_arr_o(i)
);
end generate;

Expand Down
43 changes: 32 additions & 11 deletions hdl/modules/fofb_processing/fofb_processing_channel.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,10 @@ entity fofb_processing_channel is
g_EXTRA_WIDTH : natural := 4;

-- Width for output
g_C_WIDTH : natural := 16
g_C_WIDTH : natural := 16;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer -- anti-windup lower limit
);
port(
---------------------------------------------------------------------------
Expand All @@ -74,17 +77,15 @@ entity fofb_processing_channel is
ram_write_enable_i : in std_logic;
ram_coeff_dat_o : out std_logic_vector(g_B_WIDTH-1 downto 0);

-- Result output array
-- Setpoint
sp_o : out signed(g_C_WIDTH-1 downto 0);
sp_debug_o : out signed(g_C_WIDTH-1 downto 0);

-- Valid output
sp_valid_o : out std_logic;
sp_valid_debug_o : out std_logic
sp_valid_o : out std_logic
);
end fofb_processing_channel;

architecture behave of fofb_processing_channel is
signal sp_s : signed(g_C_WIDTH-1 downto 0);
signal sp_valid_s : std_logic;

begin

Expand Down Expand Up @@ -124,10 +125,30 @@ begin
ram_addr_i => ram_addr_i,
ram_write_enable_i => ram_write_enable_i,
ram_coeff_dat_o => ram_coeff_dat_o,
sp_o => sp_o,
sp_debug_o => sp_debug_o,
sp_valid_o => sp_valid_o,
sp_valid_debug_o => sp_valid_debug_o
sp_o => sp_s,
sp_debug_o => open,
sp_valid_o => sp_valid_s,
sp_valid_debug_o => open
);

cmp_anti_windup_accumulator : entity work.anti_windup_accumulator
generic map
(
g_A_WIDTH => g_C_WIDTH, -- input width
g_Q_WIDTH => g_C_WIDTH, -- output width
g_ANTI_WINDUP_UPPER_LIMIT => g_ANTI_WINDUP_UPPER_LIMIT, -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT => g_ANTI_WINDUP_LOWER_LIMIT -- anti-windup lower limit
)
port map
(
clk_i => clk_i, -- clock
rst_n_i => rst_n_i, -- reset

a_i => sp_s, -- input a
clear_i => '0', -- clear
sum_i => sp_valid_s, -- sum
q_o => sp_o, -- output q
valid_o => sp_valid_o -- valid
);

end architecture behave;
28 changes: 13 additions & 15 deletions hdl/modules/fofb_processing/wb_fofb_processing.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,9 @@ entity wb_fofb_processing is
-- Number of channels
g_CHANNELS : natural := 8;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer; -- anti-windup lower limit

-- Wishbone parameters
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
Expand All @@ -87,13 +90,9 @@ entity wb_fofb_processing is
dcc_time_frame_start_i : in std_logic;
dcc_time_frame_end_i : in std_logic;

-- Result output array
sp_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);
sp_debug_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);

-- Valid output
sp_valid_o : out std_logic_vector(g_CHANNELS-1 downto 0);
sp_valid_debug_o : out std_logic_vector(g_CHANNELS-1 downto 0);
-- Setpoints
sp_arr_o : out t_fofb_processing_setpoints(g_CHANNELS-1 downto 0);
sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0);

---------------------------------------------------------------------------
-- Wishbone Control Interface signals
Expand Down Expand Up @@ -169,7 +168,10 @@ begin
-- Extra bits for accumulator
g_EXTRA_WIDTH => g_EXTRA_WIDTH,
-- Number of channels
g_CHANNELS => g_CHANNELS
g_CHANNELS => g_CHANNELS,

g_ANTI_WINDUP_UPPER_LIMIT => g_ANTI_WINDUP_UPPER_LIMIT, -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT => g_ANTI_WINDUP_LOWER_LIMIT -- anti-windup lower limit
)
port map(
-- Core clock
Expand All @@ -189,13 +191,9 @@ begin
ram_write_enable_i => ram_write_enable_s,
ram_coeff_dat_o => ram_coeff_dat_o_s,

-- Result output array
sp_o => sp_o,
sp_debug_o => sp_debug_o,

-- Valid output for debugging
sp_valid_o => sp_valid_o,
sp_valid_debug_o => sp_valid_debug_o
-- Setpoints
sp_arr_o => sp_arr_o,
sp_valid_arr_o => sp_valid_arr_o
);

-----------------------------
Expand Down
26 changes: 12 additions & 14 deletions hdl/modules/fofb_processing/xwb_fofb_processing.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,9 @@ entity xwb_fofb_processing is
-- Number of channels
g_CHANNELS : natural := 8;

g_ANTI_WINDUP_UPPER_LIMIT : integer; -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT : integer; -- anti-windup lower limit

-- Wishbone parameters
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
Expand All @@ -87,13 +90,9 @@ entity xwb_fofb_processing is
dcc_time_frame_start_i : in std_logic;
dcc_time_frame_end_i : in std_logic;

-- Result output array
sp_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);
sp_debug_o : out t_dot_prod_array_signed(g_CHANNELS-1 downto 0);

-- Valid output
sp_valid_o : out std_logic_vector(g_CHANNELS-1 downto 0);
sp_valid_debug_o : out std_logic_vector(g_CHANNELS-1 downto 0);
-- Setpoints
sp_arr_o : out t_fofb_processing_setpoints(g_CHANNELS-1 downto 0);
sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0);

---------------------------------------------------------------------------
-- Wishbone Control Interface signals
Expand Down Expand Up @@ -134,6 +133,9 @@ begin
-- Number of channels
g_CHANNELS => g_CHANNELS,

g_ANTI_WINDUP_UPPER_LIMIT => g_ANTI_WINDUP_UPPER_LIMIT, -- anti-windup upper limit
g_ANTI_WINDUP_LOWER_LIMIT => g_ANTI_WINDUP_LOWER_LIMIT, -- anti-windup lower limit

-- Wishbone parameters
g_INTERFACE_MODE => g_INTERFACE_MODE,
g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY,
Expand All @@ -156,13 +158,9 @@ begin
dcc_time_frame_start_i => dcc_time_frame_start_i,
dcc_time_frame_end_i => dcc_time_frame_end_i,

-- Result output array
sp_o => sp_o,
sp_debug_o => sp_debug_o,

-- Valid output for debugging
sp_valid_o => sp_valid_o,
sp_valid_debug_o => sp_valid_debug_o,
-- Setpoints
sp_arr_o => sp_arr_o,
sp_valid_arr_o => sp_valid_arr_o,

---------------------------------------------------------------------------
-- Wishbone Control Interface signals
Expand Down
6 changes: 0 additions & 6 deletions hdl/syn/afcv3_ref_design/synthesis_descriptor_pkg.vhd
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6 changes: 0 additions & 6 deletions hdl/syn/afcv4_ref_design/synthesis_descriptor_pkg.vhd
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11 changes: 11 additions & 0 deletions hdl/testbench/dot_prod_coeff_vec/Manifest.py
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
files = [
"dot_prod_coeff_vec_tb.vhd",
]

modules = {
"local" : [
"../../ip_cores/infra-cores",
"../../ip_cores/general-cores",
"../../modules/fofb_processing"
],
}
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