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CHANGELOG
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network-interconnect-tester-cores (0.54) stable; urgency=medium
* Added filter_gmii test core for emulating simple DUT
* Fixed <timestamp> for captured frames
-- Vladimir Vassilev <[email protected]> Thu, 07 Nov 2024 02:36:02 +0100
network-interconnect-tester-cores (0.53) stable; urgency=medium
* Added <last-sequence-error> container implementation added in -05
-- Vladimir Vassilev <[email protected]> Tue, 05 Nov 2024 17:27:45 +0100
network-interconnect-tester-cores (0.52) stable; urgency=medium
* Partial implementation of changes introduced in draft-ietf-bmwg-network-tester-cfg-04. Testframe bitwise filter needs more work
* Reverted autoconf simulation lib/sw option to disabled by default
-- Vladimir Vassilev <[email protected]> Wed, 20 Mar 2024 15:05:45 +0100
network-interconnect-tester-cores (0.51) stable; urgency=medium
* Updated and improved documentation. Now using Markdown for top level README
-- Vladimir Vassilev <[email protected]> Wed, 28 Feb 2024 16:06:34 +0100
network-interconnect-tester-cores (0.50) stable; urgency=medium
* Added systems/simulation cocotb based RTL simulation of the design with socket based register io interface for pre-silicon validation of applications.
-- Vladimir Vassilev <[email protected]> Tue, 27 Feb 2024 22:01:04 +0100
network-interconnect-tester-cores (0.49) stable; urgency=medium
* Corrected corrected_delta_pps default register value in the rtclock IP core
* Added identical cocotb Python benchmark template in adition to Verilog. flip_register.v and flip_register.py
* Removed AXI WSTR signals dependency from rtclock since cocotb seems to not drive the signals
-- Vladimir Vassilev <[email protected]> Wed, 21 Feb 2024 18:09:54 +0100
network-interconnect-tester-cores (0.48) stable; urgency=medium
* Dedicated pins added for the alternative frequencies ref_clk_10mhz_or_12mhz (D5) replaced with ref_clk_10mhz (D5.HDGC) and ref_clk_12mhz (D7.HDGC)
* Enable second CS (MIO40) for spi0 e.g. /dev/spidev0.1
-- Vladimir Vassilev <[email protected]> Thu, 09 Feb 2023 11:54:43 +0100
network-interconnect-tester-cores (0.47) stable; urgency=medium
* Changed ref_jitter for the clk_rst_i_plle3_tx and clk_rst_i_plle3_rx pcs/pma clock instantiation from 0.010 to 0.060
* Added the eth_pcs_pma_shared rx_locked and tx_locked signals to the axi_gpio register
-- Vladimir Vassilev <[email protected]> Mon, 19 Dec 2022 22:37:51 +0100
network-interconnect-tester-cores (0.46) stable; urgency=medium
* Swapped clock inputs for clk_wiz_1 now 12MHz is primary and 10MHz secondary
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 13:10:55 +0200
network-interconnect-tester-cores (0.45) stable; urgency=medium
* Added rtclock_1 new instance for debugging the output clock of clk_wiz_1
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 12:55:18 +0200
network-interconnect-tester-cores (0.44) stable; urgency=medium
* Removed BUFGCE instances on the input clock signals for clk_wiz_1
* Removed timing constraints on the input ref_clk_10mhz_or_12mhz
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 12:43:12 +0200
network-interconnect-tester-cores (0.43) stable; urgency=medium
* Added secondary 12MHz input clock to clk_wiz_1 in addition to the primary 10MHz option
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 02:49:26 +0200
network-interconnect-tester-cores (0.42) stable; urgency=medium
* Removed MAC and DMA instances for the eth2 and eth3 interfaces
-- Vladimir vassilev <[email protected]> Sat, 27 Aug 2022 02:19:39 +0200
network-interconnect-tester-cores (0.41) stable; urgency=medium
* Disabled the clock monitor for clk_wiz_1
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 02:03:40 +0200
network-interconnect-tester-cores (0.40) stable; urgency=medium
* Enabled dynamic reconfiguration USE_DYN_RECONFIG for clk_wiz_1
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 00:45:50 +0200
network-interconnect-tester-cores (0.39) stable; urgency=medium
* Enabled CONFIG.JITTER_SEL {Max_I_Jitter} for clk_wiz_1 and clk_wiz_2
* Reduced configured worst case jitter configuration from 20 ns to 11 ns for clk_wiz_1
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 00:32:21 +0200
network-interconnect-tester-cores (0.38) stable; urgency=medium
* Changed clk_wiz_1 to clk_wiz_2 frequency from 100 MHz to 10 MHz
-- Vladimir Vassilev <[email protected]> Sat, 27 Aug 2022 00:19:50 +0200
network-interconnect-tester-cores (0.37) stable; urgency=medium
* Enabled clock monitor for clk_wiz_1
-- Vladimir Vassilev <[email protected]> Mon, 15 Aug 2022 11:28:15 +0200
network-interconnect-tester-cores (0.36) stable; urgency=medium
* Added clk_wiz_2 100 MHz -> 100 MHz clock management tile with the intention to reduce jitter below 1000 ps
-- Vladimir Vassilev <[email protected]> Fri, 12 Aug 2022 02:15:47 +0200
network-interconnect-tester-cores (0.35) stable; urgency=medium
* Updated the xdc constraints file fixing some critical warning
-- Vladimir Vassilev <[email protected]> Fri, 12 Aug 2022 02:08:55 +0200
network-interconnect-tester-cores (0.34) stable; urgency=medium
* Updated the parameter customization for clk_wiz0 and clk_wiz1 with correct output jitter returned using GUI
* Removed no longer existing phy_gpio_tri_io port assigments from the constraints file
-- Vladimir Vassilev <[email protected]> Fri, 12 Aug 2022 02:01:17 +0200
network-interconnect-tester-cores (0.33) stable; urgency=medium
* Added monitoring for the clk_wiz0.lock signal in addition to clk_wiz1.lock
* Added explicit CONFIG.PRIM_IN_FREQ IP customization parameter for clk_wiz0
-- Vladimir Vassilev <[email protected]> Mon, 08 Aug 2022 00:38:46 +0200
network-interconnect-tester-cores (0.32) buster; urgency=medium
* Added axi_gpio instance for reading clk_wiz1.locked and writing clk_wiz0.clk_sel
* Added rtclock-clk-sel-external script to set clk_wiz0.clk_sel and select the external clock as sync source
-- Vladimir Vassilev <[email protected]> Thu, 04 Aug 2022 02:47:27 +0200
network-interconnect-tester-cores (0.31) buster; urgency=medium
* Increased CLKIN1_JITTER_PS for the clk_wiz_1 from 1000 to 12000 since U-blox LEA-M8T specifies 11 ns maximum jitter.
-- Vladimir Vassilev <[email protected]> Sun, 31 Jul 2022 11:16:21 +0200
network-interconnect-tester-cores (0.30) stable; urgency=medium
* systems/spark: Added the internal 100 MHz clock as secondary clock used when the external primary is not in locked state
-- Vladimir Vassilev <[email protected]> Sun, 16 Jan 2022 00:11:54 +0100
network-interconnect-tester-cores (0.29) stable; urgency=medium
* Added power-distribution-unit module for testing power interruption recovery times RFC2544 sec. 26.6
-- Vladimir Vassilev <[email protected]> Mon, 18 Oct 2021 13:12:47 +0200
network-interconnect-tester-cores (0.28) stable; urgency=medium
* Added gnss-clock module for management of GNSS disciplined oscillators
-- Vladimir Vassilev <[email protected]> Sun, 10 Oct 2021 23:47:31 +0200
network-interconnect-tester-cores (0.27) stable; urgency=medium
* Used 10 MHz external input clock instead of the internal 100 MHz for primary input to clk_wiz and 625 MHz synthesis
-- Vladimir Vassilev <[email protected]> Wed, 29 Sep 2021 15:28:02 +0200
network-interconnect-tester-cores (0.26) stable; urgency=medium
* lib/hw/rtclock: Added 1s PPS correction logic for frequency drift of local clock
* lib/sw/rtclock: Added rtclock-pps-correction to update the delta increment realtime clock register
* systems/spark: Fixed bug inverted uart16550/dcdn signals so that rising instead of falling pps edge is used as trigger
-- Vladimir Vassilev <[email protected]> Sun, 15 Aug 2021 09:17:41 +0200
network-interconnect-tester-cores (0.25) stable; urgency=medium
* systems/spark: Connected the GPS PPS signals to uart16550/dcdn
* lib/sw/rtclock: Added rtclock-pps-sync script that writes current second to register and enables PPS sync
-- Vladimir Vassilev <[email protected]> Sat, 24 Jul 2021 23:50:05 +0200
network-interconnect-tester-cores (0.24) stable; urgency=medium
* systems/spark: Added second instances of traffic-generator and traffic-analyzer. Instance 0 for eth0,eth2,eth4, 1 for eth1,eth3,eth5
-- Vladimir Vassilev <[email protected]> Wed, 14 Jul 2021 23:52:33 +0200
network-interconnect-tester-cores (0.23) stable; urgency=medium
* cores/traffic-analyzer-gmii: Fixed bug causing non-testframes to interfere with testframe stats
* lib/sw: Fixed bug in traffic-generator wrapper script not restoring the gmii-mux source to MAC/DMA after the generator is disabled
* systems/spark/petalinux: Fixed different MAC used for eth0 issue caused by u-boot overwriting the value in the device tree
-- Vladimir Vassilev <[email protected]> Fri, 21 May 2021 09:46:37 +0200
network-interconnect-tester-cores (0.22) stable; urgency=medium
systems/spark/petalinux:
* Added all rootfs packages except the binary sds-lib from ultra96v2_oob_2019_2 so that rootfs is identical to the original distribution
* Removed the default static inet configuration for eth5
-- Vladimir Vassilev <[email protected]> Sun, 09 May 2021 17:51:55 +0200
network-interconnect-tester-cores (0.21) stable; urgency=medium
* systems/spark/petalinux: Corrected fix for the ultra96v1 build in 0.20 causing many packages (git, ethtool etc.) to be removed from rootfs
* systems/spark: Added validation check returning error code in case impl_1 task fails
-- Vladimir Vassilev <[email protected]> Tue, 04 May 2021 13:18:13 +0200
network-interconnect-tester-cores (0.20) stable; urgency=medium
* systems/spark: Removed the optional 8-bit AXI stream based traffic_generator -> fifo -> tri_mode_ethernet_mac
implementation since it requires license for the tri_mode_ethernet_mac core and
evaluation license is no longer available for that core.
* systems/spark/petalinux: Fixed build issues for ultra96v1 boards
-- Vladimir Vassilev <[email protected]> Fri, 16 Apr 2021 21:27:43 +0200
network-interconnect-tester-cores (0.19) stable; urgency=medium
* cores/rtclock: Added alternative pps2 input
* systems/spark: Added 2x uart_1665 cores e.g. NMEA input
* systems/spark: Moved eth4 interrupts from the axi_intc directly to GIC pl_ps_irq1 1-4
-- Vladimir Vassilev <[email protected]> Tue, 02 Mar 2021 14:08:44 +0100
network-interconnect-tester-cores (0.18) stable; urgency=medium
* cores/rtclock: Added rtclock support for 1s pps synchronization
* systems/spark: Connected ls_mezz_int0 to rtclock_0/pps
-- Vladimir Vassilev <[email protected]> Mon, 01 Mar 2021 14:24:21 +0100
network-interconnect-tester-cores (0.17) stable; urgency=medium
* systems/spark: Added xilinx:axi_intc core to pl_ps_irq1 so that >8 interrupts can be handled.
-- Vladimir Vassilev <[email protected]> Fri, 26 Feb 2021 22:21:12 +0100
network-interconnect-tester-cores (0.16) stable; urgency=medium
* Updated traffic-generator-gmii testframe-type option according to draft-vassilev-bmwg-network-interconnect-tester-05
-- Vladimir Vassilev <[email protected]> Mon, 22 Feb 2021 16:08:21 +0100
network-interconnect-tester-cores (0.15) stable; urgency=medium
* Implemented burst mode
-- Vladimir Vassilev <[email protected]> Wed, 03 Feb 2021 11:07:32 +0100
network-interconnect-tester-cores (0.14) stable; urgency=medium
* Fixed bug in block ram frame data buffer interface to AXI Lite causing data corruption
* Fixed bug in latency registers not being updated
-- Vladimir Vassilev <[email protected]> Sat, 16 Jan 2021 14:16:11 +0100
network-interconnect-tester-cores (0.13) stable; urgency=medium
* Added dynamic testframe mode generated with 64 bit sequence number and PTP timestamp used for latency calculation
-- Vladimir Vassilev <[email protected]> Mon, 11 Jan 2021 12:41:03 +0100
network-interconnect-tester-cores (0.12) stable; urgency=medium
* Fixed bug in the frame payload buffer implementation
* cores/analyzer: preamble is no longer included in the octets statistics added bad_preamble_{pkts,octets} and octets_total counters
* lib/sw: Added loopback tool for configuration of local loopback using pcs/pma core mdio access
* lib/sw: Added wrapper scripts for systems using multiplexed generator and analyzer cores
-- Vladimir Vassilev <[email protected]> Fri, 01 Jan 2021 21:32:05 +0100
network-interconnect-tester-cores (0.11) stable; urgency=medium
* system/spark: Added gmii_mux instance to the design forwarding traffic from any of the interfaces to the traffic analyzer core
* cores/gmii_mux: Increased available inputs from 5 to 6
-- Vladimir Vassilev <[email protected]> Sat, 19 Dec 2020 22:42:38 +0100
network-interconnect-tester-cores (0.10) stable; urgency=medium
* Added Ethernet CRC checking to the traffic analyzer core with BAD_CRC_PKTS and BAD_CRC_OCTETS registers
-- Vladimir Vassilev <[email protected]> Sat, 19 Dec 2020 22:27:17 +0100
network-interconnect-tester-cores (0.9) stable; urgency=medium
* Implemented total-frames generator parameter
* Fixed capture synchronization so that a frame is atomically completed even if freeze_stats gets set underway
* Added --disable to traffic-generator-gmii parameters
* Software implementing the capture functionality in the analyzer model
-- Vladimir Vassilev <[email protected]> Thu, 10 Dec 2020 19:40:23 +0100
network-interconnect-tester-cores (0.8) stable; urgency=medium
* system/spark: Added wifi kernel module and firmware package
* system/spark: Added openvswitch kernel module
-- Vladimir Vassilev <[email protected]> Thu, 03 Dec 2020 10:23:38 +0100
network-interconnect-tester-cores (0.7) stable; urgency=medium
* lib/sw: Added traffic-generator-gmii and traffic-analyzer-gmii tools
-- Vladimir Vassilev <[email protected]> Mon, 26 Oct 2020 14:24:10 +0100
network-interconnect-tester-cores (0.6) stable; urgency=medium
* Added realtime clock core - rtclock
* Added traffic analyzer core - traffic_analyzer_gmii. Supports basic counters and single frame capture to block ram
* Enhanced traffic generator. Added frame data buffer block ram
-- Vladimir Vassilev <[email protected]> Thu, 03 Sep 2020 13:02:26 +0200
network-interconnect-tester-cores (0.5) stable; urgency=medium
* Fixed bug in gmii_mux input select logic overlap e.g. 2'h04 was interpreted as 0
* Fixed bug in eth4 tx caused by wrong gmii index pcs/pma
-- Vladimir Vassilev <[email protected]> Tue, 18 Aug 2020 12:14:10 +0200
network-interconnect-tester-cores (0.4) stable; urgency=medium
* Added traffic_generator_gmii core generating traffic without MAC
* Added additional 2 inputs to the gmii_mux
* Added instance of the new traffic_generator_gmii in addition to the AXI traffic_generator
* Added passthrough loopback mode where ethN+0 ingress is connected as ethN+1 egress and vice versa
-- Vladimir Vassilev <[email protected]> Sun, 26 Jul 2020 15:43:43 +0200
network-interconnect-tester-cores (0.3) stable; urgency=medium
* Added gmii-mux-tool application to configure the mux from userspace
* Fixed bug in gmii_mux core
-- Vladimir Vassilev <[email protected]> Sat, 11 Jul 2020 16:43:07 +0200
network-interconnect-tester-cores (0.2) stable; urgency=medium
* Added petalinux build scripts and patches
* Fixed synthesis bug in IP
-- Vladimir Vassilev <[email protected]> Thu, 25 Jun 2020 03:42:09 +0200
network-interconnect-tester-cores (0.1) stable; urgency=medium
* Added support for new system - spark v1 6x SFP+ 96boards extension card compatible with Ultra96
* Added clock management tile to generate 625 MHz from the 100 MHz system clock due to lack of oscillator
* Moved the shared gig eth pcs pma logic to a dedicated IP module based on the Xilinx example code
* eth0,eth1,eth4 and eth5 can be used as general interfaces. eth3 does not have DMA due to depletion of DMA channels. Both eth2 and eth3 have disconnected irq. Should use additional axi interrupt.
* Added third port to the gmii_mux and changed behavior so port 0 is selected by default
-- Vladimir Vassilev <[email protected]> Wed, 24 Jun 2020 02:02:17 +0200
network-interconnect-tester-cores (0.0) stable; urgency=medium
* Project template. Minimalistic set of tcl and Verilog files specifying the coding style and project organization.
-- Vladimir Vassilev <[email protected]> Thu, 12 Dec 2019 15:35:24 +0100