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DrZ80.s
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;@ Reesy's Z80 Emulator Version 0.001
;@ (c) Copyright 2004 Reesy, All rights reserved
;@ DrZ80 is free for non-commercial use.
;@ For commercial use, separate licencing terms must be obtained.
.data
.align 4
.global DrZ80Run
.global DrZ80Ver
.equiv INTERRUPT_MODE, 0 ;@0 = Use internal int handler, 1 = Use Mames int handler
.equiv FAST_Z80SP, 1 ;@0 = Use mem functions for stack pointer, 1 = Use direct mem pointer
.equiv UPDATE_CONTEXT, 0
.equiv DRZ80_XMAP, 0
.equiv DRZ80_XMAP_MORE_INLINE, 0
.if DRZ80_XMAP
.equ Z80_MEM_SHIFT, 13
.endif
.if INTERRUPT_MODE
.extern Interrupt
.endif
DrZ80Ver: .long 0x0001
;@ --------------------------- Defines ----------------------------
;@ Make sure that regs/pointers for z80pc to z80sp match up!
z80_icount .req r3
opcodes .req r4
cpucontext .req r5
z80pc .req r6
z80a .req r7
z80f .req r8
z80bc .req r9
z80de .req r10
z80hl .req r11
z80sp .req r12
z80xx .req lr
.equ z80pc_pointer, 0 ;@ 0
.equ z80a_pointer, z80pc_pointer+4 ;@ 4
.equ z80f_pointer, z80a_pointer+4 ;@ 8
.equ z80bc_pointer, z80f_pointer+4 ;@
.equ z80de_pointer, z80bc_pointer+4
.equ z80hl_pointer, z80de_pointer+4
.equ z80sp_pointer, z80hl_pointer+4
.equ z80pc_base, z80sp_pointer+4
.equ z80sp_base, z80pc_base+4
.equ z80ix, z80sp_base+4
.equ z80iy, z80ix+4
.equ z80i, z80iy+4
.equ z80a2, z80i+4
.equ z80f2, z80a2+4
.equ z80bc2, z80f2+4
.equ z80de2, z80bc2+4
.equ z80hl2, z80de2+4
.equ cycles_pointer, z80hl2+4
.equ previouspc, cycles_pointer+4
.equ z80irq, previouspc+4
.equ z80if, z80irq+1
.equ z80im, z80if+1
.equ z80r, z80im+1
.equ z80irqvector, z80r+1
.equ z80irqcallback, z80irqvector+4
.equ z80_write8, z80irqcallback+4
.equ z80_write16, z80_write8+4
.equ z80_in, z80_write16+4
.equ z80_out, z80_in+4
.equ z80_read8, z80_out+4
.equ z80_read16, z80_read8+4
.equ z80_rebaseSP, z80_read16+4
.equ z80_rebasePC, z80_rebaseSP+4
.equ VFlag, 0
.equ CFlag, 1
.equ ZFlag, 2
.equ SFlag, 3
.equ HFlag, 4
.equ NFlag, 5
.equ Flag3, 6
.equ Flag5, 7
.equ Z80_CFlag, 0
.equ Z80_NFlag, 1
.equ Z80_VFlag, 2
.equ Z80_Flag3, 3
.equ Z80_HFlag, 4
.equ Z80_Flag5, 5
.equ Z80_ZFlag, 6
.equ Z80_SFlag, 7
.equ Z80_IF1, 1<<0
.equ Z80_IF2, 1<<1
.equ Z80_HALT, 1<<2
.equ Z80_NMI, 1<<3
;@---------------------------------------
.text
.if DRZ80_XMAP
z80_xmap_read8: @ addr
ldr r1,[cpucontext,#z80_read8]
mov r2,r0,lsr #Z80_MEM_SHIFT
ldr r1,[r1,r2,lsl #2]
movs r1,r1,lsl #1
ldrccb r0,[r1,r0]
bxcc lr
z80_xmap_read8_handler: @ addr, func
str z80_icount,[cpucontext,#cycles_pointer]
stmfd sp!,{r12,lr}
mov lr,pc
bx r1
ldr z80_icount,[cpucontext,#cycles_pointer]
ldmfd sp!,{r12,pc}
z80_xmap_write8: @ data, addr
ldr r2,[cpucontext,#z80_write8]
add r2,r2,r1,lsr #Z80_MEM_SHIFT-2
bic r2,r2,#3
ldr r2,[r2]
movs r2,r2,lsl #1
strccb r0,[r2,r1]
bxcc lr
z80_xmap_write8_handler: @ data, addr, func
str z80_icount,[cpucontext,#cycles_pointer]
mov r3,r0
mov r0,r1
mov r1,r3
stmfd sp!,{r12,lr}
mov lr,pc
bx r2
ldr z80_icount,[cpucontext,#cycles_pointer]
ldmfd sp!,{r12,pc}
z80_xmap_read16: @ addr
@ check if we cross bank boundary
add r1,r0,#1
eor r1,r1,r0
tst r1,#1<<Z80_MEM_SHIFT
bne 0f
ldr r1,[cpucontext,#z80_read8]
mov r2,r0,lsr #Z80_MEM_SHIFT
ldr r1,[r1,r2,lsl #2]
movs r1,r1,lsl #1
bcs 0f
ldrb r0,[r1,r0]!
ldrb r1,[r1,#1]
orr r0,r0,r1,lsl #8
bx lr
0:
@ z80_xmap_read8 will save r3 and r12 for us
stmfd sp!,{r8,r9,lr}
mov r8,r0
bl z80_xmap_read8
mov r9,r0
add r0,r8,#1
bl z80_xmap_read8
orr r0,r9,r0,lsl #8
ldmfd sp!,{r8,r9,pc}
z80_xmap_write16: @ data, addr
add r2,r1,#1
eor r2,r2,r1
tst r2,#1<<Z80_MEM_SHIFT
bne 0f
ldr r2,[cpucontext,#z80_write8]
add r2,r2,r1,lsr #Z80_MEM_SHIFT-2
bic r2,r2,#3
ldr r2,[r2]
movs r2,r2,lsl #1
bcs 0f
strb r0,[r2,r1]!
mov r0,r0,lsr #8
strb r0,[r2,#1]
bx lr
0:
stmfd sp!,{r8,r9,lr}
mov r8,r0
mov r9,r1
bl z80_xmap_write8
mov r0,r8,lsr #8
add r1,r9,#1
bl z80_xmap_write8
ldmfd sp!,{r8,r9,pc}
z80_xmap_rebase_pc:
ldr r1,[cpucontext,#z80_read8]
mov r2,r0,lsr #Z80_MEM_SHIFT
ldr r1,[r1,r2,lsl #2]
movs r1,r1,lsl #1
strcc r1,[cpucontext,#z80pc_base]
addcc z80pc,r1,r0
bxcc lr
z80_bad_jump:
stmfd sp!,{r3,r12,lr}
mov lr,pc
ldr pc,[cpucontext,#z80_rebasePC]
mov z80pc,r0
ldmfd sp!,{r3,r12,pc}
.if FAST_Z80SP
z80_xmap_rebase_sp:
ldr r1,[cpucontext,#z80_read8]
sub r2,r0,#1
mov r2,r2,lsl #16
mov r2,r2,lsr #(Z80_MEM_SHIFT+16)
ldr r1,[r1,r2,lsl #2]
movs r1,r1,lsl #1
strcc r1,[cpucontext,#z80sp_base]
addcc z80sp,r1,r0
bxcc lr
stmfd sp!,{r3,r12,lr}
mov lr,pc
ldr pc,[cpucontext,#z80_rebaseSP]
mov z80sp,r0
ldmfd sp!,{r3,r12,pc}
.endif @ FAST_Z80SP
.endif @ DRZ80_XMAP
.macro fetch cycs
subs z80_icount,z80_icount,#\cycs
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
str z80_icount,[cpucontext,#cycles_pointer]
ldr r1,[cpucontext,#z80pc_base]
sub r2,z80pc,r1
str r2,[cpucontext,#previouspc]
.endif
ldrplb r0,[z80pc],#1
ldrpl pc,[opcodes,r0, lsl #2]
bmi z80_execute_end
.endm
.macro eatcycles cycs
sub z80_icount,z80_icount,#\cycs
.if UPDATE_CONTEXT
str z80_icount,[cpucontext,#cycles_pointer]
.endif
.endm
.macro readmem8
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if DRZ80_XMAP
.if !DRZ80_XMAP_MORE_INLINE
ldr r1,[cpucontext,#z80_read8]
mov r2,r0,lsr #Z80_MEM_SHIFT
ldr r1,[r1,r2,lsl #2]
movs r1,r1,lsl #1
ldrccb r0,[r1,r0]
blcs z80_xmap_read8_handler
.else
bl z80_xmap_read8
.endif
.else ;@ if !DRZ80_XMAP
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0
ldmfd sp!,{r3,r12}
.endif
.endm
.macro readmem8HL
mov r0,z80hl, lsr #16
readmem8
.endm
.macro readmem16
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if DRZ80_XMAP
bl z80_xmap_read16
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read16]
ldmfd sp!,{r3,r12}
.endif
.endm
.macro writemem8
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if DRZ80_XMAP
.if DRZ80_XMAP_MORE_INLINE
ldr r2,[cpucontext,#z80_write8]
mov lr,r1,lsr #Z80_MEM_SHIFT
ldr r2,[r2,lr,lsl #2]
movs r2,r2,lsl #1
strccb r0,[r2,r1]
blcs z80_xmap_write8_handler
.else
bl z80_xmap_write8
.endif
.else ;@ if !DRZ80_XMAP
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endif
.endm
.macro writemem8DE
mov r1,z80de, lsr #16
writemem8
.endm
.macro writemem8HL
mov r1,z80hl, lsr #16
writemem8
.endm
.macro writemem16
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if DRZ80_XMAP
bl z80_xmap_write16
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_write16] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endif
.endm
.macro copymem8HL_DE
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
mov r0,z80hl, lsr #16
.if DRZ80_XMAP
bl z80_xmap_read8
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0
.endif
mov r1,z80de, lsr #16
.if DRZ80_XMAP
bl z80_xmap_write8
.else
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endif
.endm
;@---------------------------------------
.macro rebasepc
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if DRZ80_XMAP
bl z80_xmap_rebase_pc
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_rebasePC] ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0
ldmfd sp!,{r3,r12}
mov z80pc,r0
.endif
.endm
.macro rebasesp
.if UPDATE_CONTEXT
str z80pc,[cpucontext,#z80pc_pointer]
.endif
.if DRZ80_XMAP
bl z80_xmap_rebase_sp
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_rebaseSP] ;@ external function must rebase sp
ldmfd sp!,{r3,r12}
mov z80sp,r0
.endif
.endm
;@----------------------------------------------------------------------------
.macro opADC
movs z80f,z80f,lsr#2 ;@ get C
subcs r0,r0,#0x100
eor z80f,r0,z80a,lsr#24 ;@ prepare for check of half carry
adcs z80a,z80a,r0,ror#8
mrs r0,cpsr ;@ S,Z,V&C
eor z80f,z80f,z80a,lsr#24
and z80f,z80f,#1<<HFlag ;@ H, correct
orr z80f,z80f,r0,lsr#28
.endm
.macro opADCA
movs z80f,z80f,lsr#2 ;@ get C
orrcs z80a,z80a,#0x00800000
adds z80a,z80a,z80a
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
tst z80a,#0x10000000 ;@ H, correct
orrne z80f,z80f,#1<<HFlag
fetch 4
.endm
.macro opADCH reg
mov r0,\reg,lsr#24
opADC
fetch 4
.endm
.macro opADCL reg
movs z80f,z80f,lsr#2 ;@ get C
adc r0,\reg,\reg,lsr#15
orrcs z80a,z80a,#0x00800000
mov r1,z80a,lsl#4 ;@ Prepare for check of half carry
adds z80a,z80a,r0,lsl#23
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
cmn r1,r0,lsl#27
orrcs z80f,z80f,#1<<HFlag ;@ H, correct
fetch 4
.endm
.macro opADCb
opADC
.endm
;@---------------------------------------
.macro opADD reg shift
mov r1,z80a,lsl#4 ;@ Prepare for check of half carry
adds z80a,z80a,\reg,lsl#\shift
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
cmn r1,\reg,lsl#\shift+4
orrcs z80f,z80f,#1<<HFlag
.endm
.macro opADDA
adds z80a,z80a,z80a
mrs z80f,cpsr ;@ S,Z,V&C
mov z80f,z80f,lsr#28
tst z80a,#0x10000000 ;@ H, correct
orrne z80f,z80f,#1<<HFlag
fetch 4
.endm
.macro opADDH reg
and r0,\reg,#0xFF000000
opADD r0 0
fetch 4
.endm
.macro opADDL reg
opADD \reg 8
fetch 4
.endm
.macro opADDb
opADD r0 24
.endm
;@---------------------------------------
.macro opADC16 reg
movs z80f,z80f,lsr#2 ;@ get C
adc r0,z80a,\reg,lsr#15
orrcs z80hl,z80hl,#0x00008000
mov r1,z80hl,lsl#4
adds z80hl,z80hl,r0,lsl#15
mrs z80f,cpsr ;@ S, Z, V & C
mov z80f,z80f,lsr#28
cmn r1,r0,lsl#19
orrcs z80f,z80f,#1<<HFlag
fetch 15
.endm
.macro opADC16HL
movs z80f,z80f,lsr#2 ;@ get C
orrcs z80hl,z80hl,#0x00008000
adds z80hl,z80hl,z80hl
mrs z80f,cpsr ;@ S, Z, V & C
mov z80f,z80f,lsr#28
tst z80hl,#0x10000000 ;@ H, correct.
orrne z80f,z80f,#1<<HFlag
fetch 15
.endm
.macro opADD16 reg1 reg2
mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry
adds \reg1,\reg1,\reg2
bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)
orrcs z80f,z80f,#1<<CFlag
cmn r1,\reg2,lsl#4
orrcs z80f,z80f,#1<<HFlag
.endm
.macro opADD16s reg1 reg2 shift
mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry
adds \reg1,\reg1,\reg2,lsl#\shift
bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)
orrcs z80f,z80f,#1<<CFlag
cmn r1,\reg2,lsl#4+\shift
orrcs z80f,z80f,#1<<HFlag
.endm
.macro opADD16_2 reg
adds \reg,\reg,\reg
bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)
orrcs z80f,z80f,#1<<CFlag
tst \reg,#0x10000000 ;@ H, correct.
orrne z80f,z80f,#1<<HFlag
.endm
;@---------------------------------------
.macro opAND reg shift
and z80a,z80a,\reg,lsl#\shift
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
orr z80f,z80f,#1<<HFlag
.endm
.macro opANDA
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
orr z80f,z80f,#1<<HFlag
fetch 4
.endm
.macro opANDH reg
opAND \reg 0
fetch 4
.endm
.macro opANDL reg
opAND \reg 8
fetch 4
.endm
.macro opANDb
opAND r0 24
.endm
;@---------------------------------------
.macro opBITH reg bit
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(24+\bit)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)
fetch 8
.endm
.macro opBIT7H reg
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(24+7)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)
fetch 8
.endm
.macro opBITL reg bit
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(16+\bit)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)
fetch 8
.endm
.macro opBIT7L reg
and z80f,z80f,#1<<CFlag
tst \reg,#1<<(16+7)
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)
fetch 8
.endm
.macro opBITb bit
and z80f,z80f,#1<<CFlag
tst r0,#1<<\bit
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)
.endm
.macro opBIT7b
and z80f,z80f,#1<<CFlag
tst r0,#1<<7
orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)
orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)
.endm
;@---------------------------------------
.macro opCP reg shift
mov r1,z80a,lsl#4 ;@ prepare for check of half carry
cmp z80a,\reg,lsl#\shift
mrs z80f,cpsr
mov z80f,z80f,lsr#28 ;@ S,Z,V&C
eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n
cmp r1,\reg,lsl#\shift+4
orrcc z80f,z80f,#1<<HFlag
.endm
.macro opCPA
mov z80f,#(1<<ZFlag)|(1<<NFlag) ;@ set Z & n
fetch 4
.endm
.macro opCPH reg
and r0,\reg,#0xFF000000
opCP r0 0
fetch 4
.endm
.macro opCPL reg
opCP \reg 8
fetch 4
.endm
.macro opCPb
opCP r0 24
.endm
;@---------------------------------------
.macro opDEC8 reg ;@for A and memory
and z80f,z80f,#1<<CFlag ;@save carry
orr z80f,z80f,#1<<NFlag ;@set n
tst \reg,#0x0f000000
orreq z80f,z80f,#1<<HFlag
subs \reg,\reg,#0x01000000
orrmi z80f,z80f,#1<<SFlag
orrvs z80f,z80f,#1<<VFlag
orreq z80f,z80f,#1<<ZFlag
.endm
.macro opDEC8H reg ;@for B, D & H
and z80f,z80f,#1<<CFlag ;@save carry
orr z80f,z80f,#1<<NFlag ;@set n
tst \reg,#0x0f000000
orreq z80f,z80f,#1<<HFlag
subs \reg,\reg,#0x01000000
orrmi z80f,z80f,#1<<SFlag
orrvs z80f,z80f,#1<<VFlag
tst \reg,#0xff000000 ;@Z
orreq z80f,z80f,#1<<ZFlag
.endm
.macro opDEC8L reg ;@for C, E & L
mov \reg,\reg,ror#24
opDEC8H \reg
mov \reg,\reg,ror#8
.endm
.macro opDEC8b ;@for memory
mov r0,r0,lsl#24
opDEC8 r0
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opIN
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_in] ;@ r0=port - data returned in r0
ldmfd sp!,{r3,r12}
.endm
.macro opIN_C
mov r0,z80bc, lsr #16
opIN
.endm
;@---------------------------------------
.macro opINC8 reg ;@for A and memory
and z80f,z80f,#1<<CFlag ;@save carry, clear n
adds \reg,\reg,#0x01000000
orrmi z80f,z80f,#1<<SFlag
orrvs z80f,z80f,#1<<VFlag
orrcs z80f,z80f,#1<<ZFlag ;@cs when going from 0xFF to 0x00
tst \reg,#0x0f000000
orreq z80f,z80f,#1<<HFlag
.endm
.macro opINC8H reg ;@for B, D & H
opINC8 \reg
.endm
.macro opINC8L reg ;@for C, E & L
mov \reg,\reg,ror#24
opINC8 \reg
mov \reg,\reg,ror#8
.endm
.macro opINC8b ;@for memory
mov r0,r0,lsl#24
opINC8 r0
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opOR reg shift
orr z80a,z80a,\reg,lsl#\shift
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
.endm
.macro opORA
sub r0,opcodes,#0x100
ldrb z80f,[r0,z80a, lsr #24]
fetch 4
.endm
.macro opORH reg
and r0,\reg,#0xFF000000
opOR r0 0
fetch 4
.endm
.macro opORL reg
opOR \reg 8
fetch 4
.endm
.macro opORb
opOR r0 24
.endm
;@---------------------------------------
.macro opOUT
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_out] ;@ r0=port r1=data
ldmfd sp!,{r3,r12}
.endm
.macro opOUT_C
mov r0,z80bc, lsr #16
opOUT
.endm
;@---------------------------------------
.macro opPOP
.if FAST_Z80SP
ldrb r0,[z80sp],#1
ldrb r1,[z80sp],#1
orr r0,r0,r1, lsl #8
.else
mov r0,z80sp
readmem16
add z80sp,z80sp,#2
.endif
.endm
.macro opPOPreg reg
opPOP
mov \reg,r0, lsl #16
fetch 10
.endm
;@---------------------------------------
.macro stack_check
@ try to protect against stack overflows, lock into current bank
ldr r1,[cpucontext,#z80sp_base]
sub r1,z80sp,r1
cmp r1,#2
addlt z80sp,z80sp,#1<<Z80_MEM_SHIFT
.endm
.macro opPUSHareg reg @ reg > r1
.if FAST_Z80SP
.if DRZ80_XMAP
stack_check
.endif
mov r1,\reg, lsr #8
strb r1,[z80sp,#-1]!
strb \reg,[z80sp,#-1]!
.else
mov r0,\reg
sub z80sp,z80sp,#2
mov r1,z80sp
writemem16
.endif
.endm
.macro opPUSHreg reg
.if FAST_Z80SP
.if DRZ80_XMAP
stack_check
.endif
mov r1,\reg, lsr #24
strb r1,[z80sp,#-1]!
mov r1,\reg, lsr #16
strb r1,[z80sp,#-1]!
.else
mov r0,\reg,lsr #16
sub z80sp,z80sp,#2
mov r1,z80sp
writemem16
.endif
.endm
;@---------------------------------------
.macro opRESmemHL bit
mov r0,z80hl, lsr #16
.if DRZ80_XMAP
bl z80_xmap_read8
bic r0,r0,#1<<\bit
mov r1,z80hl, lsr #16
bl z80_xmap_write8
.else
stmfd sp!,{r3,r12}
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0
bic r0,r0,#1<<\bit
mov r1,z80hl, lsr #16
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endif
fetch 15
.endm
;@---------------------------------------
.macro opRESmem bit
.if DRZ80_XMAP
stmfd sp!,{r0} ;@ save addr as well
bl z80_xmap_read8
bic r0,r0,#1<<\bit
ldmfd sp!,{r1} ;@ restore addr into r1
bl z80_xmap_write8
.else
stmfd sp!,{r3,r12}
stmfd sp!,{r0} ;@ save addr as well
mov lr,pc
ldr pc,[cpucontext,#z80_read8] ;@ r0=addr - data returned in r0
bic r0,r0,#1<<\bit
ldmfd sp!,{r1} ;@ restore addr into r1
mov lr,pc
ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr
ldmfd sp!,{r3,r12}
.endif
fetch 23
.endm
;@---------------------------------------
.macro opRL reg1 reg2 shift
movs \reg1,\reg2,lsl \shift
tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!
orrne \reg1,\reg1,#0x01000000
;@ and r2,z80f,#1<<CFlag
;@ orr $x,$x,r2,lsl#23
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1,lsr#24] ;@get PZS
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRLA
opRL z80a, z80a, #1
fetch 8
.endm
.macro opRLH reg
and r0,\reg,#0xFF000000 ;@mask high to r0
adds \reg,\reg,r0
tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!
orrne \reg,\reg,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24] ;@get PZS
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRLL reg
opRL r0, \reg, #9
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsr#8
fetch 8
.endm
.macro opRLb
opRL r0, r0, #25
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opRLC reg1 reg2 shift
movs \reg1,\reg2,lsl#\shift
orrcs \reg1,\reg1,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1,lsr#24]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRLCA
opRLC z80a, z80a, 1
fetch 8
.endm
.macro opRLCH reg
and r0,\reg,#0xFF000000 ;@mask high to r0
adds \reg,\reg,r0
orrcs \reg,\reg,#0x01000000
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRLCL reg
opRLC r0, \reg, 9
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsr#8
fetch 8
.endm
.macro opRLCb
opRLC r0, r0, 25
mov r0,r0,lsr#24
.endm
;@---------------------------------------
.macro opRR reg1 reg2 shift
movs \reg1,\reg2,lsr#\shift
tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!
orrne \reg1,\reg1,#0x00000080
;@ and r2,z80_f,#PSR_C
;@ orr \reg1,\reg1,r2,lsl#6
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRRA
orr z80a,z80a,z80f,lsr#1 ;@get C
movs z80a,z80a,ror#25
mov z80a,z80a,lsl#24
sub r1,opcodes,#0x100
ldrb z80f,[r1,z80a,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRRH reg
orr r0,\reg,z80f,lsr#1 ;@get C
movs r0,r0,ror#25
and \reg,\reg,#0x00FF0000 ;@mask out low
orr \reg,\reg,r0,lsl#24
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg,lsr#24]
orrcs z80f,z80f,#1<<CFlag
fetch 8
.endm
.macro opRRL reg
and r0,\reg,#0x00FF0000 ;@mask out low to r0
opRR r0 r0 17
and \reg,\reg,#0xFF000000 ;@mask out high
orr \reg,\reg,r0,lsl#16
fetch 8
.endm
.macro opRRb
opRR r0 r0 1
.endm
;@---------------------------------------
.macro opRRC reg1 reg2 shift
movs \reg1,\reg2,lsr#\shift
orrcs \reg1,\reg1,#0x00000080
sub r1,opcodes,#0x100
ldrb z80f,[r1,\reg1]
orrcs z80f,z80f,#1<<CFlag
.endm
.macro opRRCA
opRRC z80a, z80a, 25
mov z80a,z80a,lsl#24
fetch 8
.endm
.macro opRRCH reg
opRRC r0, \reg, 25
and \reg,\reg,#0x00FF0000 ;@mask out low
orr \reg,\reg,r0,lsl#24
fetch 8
.endm