From 549f71675e7e5f04c727ff80d6486ea40eb14db2 Mon Sep 17 00:00:00 2001 From: Remy van Elst Date: Tue, 30 Apr 2024 14:05:33 +0200 Subject: [PATCH 1/4] Update version --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4f66f1b..3ea36d3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,7 +1,7 @@ cmake_minimum_required(VERSION 3.10) set(CMAKE_CXX_STANDARD 11) set(CMAKE_CXX_STANDARD_REQUIRED ON) -project(AXPBox VERSION 0.1) +project(AXPBox VERSION 1.1.2) # Source files file(GLOB srcs src/*.cpp src/base/*.cpp src/gui/*.cpp) From b9a7de41face6bde9e6ab20fba9b85b37cd1b8c2 Mon Sep 17 00:00:00 2001 From: Remy van Elst Date: Tue, 30 Apr 2024 14:07:20 +0200 Subject: [PATCH 2/4] Add nullptr check and log. Hit this with icache enabled when trying to do ARC stuff from here: https://archive.org/details/es40-1211e8a / https://www.youtube.com/watch?v=V2Nr1O85hss&t=0s --- src/AlphaCPU.hpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/AlphaCPU.hpp b/src/AlphaCPU.hpp index 720cc19..6d687cf 100644 --- a/src/AlphaCPU.hpp +++ b/src/AlphaCPU.hpp @@ -494,8 +494,12 @@ inline int CAlphaCPU::get_icache(u64 address, u32 *data) { return result; } - memcpy(state.icache[state.next_icache].data, cSystem->PtrToMem(p_a), + char* addr = cSystem->PtrToMem(p_a); + if(addr) + memcpy(state.icache[state.next_icache].data, addr, ICACHE_LINE_SIZE * 4); + else + printf("PtrToMem(p_a) == nullptr! Address: %lu.\n", p_a); state.icache[state.next_icache].valid = true; state.icache[state.next_icache].asn = state.asn; From 7a3e8c5829fabf8da6acfb0ab54bec01a7eb6bfe Mon Sep 17 00:00:00 2001 From: Remy van Elst Date: Tue, 30 Apr 2024 14:08:33 +0200 Subject: [PATCH 3/4] Port code from @gdwnldsKSC/es40 regarding S3 --- src/AlphaCPU_vmspal.cpp | 8 +- src/S3Trio64.cpp | 257 +++++++++++++++++++++++++++++++++++----- src/S3Trio64.hpp | 18 ++- src/StdAfx.hpp | 27 +++++ 4 files changed, 276 insertions(+), 34 deletions(-) diff --git a/src/AlphaCPU_vmspal.cpp b/src/AlphaCPU_vmspal.cpp index 0e4a1f5..61cccb2 100644 --- a/src/AlphaCPU_vmspal.cpp +++ b/src/AlphaCPU_vmspal.cpp @@ -84,8 +84,8 @@ #define r30 state.r[30] #define r31 state.r[31] -#define hw_stq(a, b) cSystem->WriteMem(a & ~U64(0x7), 64, b, this) -#define hw_stl(a, b) cSystem->WriteMem(a & ~U64(0x3), 32, b, this) +#define hw_stq(a, b) cSystem->WriteMem((a) & ~U64(0x7), 64, b, this) +#define hw_stl(a, b) cSystem->WriteMem((a) & ~U64(0x3), 32, b, this) #define stq(a, b) \ if (virt2phys(a, &phys_address, ACCESS_WRITE, NULL, 0)) \ return -1; \ @@ -106,8 +106,8 @@ if (virt2phys(a, &phys_address, ACCESS_READ, NULL, 0)) \ return -1; \ b = (char)(cSystem->ReadMem(phys_address, 8, this)); -#define hw_ldq(a, b) b = cSystem->ReadMem(a & ~U64(0x7), 64, this) -#define hw_ldl(a, b) b = sext_u64_32(cSystem->ReadMem(a & ~U64(0x3), 32, this)); +#define hw_ldq(a, b) b = cSystem->ReadMem((a) & ~U64(0x7), 64, this) +#define hw_ldl(a, b) b = sext_u64_32(cSystem->ReadMem((a) & ~U64(0x3), 32, this)); #define hw_ldbu(a, b) b = cSystem->ReadMem(a, 8, this) /** diff --git a/src/S3Trio64.cpp b/src/S3Trio64.cpp index e98da0f..850b3f2 100644 --- a/src/S3Trio64.cpp +++ b/src/S3Trio64.cpp @@ -323,6 +323,25 @@ void CS3Trio64::init() { state.sequencer.reset2 = 1; state.sequencer.extended_mem = 1; // display mem greater than 64K state.sequencer.odd_even = 1; // use sequential addressing mode + state.sequencer.sr8 = 0; // unlock extended sequencer, default 00h on powerup + state.sequencer.sr9 = 0; // Extended Sequencer Register 9 (SR9) + state.sequencer.srA = 0; // External Bus Request Control (SRA) + state.sequencer.srB = 0; // Miscellaneous Extended Sequencer Register (SRB) + state.sequencer.sr10 = 0; // CLK Value Low Register (UNLK_EXSR) (SR10) + state.sequencer.sr11 = 0; // MCLK Value High Register (SR11) + state.sequencer.sr12 = 0; // DCLK Value Low Register (SR12) + state.sequencer.sr13 = 0; // DCLK Value High Register (SR13) + state.sequencer.sr14 = 0; // CLKSYN Control 1 Register (SR14) + state.sequencer.sr14 = 0; // CLKSYN Control 1 Register (SR14) + state.sequencer.sr15 = 0; // CLKSYN Control 2 Register (SR15) + state.sequencer.sr15 = 0; // CLKSYN Control 2 Register (SR15) + state.sequencer.sr18 = 0; // RAMDAC/CLKSYN Control Register (SR18) + state.sequencer.sr18 = 0; // RAMDAC/CLKSYN Control Register (SR18) + state.sequencer.sr1a = 0; // not sure what's going on here with these, 86box says to (internal use maybe?) + state.sequencer.sr1a = 0; // not sure what's going on here with these, 86box says to (internal use maybe?) + state.sequencer.sr1b = 0; // just throw the value in here if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20) { + state.sequencer.sr1b = 0; // just throw the value in here if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20) { + state.memsize = 0x40000; state.memory = new u8[state.memsize]; @@ -330,12 +349,14 @@ void CS3Trio64::init() { state.last_bpp = 8; + state.CRTC.reg[0x70] = 0; state.CRTC.reg[0x09] = 16; + state.CRTC.reg[0x2E] = 0x11; // Device low ID register, 0x10 for Trio32, 0x11 for Trio64 + state.CRTC.reg[0x30] = 0xE1; // Chip ID/REV Register (CHIP-ID/REV) (CR30) - 0xE1H on powerup. + state.CRTC.reg[0x36] = 0x1A; // Configuration 1 Register (CONF_REG1) (CR36) - set per 86box for PCI startup + state.CRTC.reg[0x40] = 0x30; // System Configuration Register (SYS_CNFG) (CR40) - 0x30H on powerup. state.graphics_ctrl.memory_mapping = 3; // color text mode state.vga_mem_updated = 1; - - printf("%s: $Id: S3Trio64.cpp,v 1.20 2008/05/31 15:47:10 iamcamiel Exp $\n", - devid_string); } /** @@ -713,6 +734,12 @@ u32 CS3Trio64::io_read(u32 address, int dsize) { data = read_b_3c5(); break; + case 0x3c6: + data = read_b_3c6(); + break; + + case 0x3C7: + case 0x3C8: case 0x3c9: data = read_b_3c9(); break; @@ -789,6 +816,9 @@ void CS3Trio64::io_write_b(u32 address, u8 data) { write_b_3c2(data); break; + case 0x3c3: // do nothing, we're not writing anything. VGA subsystem setup. + break; + case 0x3c4: write_b_3c4(data); break; @@ -821,6 +851,10 @@ void CS3Trio64::io_write_b(u32 address, u8 data) { write_b_3cf(data); break; + case 0x3da: + write_b_3da(data); + break; + case 0x3b4: case 0x3d4: write_b_3d4(data); @@ -1320,11 +1354,15 @@ void CS3Trio64::write_b_3c5(u8 value) { u8 charmap1; u8 charmap2; +#ifdef DEBUG_VGA + printf("VGA: 3c5 WRITE INDEX=0x%02x BINARY VALUE=" PRINTF_BINARY_PATTERN_INT8 " HEX VALUE=0x%02x\n", state.sequencer.index, PRINTF_BYTE_TO_BINARY_INT8(value), value); +#endif + switch (state.sequencer.index) { // Sequencer: reset register - case 0: + case 0x00: #if defined(DEBUG_VGA) - printf("write 0x3c5: sequencer reset: value=0x%02x \n", (unsigned)value); + printf("write 0x3c5: sequencer reset: value=0x%02x \n", (unsigned) value); #endif if (state.sequencer.reset1 && ((value & 0x01) == 0)) { state.sequencer.char_map_select = 0; @@ -1340,7 +1378,7 @@ void CS3Trio64::write_b_3c5(u8 value) { break; // Sequencer: clocking mode register - case 1: + case 0x01: #if defined(DEBUG_VGA) printf("io write 3c5=%02x: clocking mode reg: ignoring \n", (unsigned)value); @@ -1350,14 +1388,14 @@ void CS3Trio64::write_b_3c5(u8 value) { break; // Sequencer: map mask register - case 2: + case 0x02: state.sequencer.map_mask = (value & 0x0f); for (i = 0; i < 4; i++) state.sequencer.map_mask_bit[i] = (value >> i) & 0x01; break; // Sequencer: character map select register - case 3: + case 0x03: state.sequencer.char_map_select = value; charmap1 = value & 0x13; if (charmap1 > 3) @@ -1378,7 +1416,7 @@ void CS3Trio64::write_b_3c5(u8 value) { break; // Sequencer: memory mode register - case 4: + case 0x4: state.sequencer.extended_mem = (value >> 1) & 0x01; state.sequencer.odd_even = (value >> 2) & 0x01; state.sequencer.chain_four = (value >> 3) & 0x01; @@ -1391,6 +1429,70 @@ void CS3Trio64::write_b_3c5(u8 value) { #endif break; + case 0x09: + state.sequencer.sr9 = value & 0x80; // only one bit used, rest reserved + break; + + case 0x08: // Unlock Extended Sequencer (SR8) + state.sequencer.sr8 = value; + break; + + case 0x0A: // External Bus Request Control Register (SRA) + state.sequencer.srA = value; + break; + + case 0x0B: // // Miscellaneous Extended Sequencer Register (SRB) + state.sequencer.srB = value; + break; + + case 0x10: // CLK Value Low Register (UNLK_EXSR) (SR10) + state.sequencer.sr10 = value; + break; + + case 0x11: // MCLK Value High Register (SR11) + state.sequencer.sr11 = value; + break; + + case 0x12: // DCLK Value Low Register(SR12) + state.sequencer.sr12 = value; + break; + + case 0x13: // DCLK Value High Register (SR13) + state.sequencer.sr13 = value; + break; + + case 0x14: // CLKSYN Control 1 Register SR14 + state.sequencer.sr14 = value; + break; + + case 0x15: // CLKSYN Control 2 Register SR15 + state.sequencer.sr15 = value; + break; + + case 0x18: // RAMDAC/CLKSYN Control Register (SR18) + state.sequencer.sr18 = value; + break; + + /* NOT DOCUMENTED - Sequence Register 1A & 1B - 86box for handling this is + + if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20) { + svga->seqregs[svga->seqaddr] = val; + switch (svga->seqaddr) { + case 0x12: + case 0x13: + svga_recalctimings(svga); + return; + default: + break; */ + + case 0x1A: + state.sequencer.sr1a = value; + break; + + case 0x1B: + state.sequencer.sr1b = value; + break; + default: FAILURE_1(NotImplemented, "io write 3c5: index %u unhandled", (unsigned)state.sequencer.index); @@ -1414,6 +1516,12 @@ void CS3Trio64::write_b_3c6(u8 value) { // indexing into color register state.pel.data[] } +u8 CS3Trio64::read_b_3c6() +{ + return state.pel.mask; +} + + /** * Write VGA DAC Address Read Mode register (0x3c7) * @@ -2372,14 +2480,31 @@ void CS3Trio64::write_b_3d4(u8 value) { **/ void CS3Trio64::write_b_3d5(u8 value) { - /* CRTC Registers */ - if (state.CRTC.address > 0x18) { -#if defined(DEBUG_VGA) - printf("write: invalid CRTC register 0x%02x ignored", - (unsigned)state.CRTC.address); -#endif - return; - } + + #ifdef DEBUG_VGA + printf("VGA: 3d5 WRITE CRTC register=0x%02x BINARY VALUE=" PRINTF_BINARY_PATTERN_INT8 " HEX VALUE=0x%02x\n", state.CRTC.address, PRINTF_BYTE_TO_BINARY_INT8(value), value); + #endif + int mask = 0; + /* CRTC Registers */ + if((state.CRTC.address > 0x18) && (state.CRTC.address != 0x36) && (state.CRTC.address != 0x38) && (state.CRTC.address != 0x39) && \ + (state.CRTC.address != 0x42) && (state.CRTC.address != 0x66) && (state.CRTC.address != 0x6b) && (state.CRTC.address != 0x6c) && \ + (state.CRTC.address != 0x5c) && (state.CRTC.address != 0x42) && (state.CRTC.address != 0x40) && (state.CRTC.address != 0x31) && \ + (state.CRTC.address != 0x50) && (state.CRTC.address != 51)) + { + #if defined(DEBUG_VGA) + printf("VGA 3D5 Write WARNING: UNVERIFIED CRTC register 0x%02x but still written\n", + (unsigned) state.CRTC.address); + #endif + } + + if (state.CRTC.address > 0x70) + { + #if defined(DEBUG_VGA) + printf("write: invalid CRTC register 0x%02x ignored\n", + (unsigned)state.CRTC.address); + #endif + return; + } if (state.CRTC.write_protect && (state.CRTC.address < 0x08)) { if (state.CRTC.address == 0x07) { @@ -2467,6 +2592,38 @@ void CS3Trio64::write_b_3d5(u8 value) { state.line_compare |= state.CRTC.reg[0x18]; redraw_area(0, 0, old_iWidth, old_iHeight); break; + + case 0x31: // Memory Configuration Register (MEM_CFG) (CR31) + break; + + case 0x36: // Configuration 1 Register (CONF_REG1) (CR36) + break; + + case 0x38: // unlock S3 VGA registers (CR30 - CR3C) + case 0x39: // unlock System Control, System Extension, and Strapping registers (CR40-CR4F, CR50-CR6D) + case 0x40: // System Control Register (SYS_CTRL) (CR40) + break; + + case 0x42: // Mode Control Register (MODE_CTL) (CR42) + break; + + case 0x50: // Extended System Cont 1 Register (EXT_SCTL_1) (CR50) + break; // FIXME: Might need some logic here. 86box code vid_s3 line 2646 + + case 0x51: // Extended System Cont 2 Register (EXT_SCTL_2) (CR51) + break; // FIXME: Might need logic here. 86box code vid_s3 line 2701 + + case 0x5c: // Extended RAMDAC Control Register (EX_DAC_CT) (CR55) + break; + + case 0x66: // Extended Miscellaneous Control 1 Register (EXT-MISC-1) (CR66) - we don't do anything here + break; + + case 0x6b: // Extended BIOS Flag 3 Register (EBIOS-FLG3) (CR6B) - Internal firmware reserved + break; + + case 0x6c: // Extended BIOS Flag 4 Register (EBIOS-FLG4) (CR6C) - Internal firmware reserved + break; } } } @@ -2589,34 +2746,45 @@ u8 CS3Trio64::read_b_3c4() { return state.sequencer.index; } **/ u8 CS3Trio64::read_b_3c5() { switch (state.sequencer.index) { - case 0: /* sequencer: reset */ + case 0x0: /* sequencer: reset */ #if defined(DEBUG_VGA) BX_DEBUG(("io read 0x3c5: sequencer reset")); #endif return (state.sequencer.reset1 ? 1 : 0) | (state.sequencer.reset2 ? 2 : 0); - break; - case 1: /* sequencer: clocking mode */ + case 0x1: /* sequencer: clocking mode */ #if defined(DEBUG_VGA) BX_DEBUG(("io read 0x3c5: sequencer clocking mode")); #endif return state.sequencer.reg1; - break; - case 2: /* sequencer: map mask register */ + case 0x2: /* sequencer: map mask register */ return state.sequencer.map_mask; - break; - case 3: /* sequencer: character map select register */ + case 0x3: /* sequencer: character map select register */ return state.sequencer.char_map_select; - break; - case 4: /* sequencer: memory mode register */ + case 0x4: /* sequencer: memory mode register */ return (state.sequencer.extended_mem << 1) | (state.sequencer.odd_even << 2) | (state.sequencer.chain_four << 3); - break; + + case 0x9: + return state.sequencer.sr9; + + case 0xA: // External Bus Request Control Register (SRA) + return state.sequencer.srA; + + case 0x10: /* sequencer: SR10 */ + return state.sequencer.sr10; + + case 0x12: + return state.sequencer.sr12; + + case 0x15: + return state.sequencer.sr15; default: + printf("FAIL VGA: 3c5 READ INDEX=0x%02x %d\n", state.sequencer.index, state.sequencer.index); FAILURE_1(NotImplemented, "io read 0x3c5: index %u unhandled", (unsigned)state.sequencer.index); } @@ -2763,12 +2931,38 @@ u8 CS3Trio64::read_b_3d4() { return state.CRTC.address; } * For a description of CRTC Registers, see CCirrus::write_b_3d4. **/ u8 CS3Trio64::read_b_3d5() { - if (state.CRTC.address > 0x18) { + if((state.CRTC.address > 0x18) && (state.CRTC.address != 0x2e) && (state.CRTC.address != 0x2f) && (state.CRTC.address != 0x36) && \ + (state.CRTC.address != 0x40) && (state.CRTC.address != 0x42) && (state.CRTC.address != 0x30) && (state.CRTC.address != 0x6b) && \ + (state.CRTC.address != 0x6c) && (state.CRTC.address != 0x67)) + { FAILURE_1(NotImplemented, "io read: invalid CRTC register 0x%02x \n", (unsigned)state.CRTC.address); } - return state.CRTC.reg[state.CRTC.address]; + switch (state.CRTC.address) + { + case 0x2e: // Chip ID for S3, 0x11 == Trio64 (rev 00h) / Trio64V+ (rev 40h) +#ifdef DEBUG_VGA + printf("VGA: CRTC CHIP ID READ 0x2E HARDCODED 0x11 For TRIO64\n"); +#endif + return 0x11; + + case 0x2f: // Revision ID, low byte of the PCI ID, in our case for Trio64, this will just be 0x00 +#ifdef DEBUG_VGA + printf("VGA: CRTC CHIP REVISION ID READ 0x2F HARDCODED 0x11 FOR TRIO64\n"); +#endif + return 0x00; + break; + + + return state.CRTC.reg[state.CRTC.address]; + default: +#ifdef DEBUG_VGA + printf("VGA: 3d5 READ CRTC register=0x%02x BINARY VALUE=" PRINTF_BINARY_PATTERN_INT8 " HEX VALUE=0x%02x\n", state.CRTC.address, \ + PRINTF_BYTE_TO_BINARY_INT8(state.CRTC.reg[state.CRTC.address]), state.CRTC.reg[state.CRTC.address]); +#endif + return state.CRTC.reg[state.CRTC.address]; + } } /** @@ -2794,6 +2988,11 @@ u8 CS3Trio64::read_b_3d5() { * register, to generate an interrupt at the start of *the vertical retrace. \endcode **/ +// above comment applies to the read, not this write function +void CS3Trio64::write_b_3da(u8 value) { + state.port3da = value; +} + u8 CS3Trio64::read_b_3da() { /* Input Status 1 (color emulation modes) */ diff --git a/src/S3Trio64.hpp b/src/S3Trio64.hpp index e178d90..de666a6 100644 --- a/src/S3Trio64.hpp +++ b/src/S3Trio64.hpp @@ -91,6 +91,7 @@ class CS3Trio64 : public CVGA { void write_b_3cf(u8 data); void write_b_3d4(u8 data); void write_b_3d5(u8 data); + void write_b_3da(u8 data); u8 read_b_3c0(); u8 read_b_3c1(); @@ -98,6 +99,7 @@ class CS3Trio64 : public CVGA { u8 read_b_3c3(); u8 read_b_3c4(); u8 read_b_3c5(); + u8 read_b_3c6(); u8 read_b_3c9(); u8 read_b_3ca(); u8 read_b_3cc(); @@ -143,6 +145,7 @@ class CS3Trio64 : public CVGA { 4]; /**< Currently allocates the tile as large as needed. */ unsigned x_tilesize; unsigned y_tilesize; + u8 port3da; struct SS3_attr { bool flip_flop; /* 0 = address, 1 = data-write */ @@ -194,6 +197,19 @@ class CS3Trio64 : public CVGA { bool extended_mem; bool odd_even; bool chain_four; + u8 sr9; // Extended Sequencer Register 9 (SR9) + u8 sr8; // unlock extended sequencer (SR8) + u8 srA; // External Bus Request Control (SRA) + u8 srB; // Miscellaneous Extended Sequencer Register (SRB) + u8 sr10; // CLK Value Low Register (UNLK_EXSR) (SR10) + u8 sr11; // MCLK Value High Register (SR11) + u8 sr12; // DCLK Value Low Register (SR12) + u8 sr13; // DCLK Value High Register (SR13) + u8 sr14; // CLKSYN Control 1 Register (SR14) + u8 sr15; // CLKSYN Control 2 Register (SR15) + u8 sr18; // RAMDAC/CLKSYN Control Register (SR18) + u8 sr1a; // SR1A ? - + u8 sr1b; // SR1B ? } sequencer; struct SS3_pel { @@ -236,7 +252,7 @@ class CS3Trio64 : public CVGA { struct SS3_crtc { u8 address; - u8 reg[0x20]; + u8 reg[0x70]; bool write_protect; } CRTC; } state; diff --git a/src/StdAfx.hpp b/src/StdAfx.hpp index 649a334..0f717cb 100644 --- a/src/StdAfx.hpp +++ b/src/StdAfx.hpp @@ -213,4 +213,31 @@ inline char printable(char c) { #endif #endif + +/* --- PRINTF_BYTE_TO_BINARY macro's --- */ +#define PRINTF_BINARY_PATTERN_INT8 "%c%c%c%c%c%c%c%c" +#define PRINTF_BYTE_TO_BINARY_INT8(i) \ + (((i) & 0x80ll) ? '1' : '0'), \ + (((i) & 0x40ll) ? '1' : '0'), \ + (((i) & 0x20ll) ? '1' : '0'), \ + (((i) & 0x10ll) ? '1' : '0'), \ + (((i) & 0x08ll) ? '1' : '0'), \ + (((i) & 0x04ll) ? '1' : '0'), \ + (((i) & 0x02ll) ? '1' : '0'), \ + (((i) & 0x01ll) ? '1' : '0') + +#define PRINTF_BINARY_PATTERN_INT16 \ + PRINTF_BINARY_PATTERN_INT8 PRINTF_BINARY_PATTERN_INT8 +#define PRINTF_BYTE_TO_BINARY_INT16(i) \ + PRINTF_BYTE_TO_BINARY_INT8((i) >> 8), PRINTF_BYTE_TO_BINARY_INT8(i) +#define PRINTF_BINARY_PATTERN_INT32 \ + PRINTF_BINARY_PATTERN_INT16 PRINTF_BINARY_PATTERN_INT16 +#define PRINTF_BYTE_TO_BINARY_INT32(i) \ + PRINTF_BYTE_TO_BINARY_INT16((i) >> 16), PRINTF_BYTE_TO_BINARY_INT16(i) +#define PRINTF_BINARY_PATTERN_INT64 \ + PRINTF_BINARY_PATTERN_INT32 PRINTF_BINARY_PATTERN_INT32 +#define PRINTF_BYTE_TO_BINARY_INT64(i) \ + PRINTF_BYTE_TO_BINARY_INT32((i) >> 32), PRINTF_BYTE_TO_BINARY_INT32(i) +/* --- end macros --- */ + #endif // !defined(INCLUDED_STDAFX_H) From 09b9e882a15d50be77bb37256f2c0e89aefbf2af Mon Sep 17 00:00:00 2001 From: Remy van Elst Date: Sat, 4 May 2024 20:57:22 +0200 Subject: [PATCH 4/4] Port relevant bits from - 46b2a88fdadd618e48eb7e0dc52abc1abf37ef51 - 73b8ffa32629eca039fc13f0e3cb42b1c3a38d9f - 8c1e0cae82f42189d45eca39730d672885bb1816 --- src/S3Trio64.cpp | 16 +++++++++++++--- src/S3Trio64.hpp | 1 + src/Serial.cpp | 31 +++++++++++++++++-------------- 3 files changed, 31 insertions(+), 17 deletions(-) diff --git a/src/S3Trio64.cpp b/src/S3Trio64.cpp index 850b3f2..848afc9 100644 --- a/src/S3Trio64.cpp +++ b/src/S3Trio64.cpp @@ -327,6 +327,7 @@ void CS3Trio64::init() { state.sequencer.sr9 = 0; // Extended Sequencer Register 9 (SR9) state.sequencer.srA = 0; // External Bus Request Control (SRA) state.sequencer.srB = 0; // Miscellaneous Extended Sequencer Register (SRB) + state.sequencer.srD = 0; // Extended Sequencer Register (EX_SR_D) (SRD) 00H poweron state.sequencer.sr10 = 0; // CLK Value Low Register (UNLK_EXSR) (SR10) state.sequencer.sr11 = 0; // MCLK Value High Register (SR11) state.sequencer.sr12 = 0; // DCLK Value Low Register (SR12) @@ -2774,6 +2775,12 @@ u8 CS3Trio64::read_b_3c5() { case 0xA: // External Bus Request Control Register (SRA) return state.sequencer.srA; + case 0x0b: + return state.sequencer.srB; + + case 0x0D: + return state.sequencer.srD; + case 0x10: /* sequencer: SR10 */ return state.sequencer.sr10; @@ -2783,6 +2790,9 @@ u8 CS3Trio64::read_b_3c5() { case 0x15: return state.sequencer.sr15; + case 0x18: + return state.sequencer.sr18; + default: printf("FAIL VGA: 3c5 READ INDEX=0x%02x %d\n", state.sequencer.index, state.sequencer.index); FAILURE_1(NotImplemented, "io read 0x3c5: index %u unhandled", @@ -2931,9 +2941,9 @@ u8 CS3Trio64::read_b_3d4() { return state.CRTC.address; } * For a description of CRTC Registers, see CCirrus::write_b_3d4. **/ u8 CS3Trio64::read_b_3d5() { - if((state.CRTC.address > 0x18) && (state.CRTC.address != 0x2e) && (state.CRTC.address != 0x2f) && (state.CRTC.address != 0x36) && \ - (state.CRTC.address != 0x40) && (state.CRTC.address != 0x42) && (state.CRTC.address != 0x30) && (state.CRTC.address != 0x6b) && \ - (state.CRTC.address != 0x6c) && (state.CRTC.address != 0x67)) + if((state.CRTC.address > 0x70) && (state.CRTC.address != 0x2e) && (state.CRTC.address != 0x2f) && (state.CRTC.address != 0x36) && + (state.CRTC.address != 0x40) && (state.CRTC.address != 0x42) && (state.CRTC.address != 0x30) && (state.CRTC.address != 0x31) && + (state.CRTC.address != 0x32) && (state.CRTC.address != 0x6b) && (state.CRTC.address != 0x6c) && (state.CRTC.address != 0x67)) { FAILURE_1(NotImplemented, "io read: invalid CRTC register 0x%02x \n", (unsigned)state.CRTC.address); diff --git a/src/S3Trio64.hpp b/src/S3Trio64.hpp index de666a6..e2f7fda 100644 --- a/src/S3Trio64.hpp +++ b/src/S3Trio64.hpp @@ -201,6 +201,7 @@ class CS3Trio64 : public CVGA { u8 sr8; // unlock extended sequencer (SR8) u8 srA; // External Bus Request Control (SRA) u8 srB; // Miscellaneous Extended Sequencer Register (SRB) + u8 srD; // Extended Sequencer Register (EX_SR_D) (SRD) u8 sr10; // CLK Value Low Register (UNLK_EXSR) (SR10) u8 sr11; // MCLK Value High Register (SR11) u8 sr12; // DCLK Value Low Register (SR12) diff --git a/src/Serial.cpp b/src/Serial.cpp index 2ecbe5d..4ee1b13 100644 --- a/src/Serial.cpp +++ b/src/Serial.cpp @@ -639,23 +639,26 @@ void CSerial::WaitForConnection() { state.serial_cycles = 0; - // Send some control characters to the telnet client to handle - // character-at-a-time mode. - sprintf(buffer, telnet_options, IAC, DO, TELOPT_ECHO); - this->write(buffer); + if (state.iNumber != 1) // don't send if serial #1, kgdb support + { + // Send some control characters to the telnet client to handle + // character-at-a-time mode. + sprintf(buffer, telnet_options, IAC, DO, TELOPT_ECHO); + this->write(buffer); - sprintf(buffer, telnet_options, IAC, DO, TELOPT_NAWS); - write(buffer); + sprintf(buffer, telnet_options, IAC, DO, TELOPT_NAWS); + write(buffer); - sprintf(buffer, telnet_options, IAC, DO, TELOPT_LFLOW); - this->write(buffer); + sprintf(buffer, telnet_options, IAC, DO, TELOPT_LFLOW); + this->write(buffer); - sprintf(buffer, telnet_options, IAC, WILL, TELOPT_ECHO); - this->write(buffer); + sprintf(buffer, telnet_options, IAC, WILL, TELOPT_ECHO); + this->write(buffer); - sprintf(buffer, telnet_options, IAC, WILL, TELOPT_SGA); - this->write(buffer); + sprintf(buffer, telnet_options, IAC, WILL, TELOPT_SGA); + this->write(buffer); - sprintf(s, "This is serial port #%d on ES40 Emulator\r\n", state.iNumber); - this->write(s); + sprintf(s, "This is serial port #%d on the AXPBox Emulator\r\n", state.iNumber); + this->write(s); + } }