generated from chipsalliance/chisel-template
-
Notifications
You must be signed in to change notification settings - Fork 0
/
makefile
37 lines (25 loc) · 847 Bytes
/
makefile
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
FISH_CORE_HOME := $(shell pwd)
Linux_payload := ${FISH_CORE_HOME}/sim/ready_to_run/fw_payload.elf
sim_dir := ${FISH_CORE_HOME}/sim
clean_dir := ${FISH_CORE_HOME}/project \
${FISH_CORE_HOME}/.venv \
${FISH_CORE_HOME}/target \
${FISH_CORE_HOME}/sim/.xmake \
${FISH_CORE_HOME}/sim/.cache \
${FISH_CORE_HOME}/sim/build \
define check_and_create_folder
@if [ ! -d "$(1)" ]; then \
echo "Creating folder $(1)"; \
mkdir -p $(1); \
fi
endef
gen_fish_soc_verilog:
$(call check_and_create_folder,${FISH_CORE_HOME}/sim/vsrc)
cd ${FISH_CORE_HOME} && sbt "runMain leesum.Core.gen_FishSoc"
build_sim:gen_fish_soc_verilog
cd ${sim_dir} && xmake
linux:build_sim
cd ${sim_dir} && xmake run Vtop --file ${Linux_payload} --clk 500000000
clean_all:
rm -rf ${clean_dir}
.PHONY: gen_verilog build_sim linux