[Backport] 8276799: Implementation of JEP 422: Linux/RISC-V Port

Summary: sync with riscv upstream riscv-port-jdk11u
  This is a combination of multiple patches.
Revert "[Misc] Add failed test cases to linux-riscv problem list"
Revert "[Misc] RISC-V backend build broken after merging VectorAPI"
Revert "[Backport] 8297476: Increase InlineSmallCode default from 1000 to 2500 for RISC-V"
Revert "[RISCV] Backport ShenandoahGC specific code"
Revert "[Backport] 8296771: RISC-V: C2: assert(false) failed: bad AD file"
Revert "[Misc] Fix ported TestLibmIntrinsics.java"
Revert "[Backport] 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic"
Revert "[Backport] 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub"
Revert "[Backport] 8278743: riscv: Remove the x4 register saving logic in Java frames"
Revert "[Backport] 8287418: riscv: Fix correctness issue of MacroAssembler::movptr"
Revert "[RISCV] Backport RVV and support RVV-0.7.1"
Revert "[RISCV] support paired memory instruction in CSky (dragonwell-project#217)"
Revert "[Backport] Backport RISC-V backend code from the openjdk/riscv-port repo's initial load"
8276799: Implementation of JEP 422: Linux/RISC-V Port
8283737: riscv: MacroAssembler::stop() should emit fixed-length instruction sequence
8285437: riscv: Fix MachNode size mismatch for MacroAssembler::verify_oops*
8287418: riscv: Fix correctness issue of MacroAssembler::movptr
8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub
8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic
8291952: riscv: Remove PRAGMA_NONNULL_IGNORED
8308277: RISC-V: Improve vectorization of Match.sqrt() on floats
8282306: os::is_first_C_frame(frame*) crashes on invalid link access
[RISCV] support paired memory instruction in CSky (dragonwell-project#217)
[RISCV] Backport RVV and support RVV-0.7.1
[Misc] Fix build/test failre after riscv port

Test Plan: jtreg tier1~3

Reviewed-by:

Issue: https://aone.alibaba-inc.com/v2/project/355606/req/55189627

CR:

make/autoconf/build-aux/autoconf-config.guess

@@ -1000,9 +1000,6 @@ EOF
     ppc:Linux:*:*)
 	echo powerpc-unknown-linux-gnu
 	exit ;;
-    riscv64:Linux:*:*)
-	echo riscv64-unknown-linux-gnu
-	exit ;;
     s390:Linux:*:* | s390x:Linux:*:*)
 	echo ${UNAME_MACHINE}-ibm-linux
 	exit ;;

make/autoconf/build-aux/autoconf-config.sub

@@ -302,7 +302,6 @@ case $basic_machine in
 	| pdp10 | pdp11 | pj | pjl \
 	| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
 	| pyramid \
-	| riscv64 \
 	| score \
 	| sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
 	| sh64 | sh64le \
@@ -384,7 +383,6 @@ case $basic_machine in
 	| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
 	| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
 	| pyramid-* \
-	| riscv64-* \
 	| romp-* | rs6000-* \
 	| sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
 	| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \

make/autoconf/hotspot.m4

@@ -371,7 +371,7 @@ AC_DEFUN_ONCE([HOTSPOT_SETUP_JVM_FEATURES],
   if HOTSPOT_CHECK_JVM_FEATURE(shenandoahgc); then
     if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86" || \
        test "x$OPENJDK_TARGET_CPU" = "xaarch64" || \
-       test "x$OPENJDK_TARGET_CPU_ARCH" = "xriscv"; then
+       test "x$OPENJDK_TARGET_CPU" = "xriscv64"; then
       AC_MSG_RESULT([yes])
     else
       DISABLED_JVM_FEATURES="$DISABLED_JVM_FEATURES shenandoahgc"

make/autoconf/libraries.m4

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -130,10 +130,9 @@ AC_DEFUN_ONCE([LIB_SETUP_LIBRARIES],
     BASIC_JVM_LIBS="$BASIC_JVM_LIBS -lthread"
   fi
 
-  # Programs which use C11 or C++11 atomics, like #include <atomic>,
-  # generally must link against -latomic on RISC-V
+  # Because RISC-V only has word-sized atomics, it requries libatomic where
+  # other common architectures do not.  So link libatomic by default.
   if test "x$OPENJDK_TARGET_OS" = xlinux && test "x$OPENJDK_TARGET_CPU" = xriscv64; then
-    BASIC_JDKLIB_LIBS="$BASIC_JDKLIB_LIBS -latomic"
     BASIC_JVM_LIBS="$BASIC_JVM_LIBS -latomic"
   fi
 

make/autoconf/platform.m4

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it

make/hotspot/gensrc/GensrcAdlc.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013, 2021, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2013, 2022, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -150,6 +150,12 @@ ifeq ($(call check-jvm-feature, compiler2), true)
       $d/os_cpu/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH).ad \
     )))
 
+  ifeq ($(HOTSPOT_TARGET_CPU_ARCH), riscv)
+    AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \
+        $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_CPU_ARCH)_b.ad \
+    )))
+  endif
+
   ifeq ($(call check-jvm-feature, shenandoahgc), true)
     AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \
         $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \

src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *

src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it

src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2019, SAP SE. All rights reserved.
+ * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it

src/hotspot/cpu/riscv/abstractInterpreter_riscv.cpp

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -34,7 +34,6 @@
 #include "utilities/debug.hpp"
 #include "utilities/macros.hpp"
 
-
 int AbstractInterpreter::BasicType_as_index(BasicType type) {
   int i = 0;
   switch (type) {
@@ -102,7 +101,7 @@ int AbstractInterpreter::size_activation(int max_stack,
              // frame do we need to allow max_stack words.
              (is_top_frame ? max_stack : temps + extra_args);
 
-  // On riscv64 we always keep the stack pointer 16-aligned, so we
+  // On riscv we always keep the stack pointer 16-aligned, so we
   // must round up here.
   size = align_up(size, 2);
 
@@ -134,10 +133,9 @@ void AbstractInterpreter::layout_activation(Method* method,
 #endif
 
   interpreter_frame->interpreter_frame_set_method(method);
-  // NOTE the difference in using sender_sp and
-  // interpreter_frame_sender_sp interpreter_frame_sender_sp is
-  // the original sp of the caller (the unextended_sp) and
-  // sender_sp is fp+8/16 (32bit/64bit)
+  // NOTE the difference in using sender_sp and interpreter_frame_sender_sp
+  // interpreter_frame_sender_sp is the original sp of the caller (the unextended_sp)
+  // and sender_sp is fp
   intptr_t* locals = NULL;
   if (caller->is_interpreted_frame()) {
     locals = caller->interpreter_frame_last_sp() + caller_actual_parameters - 1;
@@ -171,6 +169,7 @@ void AbstractInterpreter::layout_activation(Method* method,
     interpreter_frame->set_interpreter_frame_sender_sp(caller->sp() +
                                                        extra_locals);
   }
+
   *interpreter_frame->interpreter_frame_cache_addr() =
     method->constants()->cache();
   *interpreter_frame->interpreter_frame_mirror_addr() =

src/hotspot/cpu/riscv/assembler_riscv.cpp

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -21,6 +21,7 @@
  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  * or visit www.oracle.com if you need additional information or have any
  * questions.
+ *
  */
 
 #include <stdio.h>
@@ -34,7 +35,6 @@
 #include "memory/resourceArea.hpp"
 #include "runtime/interfaceSupport.inline.hpp"
 #include "runtime/sharedRuntime.hpp"
-#include "nativeInst_riscv.hpp"
 
 int AbstractAssembler::code_fill_byte() {
   return 0;
@@ -80,11 +80,16 @@ void Assembler::subw(Register Rd, Register Rn, int64_t decrement, Register temp)
   }
 }
 
-void Assembler::li(Register Rd, int64_t imm) {
+void Assembler::zext_w(Register Rd, Register Rs) {
+  add_uw(Rd, Rs, zr);
+}
+
+void Assembler::_li(Register Rd, int64_t imm) {
   // int64_t is in range 0x8000 0000 0000 0000 ~ 0x7fff ffff ffff ffff
   int shift = 12;
   int64_t upper = imm, lower = imm;
-  // Split imm to a lower 12-bit sign-extended part and the remainder, because addi will sign-extend the lower imm.
+  // Split imm to a lower 12-bit sign-extended part and the remainder,
+  // because addi will sign-extend the lower imm.
   lower = ((int32_t)imm << 20) >> 20;
   upper -= lower;
 
@@ -98,8 +103,7 @@ void Assembler::li(Register Rd, int64_t imm) {
     if (lower != 0) {
       addi(Rd, Rd, lower);
     }
-  }
-  else {
+  } else {
     // 32-bit integer
     Register hi_Rd = zr;
     if (upper != 0) {
@@ -113,8 +117,8 @@ void Assembler::li(Register Rd, int64_t imm) {
 }
 
 void Assembler::li64(Register Rd, int64_t imm) {
-   // Load upper 32 bits. Upper = imm[63:32], but if imm[31] = 1 or (imm[31:28] == 0x7ff && imm[19] == 1),
-   // upper = imm[63:32] + 1.
+   // Load upper 32 bits. upper = imm[63:32], but if imm[31] == 1 or
+   // (imm[31:28] == 0x7ff && imm[19] == 1), upper = imm[63:32] + 1.
    int64_t lower = imm & 0xffffffff;
    lower -= ((lower << 44) >> 44);
    int64_t tmp_imm = ((uint64_t)(imm & 0xffffffff00000000)) + (uint64_t)lower;
@@ -209,13 +213,13 @@ void Assembler::ret() {
 
 #define INSN(NAME, REGISTER)                                   \
   void Assembler::NAME(const Address &adr, Register temp) {    \
-    switch(adr.getMode()) {                                    \
+    switch (adr.getMode()) {                                   \
       case Address::literal: {                                 \
         code_section()->relocate(pc(), adr.rspec());           \
         NAME(adr.target(), temp);                              \
         break;                                                 \
       }                                                        \
-      case Address::base_plus_offset:{                         \
+      case Address::base_plus_offset: {                        \
         int32_t offset = 0;                                    \
         baseOffset(temp, adr, offset);                         \
         jalr(REGISTER, temp, offset);                          \
@@ -366,4 +370,3 @@ Address::Address(address target, relocInfo::relocType rtype) : _base(noreg), _of
       ShouldNotReachHere();
   }
 }
-