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channels.py
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# atomic clock diagnostic TDS signals
hanford_cesium_msr = 'H1:SYS-TIMING_C_MA_A_PORT_2_SLAVE_CFC_TIMEDIFF_1'
hanford_cesium_ex = 'H1:SYS-TIMING_X_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_1'
hanford_cesium_ey = 'H1:SYS-TIMING_Y_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_1'
hanford_nts_msr = 'H1:SYS-TIMING_C_MA_A_PORT_2_SLAVE_CFC_TIMEDIFF_2'
hanford_cnsii_ex = 'H1:SYS-TIMING_X_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_3'
hanford_cnsii_ey = 'H1:SYS-TIMING_Y_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_3'
livingston_cesium_msr = 'L1:SYS-TIMING_C_MA_A_PORT_2_SLAVE_CFC_TIMEDIFF_1'
livingston_cesium_ex = 'L1:SYS-TIMING_X_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_1'
livingston_cesium_ey = 'L1:SYS-TIMING_Y_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_1'
livingston_nts_msr = 'L1:SYS-TIMING_C_MA_A_PORT_2_SLAVE_CFC_TIMEDIFF_2'
livingston_cnsii_ex = 'L1:SYS-TIMING_X_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_3'
livingston_cnsii_ey = 'L1:SYS-TIMING_Y_FO_A_PORT_9_SLAVE_CFC_TIMEDIFF_3'
# 16k duotone signals
hanford_duotone_ex = 'H1:CAL-PCALX_FPGA_DTONE_IN1_DQ'
hanford_duotone_ey = 'H1:CAL-PCALY_FPGA_DTONE_IN1_DQ'
livingston_duotone_ex = 'L1:CAL-PCALX_FPGA_DTONE_IN1_DQ'
livingston_duotone_ex = 'L1:CAL-PCALY_FPGA_DTONE_IN1_DQ'
# 16k IRIG-B signals
hanford_irigb_ex = 'H1:CAL-PCALX_IRIGB_OUT_DQ'
hanford_irigb_ey = 'H1:CAL-PCALY_IRIGB_OUT_DQ'
livingston_irigb_ex = 'L1:CAL-PCALX_IRIGB_OUT_DQ'
livingston_irigb_ey = 'L1:CAL-PCALY_IRIGB_OUT_DQ'
# filtered duotone signals, not interesting
hanford_duotone_filtered_ex = 'H1:CAL-PCALX_DAC_FILT_DTONE_OUT_DQ'
hanford_duotone_filtered_ey = 'H1:CAL-PCALY_DAC_FILT_DTONE_OUT_DQ'