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entropy_src.hjson
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{ name: "entropy_src",
human_name: "Entropy Source",
one_line_desc: "Filters and checks raw entropy bits from a random noise source and forwards them to CSRNG",
one_paragraph_desc: '''
Entropy Source takes bits from a physically random noise source (external to Entropy Source) and produces random values in a manner that is compliant both with FIPS (through [NIST SP 800-90B][nist-sp-800-90b]) and [CC (AIS31)][bsi-ais31] recommendations.
The random values produced by Entropy Source serve as non-deterministic seeds for CSRNG.
Depending on the mode of operation, Entropy Source can apply a secure hash function to the raw noise bits for conditioning.
To detect statistical defects in the raw noise bits, Entropy Source performs multiple health checks.
[bsi-ais31]: https://www.bsi.bund.de/SharedDocs/Downloads/DE/BSI/Zertifizierung/Interpretationen/AIS_31_Functionality_classes_for_random_number_generators_e.pdf
[nist-sp-800-90b]: https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-90B.pdf
'''
// Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
cip_id: "7",
design_spec: "../doc",
dv_doc: "../doc/dv",
hw_checklist: "../doc/checklist",
sw_checklist: "/sw/device/lib/dif/dif_entropy_src",
version: "1.0.0",
life_stage: "L1",
design_stage: "D2S",
verification_stage: "V2S",
dif_stage: "S2",
clocking: [{clock: "clk_i", reset: "rst_ni"}],
bus_interfaces: [
{ protocol: "tlul", direction: "device" }
],
interrupt_list: [
{ name: "es_entropy_valid"
desc: "Asserted when entropy source bits are available."}
{ name: "es_health_test_failed"
desc: "Asserted when the alert count has been met."}
{ name: "es_observe_fifo_ready"
desc: "Asserted when the observe FIFO has filled to the threshold level."}
{ name: "es_fatal_err"
desc: "Asserted when a FIFO error occurs, or if an illegal state machine state is reached."}
],
inter_signal_list: [
{ struct: "entropy_src_hw_if",
type: "req_rsp",
name: "entropy_src_hw_if",
act: "rsp",
package: "entropy_src_pkg",
}
{ struct: "cs_aes_halt"
type: "req_rsp",
name: "cs_aes_halt"
act: "req"
package: "entropy_src_pkg"
desc: '''
Coordinate activity between CSRNG's AES and Entropy Source's SHA3.
The idea is that Entropy Source requests CSRNG's AES to halt and waits for CSRNG to acknowledge before it starts its SHA3.
While SHA3 runs, Entropy Source keeps the request high.
CSRNG may not drop the acknowledge before Entropy Source drops the request.
Current limitations:
1. During startup and in Firmware Override - Extract & Insert mode, Entropy Source makes no AES Halt requests but still activates its SHA3 engine.
2. Outside Firmware Override - Extract & Insert mode, Entropy Source may activate its SHA3 engine without requesting AES Halt, but no more than for 24 Keccak rounds (24 clock cycles) every 512 clock cycles.
'''
}
{ struct: "entropy_src_rng",
type: "req_rsp",
name: "entropy_src_rng",
act: "req",
package: "entropy_src_pkg",
}
{ struct: "entropy_src_xht",
type: "req_rsp",
name: "entropy_src_xht",
act: "req",
package: "entropy_src_pkg",
}
{ struct: "mubi8"
type: "uni"
name: "otp_en_entropy_src_fw_read"
act: "rcv"
package: "prim_mubi_pkg"
}
{ struct: "mubi8"
type: "uni"
name: "otp_en_entropy_src_fw_over"
act: "rcv"
package: "prim_mubi_pkg"
}
{ struct: "logic"
type: "uni"
name: "rng_fips"
act: "req"
width: 1
package: ""
}
],
param_list: [
# Regular parameters
{ name: "EsFifoDepth",
type: "int",
default: "4",
desc: "Number of 384-bit entries in the esfinal FIFO"
local: "false",
expose: "true"
},
{ name: "Stub",
type: "bit",
default: "0",
desc: "Stub out the core of entropy_src logic"
local: "false",
expose: "true"
},
# Note: All parameters below are local, they are not actually configurable.
# Selecting values different from the default values below might cause undefined behavior.
{ name: "ObserveFifoDepth",
type: "int unsigned",
default: "64",
desc: '''
Number of 32-bit entries in the observe FIFO.
Note that upon changing this parameter, the bit widths of the !!OBSERVE_FIFO_THRESH and !!OBSERVE_FIFO_DEPTH registers have to be manually adjusted.
''',
local: "true"
},
]
alert_list: [
{ name: "recov_alert",
desc: "This alert is triggered upon the alert health test threshold criteria not met."
}
{ name: "fatal_alert",
desc: '''
This alert triggers for any condition detected in the !!ERR_CODE register,
which includes FIFO errors, COUNTER errors, FSM state errors,
and also when integrity failures are detected on the TL-UL bus.
''',
}
],
countermeasures: [
{ name: "CONFIG.REGWEN"
desc: "Registers are protected from writes."
}
{ name: "CONFIG.MUBI"
desc: "Registers have multi-bit encoded fields."
}
{ name: "CONFIG.REDUN"
desc: "Threshold register has an inverted copy to compare against."
}
{ name: "INTERSIG.MUBI"
desc: "OTP signal used to enable software access to registers."
}
{ name: "MAIN_SM.FSM.SPARSE"
desc: "The ENTROPY_SRC main state machine uses a sparse state encoding."
}
{ name: "ACK_SM.FSM.SPARSE"
desc: "The ENTROPY_SRC ack state machine uses a sparse state encoding."
}
{ name: "RNG.BKGN_CHK"
desc: "Random number generator is protected with continuous background health checks."
}
{ name: "CTR.REDUN"
desc: "Counter hardening for all health test counters."
}
{ name: "CTR.LOCAL_ESC"
desc: "Redundant counter failures will cause a local escalation to the main state machine."
}
{ name: "ESFINAL_RDATA.BUS.CONSISTENCY"
desc: "Comparison on successive bus values for the post-conditioned entropy seed bus."
}
{ name: "TILE_LINK.BUS.INTEGRITY"
desc: "Tilelink end-to-end bus integrity scheme."
}
// See the KMAC/SHA3 module documentation for additional countermeasures provided by that design"
],
regwidth: "32",
registers: [
{ name: "ME_REGWEN",
desc: "Register write enable for module enable register",
swaccess: "rw0c",
hwaccess: "none",
fields: [
{
bits: "0",
desc: ''' When true, the !!MODULE_ENABLE register can be modified.
When false, it becomes read-only.
'''
resval: 1
}
]
},
{ name: "SW_REGUPD",
desc: "Register write enable for control and threshold registers",
swaccess: "rw0c",
hwaccess: "hro",
tags: [// Exclude from writes to these field because they cause side affects.
"excl:CsrAllTests:CsrExclAll"]
fields: [
{
bits: "0",
desc: ''' When this bit true and the MODULE_ENABLE field is false,
the REGWEN write enable bit read as true, and is distributed to
all associated control and threshold registers.
When false, these registers become read-only.
'''
resval: 1
}
]
},
{ name: "REGWEN",
desc: "Register write enable for all control registers",
swaccess: "ro", // this particular enable bit is meant to be fully HW managed
hwaccess: "hwo",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{
bits: "0",
desc: '''
This read-only write enable bit will allow write access to control and threshold registers that are associated with this bit, but only when the !!MODULE_ENABLE register is set to `kMultiBitBool4False` and the !!SW_REGUPD write enable bit is set to true.
When read as false, these registers become read-only.
'''
resval: 1
}
]
},
{ name: "REV",
desc: "Revision register",
swaccess: "ro",
hwaccess: "none",
fields: [
{ bits: "23:16",
name: "CHIP_TYPE",
desc: "Read of this register shows the type of chip using this block.",
resval: "0x1"
}
{ bits: "15:8",
name: "HW_REVISION",
desc: "Read of this register shows the revision of this block.",
resval: "0x3"
}
{ bits: "7:0",
name: "ABI_REVISION",
desc: "Read of this register shows the ABI of this block.",
resval: "0x3"
}
]
},
{ name: "MODULE_ENABLE",
desc: "Module enable register",
swaccess: "rw",
hwaccess: "hro",
regwen: "ME_REGWEN",
tags: [// Exclude from writes to these field because they cause side affects.
"excl:CsrAllTests:CsrExclAll"]
fields: [
{ bits: "3:0",
mubi: true,
name: "MODULE_ENABLE",
desc: '''
Setting this field to `kMultiBitBool4True` will enable the ENTROPY_SRC module. Setting this field to `kMultiBitBool4False` will effectively reset the module.
The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details.
'''
resval: false,
},
]
},
{ name: "CONF",
desc: "Configuration register",
swaccess: "rw",
hwaccess: "hro",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they cause side affects.
"excl:CsrAllTests:CsrExclAll"]
fields: [
{ bits: "3:0",
name: "FIPS_ENABLE",
mubi: true,
desc: '''
Setting this field to `kMultiBitBool4True` selects the FIPS/CC compliant mode (or short FIPS mode).
In this mode, the ENTROPY_SRC block can generate FIPS qualified entropy.
Additional requirements to generate FIPS qualified entropy are i) that at most one of the !!ENTROPY_CONTROL.ES_ROUTE and !!ENTROPY_CONTROL.ES_TYPE fields are set to `kMultiBitBool4True` but not both, and ii) that !!CONF.RNG_BIT_ENABLE is set to `kMultiBitBool4False`.
Setting this field to `kMultiBitBool4False` selects the boot-time / bypass mode in which the hardware conditioning is bypassed.
'''
resval: false,
},
{ bits: "7:4",
name: "ENTROPY_DATA_REG_ENABLE",
mubi: true,
desc: '''
Setting this field to `kMultiBitBool4True` will enable reading entropy values from the !!ENTROPY_DATA register.
This function also requires that the otp_en_entropy_src_fw_read input is set to `kMultiBitBool8True`.
'''
resval: false
},
{ bits: "15:12",
name: "THRESHOLD_SCOPE",
mubi: true,
desc: '''
This field controls the scope (either by-line or by-sum) of the health checks.
If set to `kMultiBitBool4True`, the Adaptive Proportion and Markov Tests will accumulate all RNG input lines into a single score, and thresholds will be applied to the sum all the entropy input lines.
If set to `kMultiBitBool4False`, the RNG input lines are all scored individually.
A statistical deviation in any one input line, be it due to coincidence or failure, will force rejection of the sample, and count toward the total alert count.
'''
resval: false
},
{ bits: "23:20",
name: "RNG_BIT_ENABLE",
mubi: true,
desc: '''
Setting this field to `kMultiBitBool4True` enables the single RNG bit mode, where only one bit is sampled.
Note that the ENTROPY_SRC block can only generate FIPS qualified entropy if this field is set to `kMultiBitBool4False`.
Additional requirements to generate FIPS qualified entropy are i) that !!CONF.FIPS_ENABLE is set to `kMultiBitBool4True`, and ii) that at most one of the !!ENTROPY_CONTROL.ES_ROUTE and !!ENTROPY_CONTROL.ES_TYPE fields but not both are set to `kMultiBitBool4True`.
'''
resval: false
},
{ bits: "25:24",
name: "RNG_BIT_SEL",
desc: '''When the above bit iset, this field selects which bit from the RNG bus will
be processed when in single RNG bit mode.
This two bit field selects the RNG bit stream:
0b00: RNG bit 0
0b01: RNG bit 1
0b10: RNG bit 2
0b11: RNG bit 3
'''
}
]
},
{ name: "ENTROPY_CONTROL",
desc: "Entropy control register",
swaccess: "rw",
hwaccess: "hro",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they cause side affects.
"excl:CsrAllTests:CsrExclAll"]
fields: [
{ bits: "3:0",
name: "ES_ROUTE",
mubi: true,
desc: '''
When this field is `kMultiBitBool4False`, the generated entropy will be forwarded out of this module to the hardware interface.
Setting this field to `kMultiBitBool4True` routes the generated entropy to the !!ENTROPY_DATA register to be read by firmware.
Note that for !!ENTROPY_DATA to become readable, also !!CONF.ENTROPY_DATA_REG_ENABLE needs to be set to `kMultiBitBool4True`.
In addition, the otp_en_entropy_src_fw_read input needs to be set to `kMultiBitBool8True`.
'''
resval: false
},
{ bits: "7:4",
name: "ES_TYPE",
mubi: true,
desc: '''
When this field is `kMultiBitBool4False`, the hardware conditioning inside the ENTROPY_SRC block is enabled.
Setting this field to `kMultiBitBool4True` will bypass the hardware conditioning.
For this to work, also !!ENTROPY_CONTROL.ES_ROUTE needs to be set to `kMultiBitBool4True` to route the unconditioned, raw entropy to the !!ENTROPY_DATA register.
Alternatively, the hardware conditioning can be bypassed by setting !!CONF.FIPS_ENABLE to `kMultiBitBool4False` to disable FIPS mode and enable bypass / boot-time mode.
In both cases, the ENTROPY_SRC block will not generate FIPS qualified entropy.
To generate FIPS qualified entropy, i) !!CONF.FIPS_ENABLE needs to be set to `kMultiBitBool4True`, ii) !!CONF.RNG_BIT_ENABLE needs to be set to `kMultiBitBool4False`, and iii) at most one of the !!ENTROPY_CONTROL.ES_ROUTE and !!ENTROPY_CONTROL.ES_TYPE fields needs to be set to `kMultiBitBool4True` but not both.
'''
resval: false
},
]
},
{ name: "ENTROPY_DATA",
desc: "Entropy data bits",
swaccess: "ro",
hwaccess: "hrw",
hwext: "true",
hwre: "true",
fields: [
{ bits: "31:0",
desc: '''
A read of this register provides generated entropy bits to firmware.
For this to work also !!CONF.ENTROPY_DATA_REG_ENABLE needs to be set to `kMultiBitBool4True`.
In addition, the otp_en_entropy_src_fw_read input needs to be set to `kMultiBitBool8True`.
'''
}
]
},
{ name: "HEALTH_TEST_WINDOWS",
desc: "Health test windows register",
swaccess: "rw",
hwaccess: "hro",
regwen: "REGWEN",
fields: [
{ bits: "15:0",
name: "FIPS_WINDOW",
desc: '''
This is the window size for all health tests.
This value is used when entropy is being tested in FIPS/CC compliance mode (for simplicity referred to as FIPS mode).
The default value is (2048 bits * 1 clock/4 bits);
'''
resval: "0x0200"
}
{ bits: "31:16",
name: "BYPASS_WINDOW",
desc: '''
This is the window size for all health tests when running in bypass mode.
This mode is active after reset for the first and only test run, or when this mode is programmed by firmware by setting !!CONF.FIPS_ENABLE to `kMultiBitBool4False`.
The default value is (384 bits * 1 clock/4 bits);
Note that currently only a window size of 384 is supported and tested (this corresponds to the register default value 0x60).
Do not use any other values, unless you know what you are doing.
'''
resval: "0x0060"
}
]
},
{ name: "REPCNT_THRESHOLDS",
desc: "Repetition count test thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the repetition count health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the repetition count health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
]
},
{ name: "REPCNTS_THRESHOLDS",
desc: "Repetition count symbol test thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the repetition count symbol health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the repetition count symbol health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
]
},
{ name: "ADAPTP_HI_THRESHOLDS",
desc: "Adaptive proportion test high thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the adaptive proportion health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the adaptive proportion health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
]
},
{ name: "ADAPTP_LO_THRESHOLDS",
desc: "Adaptive proportion test low thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the adaptive proportion health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is greater than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0x0000"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the adaptive proportion health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is greater than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0x0000"
}
]
},
{ name: "BUCKET_THRESHOLDS",
desc: "Bucket test thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the bucket health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the bucket health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
]
},
{ name: "MARKOV_HI_THRESHOLDS",
desc: "Markov test high thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the Markov health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the Markov health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
]
},
{ name: "MARKOV_LO_THRESHOLDS",
desc: "Markov test low thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the Markov health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is greater than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0x0000"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the Markov health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is greater than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0x0000"
}
]
},
{ name: "EXTHT_HI_THRESHOLDS",
desc: "External health test high thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the external health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the external health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is less than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0xFFFF"
}
]
},
{ name: "EXTHT_LO_THRESHOLDS",
desc: "External health test low thresholds register",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
hwqe: "true",
regwen: "REGWEN",
tags: [// Exclude from writes to these field because they are one-way updates
"excl:CsrNonInitTests:CsrExclWrite"]
fields: [
{ bits: "15:0",
name: "FIPS_THRESH",
desc: '''This is the threshold size for the external health test.
This value is used in FIPS mode.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is greater than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0x0000"
}
{ bits: "31:16",
name: "BYPASS_THRESH",
desc: '''This is the threshold size for the external health test
running in bypass mode. This mode is active after reset for the
first and only test run, or when this mode is programmed by firmware.
This register must be written before the module is enabled.
Writing to this register will only update the register if the
written value is greater than the current value of this register.
A read from this register always reflects the current value.
'''
resval: "0x0000"
}
]
},
{ name: "REPCNT_HI_WATERMARKS",
desc: "Repetition count test high watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrAllTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "High watermark value of the REPCNT test in FIPS mode."
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "High watermark value of the REPCNT test in bypass mode."
}
]
},
{ name: "REPCNTS_HI_WATERMARKS",
desc: "Repetition count symbol test high watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrAllTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "High watermark value of the REPCNTS test in FIPS mode."
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "High watermark value of the REPCNTS test in bypass mode."
}
]
},
{ name: "ADAPTP_HI_WATERMARKS",
desc: "Adaptive proportion test high watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "High watermark value of the adaptive proportion test in FIPS mode."
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "High watermark value of the adaptive proportion test in bypass mode."
}
]
},
{ name: "ADAPTP_LO_WATERMARKS",
desc: "Adaptive proportion test low watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "Low watermark value of the adaptive proportion test in FIPS mode."
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "Low watermark value of the adaptive proportion test in bypass mode."
resval: "0xFFFF"
}
]
},
{ name: "EXTHT_HI_WATERMARKS",
desc: "External health test high watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "High watermark value of the external health test in FIPS mode."
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "High watermark value of the external health test in bypass mode."
}
]
},
{ name: "EXTHT_LO_WATERMARKS",
desc: "External health test low watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "Low watermark value of the external health test in FIPS mode."
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "Low watermark value of the external health test in bypass mode."
resval: "0xFFFF"
}
]
},
{ name: "BUCKET_HI_WATERMARKS",
desc: "Bucket test high watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "High watermark value of the bucket test in FIPS mode."
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "High watermark value of the bucket test in bypass mode."
}
]
},
{ name: "MARKOV_HI_WATERMARKS",
desc: "Markov test high watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "High watermark value of the Markov test in FIPS mode."
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "High watermark value of the Markov test in bypass mode."
}
]
},
{ name: "MARKOV_LO_WATERMARKS",
desc: "Markov test low watermarks register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
tags: [// Internal HW can modify status register
"excl:CsrNonInitTests:CsrExclCheck"]
fields: [
{ bits: "15:0",
name: "FIPS_WATERMARK",
desc: "Low watermark value of the Markov test in FIPS mode."
resval: "0xFFFF"
}
{ bits: "31:16",
name: "BYPASS_WATERMARK",
desc: "Low watermark value of the Markov test in bypass mode."
resval: "0xFFFF"
}
]
},
{ name: "REPCNT_TOTAL_FAILS",
desc: "Repetition count test failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "REPCNT_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''
}
]
},
{ name: "REPCNTS_TOTAL_FAILS",
desc: "Repetition count symbol test failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "REPCNTS_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''
}
]
},
{ name: "ADAPTP_HI_TOTAL_FAILS",
desc: "Adaptive proportion high test failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "ADAPTP_HI_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''
}
]
},
{ name: "ADAPTP_LO_TOTAL_FAILS",
desc: "Adaptive proportion low test failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "ADAPTP_LO_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''
}
]
},
{ name: "BUCKET_TOTAL_FAILS",
desc: "Bucket test failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "BUCKET_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''
}
]
},
{ name: "MARKOV_HI_TOTAL_FAILS",
desc: "Markov high test failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "MARKOV_HI_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''
}
]
},
{ name: "MARKOV_LO_TOTAL_FAILS",
desc: "Markov low test failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "MARKOV_LO_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''
}
]
},
{ name: "EXTHT_HI_TOTAL_FAILS",
desc: "External health test high threshold failure counter register",
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
fields: [
{ bits: "31:0",
name: "EXTHT_HI_TOTAL_FAILS",
desc: '''This register will hold a running count of test failures observed
during normal operation. It will persist until cleared.
'''