From 031175d22a1631c839ff117d577ef2942eed65c3 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Thu, 3 Aug 2023 09:44:02 +0530 Subject: [PATCH] feat(mpi): add MPI peripheral support for esp32p4 --- components/hal/esp32p4/include/hal/mpi_ll.h | 151 ++++++++++++++++++ .../esp32p4/include/soc/Kconfig.soc_caps.in | 14 +- .../soc/esp32p4/include/soc/interrupts.h | 2 +- components/soc/esp32p4/include/soc/soc_caps.h | 8 +- components/soc/esp32p4/mpi_periph.c | 21 +++ 5 files changed, 192 insertions(+), 4 deletions(-) create mode 100644 components/hal/esp32p4/include/hal/mpi_ll.h create mode 100644 components/soc/esp32p4/mpi_periph.c diff --git a/components/hal/esp32p4/include/hal/mpi_ll.h b/components/hal/esp32p4/include/hal/mpi_ll.h new file mode 100644 index 000000000000..f169c7d7a730 --- /dev/null +++ b/components/hal/esp32p4/include/hal/mpi_ll.h @@ -0,0 +1,151 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "hal/assert.h" +#include "soc/rsa_reg.h" +#include "soc/mpi_periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline size_t mpi_ll_calculate_hardware_words(size_t words) +{ + return words; +} + +// No need to initialize Power Control Registers in case of ESP32-P4 +static inline void mpi_ll_clear_power_control_bit(void) +{ +} + +static inline void mpi_ll_set_power_control_bit(void) +{ +} + +static inline void mpi_ll_enable_interrupt(void) +{ + REG_WRITE(RSA_INT_ENA_REG, 1); +} + +static inline void mpi_ll_disable_interrupt(void) +{ + REG_WRITE(RSA_INT_ENA_REG, 0); +} + +static inline void mpi_ll_clear_interrupt(void) +{ + REG_WRITE(RSA_INT_CLR_REG, 1); +} + +static inline bool mpi_ll_check_memory_init_complete(void) +{ + return REG_READ(RSA_QUERY_CLEAN_REG) == 0; +} + +static inline void mpi_ll_start_op(mpi_op_t op) +{ + REG_WRITE(MPI_LL_OPERATIONS[op], 1); +} + +static inline bool mpi_ll_get_int_status(void) +{ + return REG_READ(RSA_QUERY_IDLE_REG) == 0; +} + +/* Copy MPI bignum (p) to hardware memory block at 'mem_base' of mpi_param_t 'param'. + + If num_words is higher than the number of words (n) in the bignum then + these additional words will be zeroed in the memory buffer. +*/ +static inline void mpi_ll_write_to_mem_block(mpi_param_t param, size_t offset, const uint32_t* p, size_t n, size_t num_words) +{ + uint32_t mem_base = MPI_LL_BLOCK_BASES[param] + offset; + uint32_t* pbase = (uint32_t*) mem_base; + uint32_t copy_words = MIN(num_words, n); + + /* Copy MPI data to memory block registers */ + for (int i = 0; i < copy_words; i++) { + pbase[i] = p[i]; + } + + /* Zero any remaining memory block data */ + for (int i = copy_words; i < num_words; i++) { + pbase[i] = 0; + } +} + +static inline void mpi_ll_write_m_prime(uint32_t Mprime) +{ + REG_WRITE(RSA_M_PRIME_REG, Mprime); +} + +static inline void mpi_ll_write_rinv(uint32_t rinv) +{ + REG_WRITE(MPI_LL_BLOCK_BASES[MPI_PARAM_Z], rinv); +} + +static inline void mpi_ll_write_at_offset(mpi_param_t param, int offset, uint32_t value) +{ + uint32_t mem_base = MPI_LL_BLOCK_BASES[param] + offset; + REG_WRITE(mem_base, value); +} + +/* Read MPI bignum (p) back from hardware memory block. + + Reads z_words words from block. +*/ +static inline void mpi_ll_read_from_mem_block(uint32_t* p, size_t n, size_t num_words) +{ + uint32_t mem_base = MPI_LL_BLOCK_BASES[MPI_PARAM_Z]; + /* Copy data from memory block registers */ + const size_t REG_WIDTH = sizeof(uint32_t); + for (size_t i = 0; i < num_words; i++) { + p[i] = REG_READ(mem_base + (i * REG_WIDTH)); + } + /* Zero any remaining limbs in the bignum, if the buffer is bigger + than num_words */ + for (size_t i = num_words; i < n; i++) { + p[i] = 0; + } +} + +static inline void mpi_ll_set_mode(size_t length) +{ + REG_WRITE(RSA_MODE_REG, length); +} + +static inline void mpi_ll_disable_constant_time(void) +{ + REG_WRITE(RSA_CONSTANT_TIME_REG, 0); +} + +static inline void mpi_ll_enable_constant_time(void) +{ + REG_WRITE(RSA_CONSTANT_TIME_REG, 1); +} + +static inline void mpi_ll_disable_search(void) +{ + REG_WRITE(RSA_SEARCH_ENABLE_REG, 0); +} + +static inline void mpi_ll_enable_search(void) +{ + REG_WRITE(RSA_SEARCH_ENABLE_REG, 1); +} + +static inline void mpi_ll_set_search_position(size_t pos) +{ + REG_WRITE(RSA_SEARCH_POS_REG, pos); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 2e2b4bb67fa5..fd581ae2fa5c 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -43,6 +43,10 @@ config SOC_SYSTIMER_SUPPORTED bool default y +config SOC_MPI_SUPPORTED + bool + default y + config SOC_ECC_SUPPORTED bool default y @@ -551,9 +555,17 @@ config SOC_PARLIO_TX_RX_SHARE_INTERRUPT bool default y +config SOC_MPI_MEM_BLOCKS_NUM + int + default 4 + +config SOC_MPI_OPERATIONS_NUM + int + default 3 + config SOC_RSA_MAX_BIT_LEN int - default 3072 + default 4096 config SOC_SHA_DMA_MAX_BUFFER_SIZE int diff --git a/components/soc/esp32p4/include/soc/interrupts.h b/components/soc/esp32p4/include/soc/interrupts.h index 8bf26b96b137..fdce7edc2170 100644 --- a/components/soc/esp32p4/include/soc/interrupts.h +++ b/components/soc/esp32p4/include/soc/interrupts.h @@ -84,7 +84,7 @@ typedef enum { ETS_AXI_PDMA_OUT_CH1_INTR_SOURCE, ETS_AXI_PDMA_OUT_CH2_INTR_SOURCE, - ETS_RSA_INTA_SOURCE, + ETS_RSA_INTR_SOURCE, ETS_AES_INTR_SOURCE, ETS_SHA_INTR_SOURCE, ETS_ECC_INTR_SOURCE, diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index bb74d630a29a..92e50a138864 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -55,7 +55,7 @@ // #define SOC_I2C_SUPPORTED 1 //TODO: IDF-6507, TODO: IDF-7491 #define SOC_SYSTIMER_SUPPORTED 1 // #define SOC_AES_SUPPORTED 1 //TODO: IDF-6519 -// #define SOC_MPI_SUPPORTED 1 +#define SOC_MPI_SUPPORTED 1 // #define SOC_SHA_SUPPORTED 1 //TODO: IDF-7541 // #define SOC_HMAC_SUPPORTED 1 //TODO: IDF-7543 // #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: IDF-6518 @@ -297,8 +297,12 @@ #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */ +/*--------------------------- MPI CAPS ---------------------------------------*/ +#define SOC_MPI_MEM_BLOCKS_NUM (4) +#define SOC_MPI_OPERATIONS_NUM (3) + /*--------------------------- RSA CAPS ---------------------------------------*/ -#define SOC_RSA_MAX_BIT_LEN (3072) +#define SOC_RSA_MAX_BIT_LEN (4096) // TODO: IDF-5353 (Copy from esp32c3, need check) /*--------------------------- SHA CAPS ---------------------------------------*/ diff --git a/components/soc/esp32p4/mpi_periph.c b/components/soc/esp32p4/mpi_periph.c new file mode 100644 index 000000000000..1fd50f531814 --- /dev/null +++ b/components/soc/esp32p4/mpi_periph.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/rsa_reg.h" +#include "soc/mpi_periph.h" + +const uint32_t MPI_LL_BLOCK_BASES[4] = { + RSA_X_MEM, + RSA_Y_MEM, + RSA_Z_MEM, + RSA_M_MEM, +}; + +const uint32_t MPI_LL_OPERATIONS[3] = { + RSA_SET_START_MULT_REG, + RSA_SET_START_MODMULT_REG, + RSA_SET_START_MODEXP_REG, +};