diff --git a/components/driver/Kconfig b/components/driver/Kconfig index 2f8839940ab..7c68ec740fe 100644 --- a/components/driver/Kconfig +++ b/components/driver/Kconfig @@ -368,39 +368,7 @@ menu "Driver Configurations" Note that, this option only controls the RMT driver log, won't affect other drivers. endmenu # RMT Configuration - menu "MCPWM Configuration" - depends on SOC_MCPWM_SUPPORTED - config MCPWM_ISR_IRAM_SAFE - bool "Place MCPWM ISR function into IRAM" - default n - help - This will ensure the MCPWM interrupt handle is IRAM-Safe, allow to avoid flash - cache misses, and also be able to run whilst the cache is disabled. - (e.g. SPI Flash write) - - config MCPWM_CTRL_FUNC_IN_IRAM - bool "Place MCPWM control functions into IRAM" - default n - help - Place MCPWM control functions (like set_compare_value) into IRAM, - so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. - Enabling this option can improve driver performance as well. - - config MCPWM_SUPPRESS_DEPRECATE_WARN - bool "Suppress leagcy driver deprecated warning" - default n - help - Wether to suppress the deprecation warnings when using legacy MCPWM driver (driver/mcpwm.h). - If you want to continue using the legacy driver, and don't want to see related deprecation warnings, - you can enable this option. - - config MCPWM_ENABLE_DEBUG_LOG - bool "Enable debug log" - default n - help - Wether to enable the debug log message for MCPWM driver. - Note that, this option only controls the MCPWM driver log, won't affect other drivers. - endmenu # MCPWM Configuration + orsource "./mcpwm/Kconfig.mcpwm" menu "I2S Configuration" depends on SOC_I2S_SUPPORTED diff --git a/components/driver/mcpwm/Kconfig.mcpwm b/components/driver/mcpwm/Kconfig.mcpwm new file mode 100644 index 00000000000..b1a7fd8c810 --- /dev/null +++ b/components/driver/mcpwm/Kconfig.mcpwm @@ -0,0 +1,33 @@ +menu "MCPWM Configuration" + depends on SOC_MCPWM_SUPPORTED + config MCPWM_ISR_IRAM_SAFE + bool "Place MCPWM ISR function into IRAM" + default n + help + This will ensure the MCPWM interrupt handle is IRAM-Safe, allow to avoid flash + cache misses, and also be able to run whilst the cache is disabled. + (e.g. SPI Flash write) + + config MCPWM_CTRL_FUNC_IN_IRAM + bool "Place MCPWM control functions into IRAM" + default n + help + Place MCPWM control functions (like set_compare_value) into IRAM, + so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. + Enabling this option can improve driver performance as well. + + config MCPWM_SUPPRESS_DEPRECATE_WARN + bool "Suppress leagcy driver deprecated warning" + default n + help + Wether to suppress the deprecation warnings when using legacy MCPWM driver (driver/mcpwm.h). + If you want to continue using the legacy driver, and don't want to see related deprecation warnings, + you can enable this option. + + config MCPWM_ENABLE_DEBUG_LOG + bool "Enable debug log" + default n + help + Wether to enable the debug log message for MCPWM driver. + Note that, this option only controls the MCPWM driver log, won't affect other drivers. +endmenu # MCPWM Configuration diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c index a0db1abde78..d07789141a7 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_cap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,9 +111,9 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]") printf("simulate GPIO capture signal\r\n"); gpio_set_level(cap_gpio, 1); - vTaskDelay(pdMS_TO_TICKS(10)); + esp_rom_delay_us(10 * 1000); gpio_set_level(cap_gpio, 0); - vTaskDelay(pdMS_TO_TICKS(10)); + esp_rom_delay_us(10 * 1000); printf("capture value: Pos=%"PRIu32", Neg=%"PRIu32"\r\n", cap_value[0], cap_value[1]); uint32_t clk_src_res; TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res)); @@ -176,10 +176,9 @@ TEST_CASE("mcpwm_capture_software_catch", "[mcpwm]") printf("trigger software catch\r\n"); TEST_ESP_OK(mcpwm_capture_channel_trigger_soft_catch(cap_channel)); - vTaskDelay(pdMS_TO_TICKS(10)); + esp_rom_delay_us(10 * 1000); TEST_ESP_OK(mcpwm_capture_channel_trigger_soft_catch(cap_channel)); - vTaskDelay(pdMS_TO_TICKS(10)); - + esp_rom_delay_us(10 * 1000); // check user data TEST_ASSERT_EQUAL(2, test_callback_data.cap_data_index); uint32_t delta = test_callback_data.cap_data[1] - test_callback_data.cap_data[0]; diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c index 3b133f27e35..8ebd2f70278 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_cmpr.c @@ -100,7 +100,7 @@ TEST_CASE("mcpwm_comparator_event_callback", "[mcpwm]") TEST_ESP_OK(mcpwm_timer_enable(timer)); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); - vTaskDelay(pdMS_TO_TICKS(1000)); + esp_rom_delay_us(1000 * 1000); TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY)); printf("compare_counts=%"PRIu32"\r\n", compare_counts); // the timer period is 10ms, the expected compare_counts = 1s/10ms = 100 diff --git a/components/driver/test_apps/mcpwm/main/test_mcpwm_timer.c b/components/driver/test_apps/mcpwm/main/test_mcpwm_timer.c index 94215bf85a7..9ea564f07b5 100644 --- a/components/driver/test_apps/mcpwm/main/test_mcpwm_timer.c +++ b/components/driver/test_apps/mcpwm/main/test_mcpwm_timer.c @@ -169,7 +169,7 @@ TEST_CASE("mcpwm_timer_event_callbacks", "[mcpwm]") TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP)); printf("wait for full and empty events\r\n"); - bits = xEventGroupWaitBits(event_group, TEST_MCPWM_TIMER_EVENT_BIT_FULL | TEST_MCPWM_TIMER_EVENT_BIT_EMPTY, pdTRUE, pdTRUE, pdMS_TO_TICKS(1050)); + bits = xEventGroupWaitBits(event_group, TEST_MCPWM_TIMER_EVENT_BIT_FULL | TEST_MCPWM_TIMER_EVENT_BIT_EMPTY, pdTRUE, pdTRUE, pdMS_TO_TICKS(1300)); TEST_ASSERT_EQUAL(TEST_MCPWM_TIMER_EVENT_BIT_FULL | TEST_MCPWM_TIMER_EVENT_BIT_EMPTY, bits); printf("stop timer and wait for event\r\n"); diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index 3edb60f12f4..cb847f3a972 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -77,9 +77,9 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) case PERIPH_CAM_MODULE: return HP_SYS_CLKRST_REG_CAM_CLK_EN; case PERIPH_MCPWM0_MODULE: - return HP_SYS_CLKRST_REG_MCPWM0_CLK_EN; + return HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN; case PERIPH_MCPWM1_MODULE: - return HP_SYS_CLKRST_REG_MCPWM1_CLK_EN; + return HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN; case PERIPH_TIMG0_MODULE: return HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN; case PERIPH_TIMG1_MODULE: @@ -264,6 +264,7 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) return HP_SYS_CLKRST_PERI_CLK_CTRL119_REG; case PERIPH_MCPWM0_MODULE: case PERIPH_MCPWM1_MODULE: + return HP_SYS_CLKRST_SOC_CLK_CTRL2_REG; case PERIPH_TIMG0_MODULE: return HP_SYS_CLKRST_PERI_CLK_CTRL20_REG; case PERIPH_TIMG1_MODULE: diff --git a/components/hal/esp32p4/include/hal/mcpwm_ll.h b/components/hal/esp32p4/include/hal/mcpwm_ll.h new file mode 100644 index 00000000000..800e0f47475 --- /dev/null +++ b/components/hal/esp32p4/include/hal/mcpwm_ll.h @@ -0,0 +1,1680 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in hal/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-P4 MCPWM register operations + +#pragma once + +#include +#include "soc/soc_caps.h" +#include "soc/mcpwm_struct.h" +#include "soc/clk_tree_defs.h" +#include "soc/hp_sys_clkrst_struct.h" +#include "hal/mcpwm_types.h" +#include "hal/misc.h" +#include "hal/assert.h" +#include +#ifdef __cplusplus +extern "C" { +#endif + +// Get MCPWM group register base address +#define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : &MCPWM1) + +// MCPWM interrupt event mask +#define MCPWM_LL_EVENT_TIMER_STOP(timer) (1 << (timer)) +#define MCPWM_LL_EVENT_TIMER_EMPTY(timer) (1 << ((timer) + 3)) +#define MCPWM_LL_EVENT_TIMER_FULL(timer) (1 << ((timer) + 6)) +#define MCPWM_LL_EVENT_TIMER_MASK(timer) (MCPWM_LL_EVENT_TIMER_STOP(timer) | MCPWM_LL_EVENT_TIMER_EMPTY(timer) | MCPWM_LL_EVENT_TIMER_FULL(timer)) +#define MCPWM_LL_EVENT_FAULT_ENTER(fault) (1 << ((fault) + 9)) +#define MCPWM_LL_EVENT_FAULT_EXIT(fault) (1 << ((fault) + 12)) +#define MCPWM_LL_EVENT_FAULT_MASK(fault) (MCPWM_LL_EVENT_FAULT_ENTER(fault) | MCPWM_LL_EVENT_FAULT_EXIT(fault)) +#define MCPWM_LL_EVENT_CMP_EQUAL(oper, cmp) (1 << ((oper) + (cmp) * 3 + 15)) +#define MCPWM_LL_EVENT_OPER_BRAKE_CBC(oper) (1 << ((oper) + 21)) +#define MCPWM_LL_EVENT_OPER_BRAKE_OST(oper) (1 << ((oper) + 24)) +#define MCPWM_LL_EVENT_OPER_MASK(oper) (MCPWM_LL_EVENT_OPER_BRAKE_CBC(oper) | MCPWM_LL_EVENT_OPER_BRAKE_OST(oper)) +#define MCPWM_LL_EVENT_CAPTURE(cap) (1 << ((cap) + 27)) + +// Maximum values due to limited register bit width +#define MCPWM_LL_MAX_CARRIER_ONESHOT 16 +#define MCPWM_LL_MAX_CAPTURE_PRESCALE 256 +#define MCPWM_LL_MAX_DEAD_DELAY 65536 +#define MCPWM_LL_MAX_COUNT_VALUE 65536 + +// translate the HAL types into register values +#define MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) ((uint8_t[]) {0, 1}[(event)]) +#define MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) ((uint8_t[]) {0, 1, 2, 3}[(action)]) +#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)]) + +/** + * @brief The dead time module's clock source + */ +typedef enum { + MCPWM_LL_DEADTIME_CLK_SRC_GROUP, + MCPWM_LL_DEADTIME_CLK_SRC_TIMER, +} mcpwm_ll_deadtime_clock_src_t; + +////////////////////////////////////////MCPWM Group Specific//////////////////////////////////////////////////////////// + +/** + * @brief Set the clock source for MCPWM + * + * @param mcpwm Peripheral instance address + * @param clk_src Clock source for the MCPWM peripheral + */ +static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_module_clk_t clk_src) +{ + uint8_t clk_id = 0; + switch (clk_src) { + case SOC_MOD_CLK_XTAL: + clk_id = 0; + break; + case SOC_MOD_CLK_RC_FAST: + clk_id = 1; + break; + case SOC_MOD_CLK_PLL_F160M: + clk_id = 2; + break; + default: + HAL_ASSERT(false); + break; + } + if (mcpwm == &MCPWM0) { + HP_SYS_CLKRST.peri_clk_ctrl20.reg_mcpwm0_clk_src_sel = clk_id; + } else if (mcpwm == &MCPWM1) { + HP_SYS_CLKRST.peri_clk_ctrl20.reg_mcpwm1_clk_src_sel = clk_id; + } +} + +/** + * @brief Enable MCPWM module clock + * + * @param mcpwm Peripheral instance address + * @param en true to enable, false to disable + */ +static inline void mcpwm_ll_group_enable_clock(mcpwm_dev_t *mcpwm, bool en) +{ + if (mcpwm == &MCPWM0) { + HP_SYS_CLKRST.peri_clk_ctrl20.reg_mcpwm0_clk_en = en; + } else if (mcpwm == &MCPWM1) { + HP_SYS_CLKRST.peri_clk_ctrl20.reg_mcpwm1_clk_en = en; + } +} + +/** + * @brief Set the MCPWM group clock prescale + * + * @param mcpwm Peripheral instance address + * @param pre_scale Prescale value + */ +static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int pre_scale) +{ + // group clock: PWM_clk = source_clock / (prescale + 1) + if (mcpwm == &MCPWM0) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm0_clk_div_num, pre_scale - 1); + } else if (mcpwm == &MCPWM1) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm1_clk_div_num, pre_scale - 1); + } +} + +/** + * @brief Enable update MCPWM active registers from shadow registers + * + * @param mcpwm Peripheral instance address + */ +static inline void mcpwm_ll_group_enable_shadow_mode(mcpwm_dev_t *mcpwm) +{ + mcpwm->update_cfg.global_up_en = 1; + mcpwm->update_cfg.op0_up_en = 1; + mcpwm->update_cfg.op1_up_en = 1; + mcpwm->update_cfg.op2_up_en = 1; +} + +/** + * @brief Flush shadow registers to active registers + * + * @param mcpwm Peripheral instance address + */ +static inline void mcpwm_ll_group_flush_shadow(mcpwm_dev_t *mcpwm) +{ + // a toggle can trigger a forced update of all active registers in MCPWM, i.e. shadow->active + mcpwm->update_cfg.global_force_up = 1; + mcpwm->update_cfg.global_force_up = 0; +} + +//////////////////////////////////////////Interrupt Specific//////////////////////////////////////////////////////////// + +/** + * @brief Get interrupt status register address + * + * @param mcpwm Peripheral instance address + * @return Register address + */ +static inline volatile void *mcpwm_ll_intr_get_status_reg(mcpwm_dev_t *mcpwm) +{ + return &mcpwm->int_st; +} + +/** + * @brief Enable MCPWM interrupt for specific event mask + * + * @param mcpwm Peripheral instance address + * @param mask Event mask + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_intr_enable(mcpwm_dev_t *mcpwm, uint32_t mask, bool enable) +{ + if (enable) { + mcpwm->int_ena.val |= mask; + } else { + mcpwm->int_ena.val &= ~mask; + } +} + +/** + * @brief Get MCPWM interrupt status + * + * @param mcpwm Peripheral instance address + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t mcpwm_ll_intr_get_status(mcpwm_dev_t *mcpwm) +{ + return mcpwm->int_st.val; +} + +/** + * @brief Clear MCPWM interrupt status by mask + * + * @param mcpwm Peripheral instance address + * @param mask Interupt status mask + */ +__attribute__((always_inline)) +static inline void mcpwm_ll_intr_clear_status(mcpwm_dev_t *mcpwm, uint32_t mask) +{ + mcpwm->int_clr.val = mask; +} + +////////////////////////////////////////MCPWM Timer Specific//////////////////////////////////////////////////////////// + +/** + * @brief Set MCPWM timer prescale + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param prescale Prescale value + */ +static inline void mcpwm_ll_timer_set_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id, uint32_t prescale) +{ + HAL_ASSERT(prescale <= 256 && prescale > 0); + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_prescale, prescale - 1); +} + +/** + * @brief Set peak value for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param peak Peak value + * @param symmetric True to set symmetric peak value, False to set asymmetric peak value + */ +static inline void mcpwm_ll_timer_set_peak(mcpwm_dev_t *mcpwm, int timer_id, uint32_t peak, bool symmetric) +{ + if (!symmetric) { // in asymmetric mode, period = [0,peak-1] + HAL_ASSERT(peak > 0 && peak <= MCPWM_LL_MAX_COUNT_VALUE); + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak - 1); + } else { // in symmetric mode, period = [0,peak-1] + [peak,1] + HAL_ASSERT(peak < MCPWM_LL_MAX_COUNT_VALUE); + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period, peak); + } +} + +/** + * @brief Update MCPWM period immediately + * @note When period value is updated in the shadow register, it will be flushed to active register immediately. + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_update_period_at_once(mcpwm_dev_t *mcpwm, int timer_id) +{ + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod = 0; +} + +/** + * @brief Enable to update MCPWM period upon TEZ event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_timer_enable_update_period_on_tez(mcpwm_dev_t *mcpwm, int timer_id, bool enable) +{ + if (enable) { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x01; + } else { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x01; + } +} + +/** + * @brief Enable to update MCPWM period upon sync event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_timer_enable_update_period_on_sync(mcpwm_dev_t *mcpwm, int timer_id, bool enable) +{ + if (enable) { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod |= 0x02; + } else { + mcpwm->timer[timer_id].timer_cfg0.timer_period_upmethod &= ~0x02; + } +} + +/** + * @brief Set MCPWM timer count mode + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param mode Timer count mode + */ +static inline void mcpwm_ll_timer_set_count_mode(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_count_mode_t mode) +{ + switch (mode) { + case MCPWM_TIMER_COUNT_MODE_PAUSE: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 0; + break; + case MCPWM_TIMER_COUNT_MODE_UP: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 1; + break; + case MCPWM_TIMER_COUNT_MODE_DOWN: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 2; + break; + case MCPWM_TIMER_COUNT_MODE_UP_DOWN: + mcpwm->timer[timer_id].timer_cfg1.timer_mod = 3; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Execute MCPWM timer start/stop command + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param cmd Timer start/stop command + */ +static inline void mcpwm_ll_timer_set_start_stop_command(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_start_stop_cmd_t cmd) +{ + switch (cmd) { + case MCPWM_TIMER_STOP_EMPTY: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 0; + break; + case MCPWM_TIMER_STOP_FULL: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 1; + break; + case MCPWM_TIMER_START_NO_STOP: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 2; + break; + case MCPWM_TIMER_START_STOP_EMPTY: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 3; + break; + case MCPWM_TIMER_START_STOP_FULL: + mcpwm->timer[timer_id].timer_cfg1.timer_start = 4; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Get timer count value + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @return Timer count value + */ +__attribute__((always_inline)) +static inline uint32_t mcpwm_ll_timer_get_count_value(mcpwm_dev_t *mcpwm, int timer_id) +{ + // status.value saves the "next count value", so need an extra round up here to get the current count value according to count mode + // timer is paused + if (mcpwm->timer[timer_id].timer_cfg1.timer_mod == 0) { + return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value); + } + if (mcpwm->timer[timer_id].timer_status.timer_direction) { // down direction + return (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value) + 1) % + (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1); + } + // up direction + return (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_status, timer_value) + + HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period)) % + (HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + 1); +} + +/** + * @brief Get timer count direction + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @return Timer count direction + */ +__attribute__((always_inline)) +static inline mcpwm_timer_direction_t mcpwm_ll_timer_get_count_direction(mcpwm_dev_t *mcpwm, int timer_id) +{ + return mcpwm->timer[timer_id].timer_status.timer_direction ? MCPWM_TIMER_DIRECTION_DOWN : MCPWM_TIMER_DIRECTION_UP; +} + +/** + * @brief Enable sync input for timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_timer_enable_sync_input(mcpwm_dev_t *mcpwm, int timer_id, bool enable) +{ + mcpwm->timer[timer_id].timer_sync.timer_synci_en = enable; +} + +/** + * @brief Use the input sync signal as the output sync signal (i.e. propagate the input sync signal) + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_propagate_input_sync(mcpwm_dev_t *mcpwm, int timer_id) +{ + // sync_out is selected to sync_in + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 0; +} + +/** + * @brief Set the sync output signal to one of the timer event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param event Timer event + */ +static inline void mcpwm_ll_timer_sync_out_on_timer_event(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_event_t event) +{ + switch (event) { + case MCPWM_TIMER_EVENT_EMPTY: + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 1; + break; + case MCPWM_TIMER_EVENT_FULL: + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 2; + break; + default: + HAL_ASSERT(false); + break; + } +} + +/** + * @brief Disable sync output for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_disable_sync_out(mcpwm_dev_t *mcpwm, int timer_id) +{ + // sync_out will always be zero + mcpwm->timer[timer_id].timer_sync.timer_synco_sel = 3; +} + +/** + * @brief Trigger MCPWM timer software sync event + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_trigger_soft_sync(mcpwm_dev_t *mcpwm, int timer_id) +{ + mcpwm->timer[timer_id].timer_sync.timer_sync_sw = ~mcpwm->timer[timer_id].timer_sync.timer_sync_sw; +} + +/** + * @brief Set sync count value for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param phase_value Sync phase value + */ +static inline void mcpwm_ll_timer_set_sync_phase_value(mcpwm_dev_t *mcpwm, int timer_id, uint32_t phase_value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->timer[timer_id].timer_sync, timer_phase, phase_value); +} + +/** + * @brief Set sync phase direction for MCPWM timer + * + * @param mcpwm Peripheral instance address + * @param timer_id Timer ID, index from 0 to 2 + * @param direction Sync phase direction + */ +static inline void mcpwm_ll_timer_set_sync_phase_direction(mcpwm_dev_t *mcpwm, int timer_id, mcpwm_timer_direction_t direction) +{ + mcpwm->timer[timer_id].timer_sync.timer_phase_direction = direction; +} + +/** + * @brief Select which GPIO sync input to use + * + * @param mcpwm Peripheral instance address + * @param timer Timer ID, index from 0 to 2 + * @param gpio_sync_id GPIO sync ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_set_gpio_sync_input(mcpwm_dev_t *mcpwm, int timer, int gpio_sync_id) +{ + mcpwm->timer_synci_cfg.val &= ~(0x07 << (timer * 3)); + mcpwm->timer_synci_cfg.val |= (gpio_sync_id + 4) << (timer * 3); +} + +/** + * @brief Select which timer sync input to use + * + * @param mcpwm Peripheral instance address + * @param timer Timer ID, index from 0 to 2 + * @param timer_sync_id Timer sync ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_set_timer_sync_input(mcpwm_dev_t *mcpwm, int timer, int timer_sync_id) +{ + mcpwm->timer_synci_cfg.val &= ~(0x07 << (timer * 3)); + mcpwm->timer_synci_cfg.val |= (timer_sync_id + 1) << (timer * 3); +} + +/** + * @brief Clear timer sync input selection + * + * @param mcpwm Peripheral instance address + * @param timer Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_timer_clear_sync_input(mcpwm_dev_t *mcpwm, int timer) +{ + // no sync input is selected, but software sync can still work + mcpwm->timer_synci_cfg.val &= ~(0x07 << (timer * 3)); +} + +/** + * @brief Invert the GPIO sync input signal + * + * @param mcpwm Peripheral instance address + * @param sync_id GPIO sync ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_invert_gpio_sync_input(mcpwm_dev_t *mcpwm, int sync_id, bool invert) +{ + if (invert) { + mcpwm->timer_synci_cfg.val |= 1 << (sync_id + 9); + } else { + mcpwm->timer_synci_cfg.val &= ~(1 << (sync_id + 9)); + } +} + +////////////////////////////////////////MCPWM Operator Specific///////////////////////////////////////////////////////// + +/** + * @brief Flush operator shadow registers to active registers + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_operator_flush_shadow(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->update_cfg.val ^= (1 << (2 * operator_id + 3)); +} + +/** + * @brief Connect operator and timer by ID + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param timer_id Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_operator_connect_timer(mcpwm_dev_t *mcpwm, int operator_id, int timer_id) +{ + mcpwm->operator_timersel.val &= ~(0x03 << (2 * operator_id)); + mcpwm->operator_timersel.val |= (timer_id << (2 * operator_id)); +} + +/** + * @brief Update the compare value immediately + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + */ +static inline void mcpwm_ll_operator_update_compare_at_once(mcpwm_dev_t *mcpwm, int operator_id, int compare_id) +{ + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~(0x0F << (4 * compare_id)); +} + +/** + * @brief Enable to update the compare value upon TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_compare_on_tez(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 0) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 0) << (4 * compare_id)); + } +} + +/** + * @brief Enable to update the compare value upon TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_compare_on_tep(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 1) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 1) << (4 * compare_id)); + } +} + +/** + * @brief Enable to update the compare value upon sync event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_compare_on_sync(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 2) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 2) << (4 * compare_id)); + } +} + +/** + * @brief Stop updating the compare value + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param stop_or_not True to stop, False to not stop + */ +static inline void mcpwm_ll_operator_stop_update_compare(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, bool stop_or_not) +{ + if (stop_or_not) { + mcpwm->operators[operator_id].gen_stmp_cfg.val |= (1 << 3) << (4 * compare_id); + } else { + mcpwm->operators[operator_id].gen_stmp_cfg.val &= ~((1 << 3) << (4 * compare_id)); + } +} + +/** + * @brief Set compare value for comparator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param compare_id Compare ID, index from 0 to 1 + * @param compare_value Compare value + */ +__attribute__((always_inline)) +static inline void mcpwm_ll_operator_set_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id, uint32_t compare_value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operators[operator_id].timestamp[compare_id], cmpr, compare_value); +} + +/** + * @brief Set equal value for operator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param equal_id Equal ID, index from 0 to 1 + * @param equal_value Equal value + */ +__attribute__((always_inline)) +static inline void mcpwm_ll_operator_set_equal_value(mcpwm_dev_t *mcpwm, int operator_id, int event_cmpr_id, uint32_t equal_value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operators_timestamp[operator_id].timestamp[event_cmpr_id], op_tstmp_e, equal_value); +} + +/** + * @brief Update operator actions immediately + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_operator_update_action_at_once(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod = 0; +} + +/** + * @brief Enable update actions on TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_action_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 0; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 0); + } +} + +/** + * @brief Enable update actions on TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_action_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 1; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 1); + } +} + +/** + * @brief Enable update actions on sync event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_operator_enable_update_action_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 2; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 2); + } +} + +/** + * @brief Stop updating actions + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param stop_or_not True to stop, False to not stop + */ +static inline void mcpwm_ll_operator_stop_update_action(mcpwm_dev_t *mcpwm, int operator_id, bool stop_or_not) +{ + if (stop_or_not) { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod |= 1 << 3; + } else { + mcpwm->operators[operator_id].gen_cfg0.gen_cfg_upmethod &= ~(1 << 3); + } +} + +/** + * @brief Set trigger from GPIO (reuse the fault GPIO) + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param trig_id Trigger ID, index from 0 to 1 + * @param fault_gpio_id Fault GPIO ID, index from 0 to 3 + */ +static inline void mcpwm_ll_operator_set_trigger_from_gpio_fault(mcpwm_dev_t *mcpwm, int operator_id, int trig_id, int fault_gpio_id) +{ + mcpwm->operators[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operators[operator_id].gen_cfg0.val |= (fault_gpio_id << (4 + 3 * trig_id)); +} + +/** + * @brief Set trigger from sync event (when the timer/gpio/soft taken the sync signal) + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param trig_id Trigger ID, index from 0 to 1 + */ +static inline void mcpwm_ll_operator_set_trigger_from_sync(mcpwm_dev_t *mcpwm, int operator_id, int trig_id) +{ + // the timer here is not selectable, must be the one connected with the operator + mcpwm->operators[operator_id].gen_cfg0.val &= ~(0x07 << (4 + 3 * trig_id)); + mcpwm->operators[operator_id].gen_cfg0.val |= (3 << (4 + 3 * trig_id)); +} + +////////////////////////////////////////MCPWM Generator Specific//////////////////////////////////////////////////////// + +/** + * @brief Reset actions for the generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_generator_reset_actions(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + mcpwm->operators[operator_id].generator[generator_id].val = 0; +} + +/** + * @brief Set generator action on timer event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param event Timer event + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_timer_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, mcpwm_timer_event_t event, mcpwm_generator_action_t action) +{ + // empty: 0, full: 1 + if (direction == MCPWM_TIMER_DIRECTION_UP) { // utez, utep + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtez, dtep + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2 + 12)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (MCPWM_LL_TIMER_EVENT_TO_REG_VAL(event) * 2 + 12); + } +} + +/** + * @brief Set generator action on compare event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param comp_id Compare ID, index from 0 to 1 + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_compare_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, int cmp_id, int action) +{ + if (direction == MCPWM_TIMER_DIRECTION_UP) { // utea, uteb + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 4)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (cmp_id * 2 + 4); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dtea, dteb + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (cmp_id * 2 + 16)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (cmp_id * 2 + 16); + } +} + +/** + * @brief Set generator action on trigger event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param trig_id Trigger ID, index from 0 to 1 + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_trigger_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, int trig_id, int action) +{ + if (direction == MCPWM_TIMER_DIRECTION_UP) { // ut0, ut1 + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 8)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (trig_id * 2 + 8); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { // dt0, dt1 + mcpwm->operators[operator_id].generator[generator_id].val &= ~(0x03 << (trig_id * 2 + 20)); + mcpwm->operators[operator_id].generator[generator_id].val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (trig_id * 2 + 20); + } +} + +/** + * @brief Set generator action on brake event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param direction Timer direction + * @param brake_mode Brake mode + * @param action Action to set + */ +static inline void mcpwm_ll_generator_set_action_on_brake_event(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, + mcpwm_timer_direction_t direction, mcpwm_operator_brake_mode_t brake_mode, int action) +{ + // the following bit operation is highly depend on the register bit layout. + // the priority comes: generator ID > brake mode > direction + if (direction == MCPWM_TIMER_DIRECTION_UP) { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode) + 2)); + mcpwm->operators[operator_id].fh_cfg0.val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode) + 2); + } else if (direction == MCPWM_TIMER_DIRECTION_DOWN) { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(0x03 << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode))); + mcpwm->operators[operator_id].fh_cfg0.val |= MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) << (8 + 8 * generator_id + 4 * MCPWM_LL_BRAKE_MODE_TO_REG_VAL(brake_mode)); + } +} + +/** + * @brief Trigger non-continue forced action for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_gen_trigger_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_nciforce = ~mcpwm->operators[operator_id].gen_force.gen_a_nciforce; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_nciforce = ~mcpwm->operators[operator_id].gen_force.gen_b_nciforce; + } +} + +/** + * @brief Disable continue forced action for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_gen_disable_continue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + mcpwm->operators[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_cntuforce_mode = 0; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_cntuforce_mode = 0; + } +} + +/** + * @brief Disable non-continue forced action for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_gen_disable_noncontinue_force_action(mcpwm_dev_t *mcpwm, int operator_id, int generator_id) +{ + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_nciforce_mode = 0; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_nciforce_mode = 0; + } +} + +/** + * @brief Set continue force level for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param level Force level to set + */ +static inline void mcpwm_ll_gen_set_continue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) +{ + mcpwm->operators[operator_id].gen_force.gen_cntuforce_upmethod = 0; // update force method immediately + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_cntuforce_mode = level + 1; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_cntuforce_mode = level + 1; + } +} + +/** + * @brief Set non-continue force level for generator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator_id Generator ID, index from 0 to 1 + * @param level Force level to set + */ +static inline void mcpwm_ll_gen_set_noncontinue_force_level(mcpwm_dev_t *mcpwm, int operator_id, int generator_id, int level) +{ + if (generator_id == 0) { + mcpwm->operators[operator_id].gen_force.gen_a_nciforce_mode = level + 1; + } else { + mcpwm->operators[operator_id].gen_force.gen_b_nciforce_mode = level + 1; + } +} + +////////////////////////////////////////MCPWM Dead Time Specific//////////////////////////////////////////////////////// + +/** + * @brief Set clock source for dead time submodule + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param src Clock source for dead time submodule + */ +static inline void mcpwm_ll_operator_set_deadtime_clock_src(mcpwm_dev_t *mcpwm, int operator_id, mcpwm_ll_deadtime_clock_src_t src) +{ + switch (src) { + case MCPWM_LL_DEADTIME_CLK_SRC_GROUP: + mcpwm->operators[operator_id].dt_cfg.db_clk_sel = 0; + break; + case MCPWM_LL_DEADTIME_CLK_SRC_TIMER: + mcpwm->operators[operator_id].dt_cfg.db_clk_sel = 1; + break; + default: + HAL_ASSERT(false); + } +} + +/** + * @brief Select the generator for RED block + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_deadtime_red_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) +{ + mcpwm->operators[operator_id].dt_cfg.db_red_insel = generator; +} + +/** + * @brief Select the generator for FED block + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param generator Generator ID, index from 0 to 1 + */ +static inline void mcpwm_ll_deadtime_fed_select_generator(mcpwm_dev_t *mcpwm, int operator_id, int generator) +{ + mcpwm->operators[operator_id].dt_cfg.db_fed_insel = generator; +} + +/** + * @brief Set which path to bypass in the deadtime submodule + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param path Path to bypass, index from 0 to 1 + * @param bypass True to bypass, False to not bypass + */ +static inline void mcpwm_ll_deadtime_bypass_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool bypass) +{ + if (bypass) { + mcpwm->operators[operator_id].dt_cfg.val |= 1 << (path + 15); + } else { + mcpwm->operators[operator_id].dt_cfg.val &= ~(1 << (path + 15)); + } +} + +/** + * @brief Invert the output path + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param path Path to invert, index from 0 to 1 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_deadtime_invert_outpath(mcpwm_dev_t *mcpwm, int operator_id, int path, bool invert) +{ + if (invert) { + mcpwm->operators[operator_id].dt_cfg.val |= 1 << (path + 13); + } else { + mcpwm->operators[operator_id].dt_cfg.val &= ~(1 << (path + 13)); + } +} + +/** + * @brief Swap the output path + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param path Path to swap, index from 0 to 1 + * @param swap True to swap, False to not swap + */ +static inline void mcpwm_ll_deadtime_swap_out_path(mcpwm_dev_t *mcpwm, int operator_id, int path, bool swap) +{ + if (swap) { + mcpwm->operators[operator_id].dt_cfg.val |= 1 << (path + 9); + } else { + mcpwm->operators[operator_id].dt_cfg.val &= ~(1 << (path + 9)); + } +} + +/** + * @brief Enable the DEB block + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_deb(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].dt_cfg.db_deb_mode = enable; +} + +/** + * @brief Get the deadtime switch topology + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @return Dead time submodule's switch topology, each bit represents one switch on/off status + */ +static inline uint32_t mcpwm_ll_deadtime_get_switch_topology(mcpwm_dev_t *mcpwm, int operator_id) +{ + return (mcpwm->operators[operator_id].dt_cfg.db_deb_mode << 8) | (mcpwm->operators[operator_id].dt_cfg.db_b_outswap << 7) | + (mcpwm->operators[operator_id].dt_cfg.db_a_outswap << 6) | (mcpwm->operators[operator_id].dt_cfg.db_fed_insel << 5) | + (mcpwm->operators[operator_id].dt_cfg.db_red_insel << 4) | (mcpwm->operators[operator_id].dt_cfg.db_fed_outinvert << 3) | + (mcpwm->operators[operator_id].dt_cfg.db_red_outinvert << 2) | (mcpwm->operators[operator_id].dt_cfg.db_a_outbypass << 1) | + (mcpwm->operators[operator_id].dt_cfg.db_b_outbypass << 0); +} + +/** + * @brief Set falling edge delay duration + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param fed Delay duration, in deadtime submodule's clock cycles + */ +static inline void mcpwm_ll_deadtime_set_falling_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t fed) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operators[operator_id].dt_fed_cfg, db_fed, fed - 1); +} + +/** + * @brief Set rising edge delay duration + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param red Delay duration, in deadtime submodule's clock cycles + */ +static inline void mcpwm_ll_deadtime_set_rising_delay(mcpwm_dev_t *mcpwm, int operator_id, uint32_t red) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->operators[operator_id].dt_red_cfg, db_red, red - 1); +} + +/** + * @brief Update deadtime immediately + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_deadtime_update_delay_at_once(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod = 0; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod = 0; +} + +/** + * @brief Enable to update deadtime on TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_update_delay_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 0; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 0; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 0); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 0); + } +} + +/** + * @brief Enable to update deadtime on TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_update_delay_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 1; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 1; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 1); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 1); + } +} + +/** + * @brief Enable to update deadtime on sync event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_deadtime_enable_update_delay_on_sync(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 2; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 2; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 2); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 2); + } +} + +/** + * @brief Stop updating deadtime + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param stop_or_not True to stop, False to continue + */ +static inline void mcpwm_ll_deadtime_stop_update_delay(mcpwm_dev_t *mcpwm, int operator_id, bool stop_or_not) +{ + if (stop_or_not) { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod |= 1 << 3; + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod |= 1 << 3; + } else { + mcpwm->operators[operator_id].dt_cfg.db_fed_upmethod &= ~(1 << 3); + mcpwm->operators[operator_id].dt_cfg.db_red_upmethod &= ~(1 << 3); + } +} + +////////////////////////////////////////MCPWM Carrier Specific////////////////////////////////////////////////////////// + +/** + * @brief Enable carrier for MCPWM operator + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_carrier_enable(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_en = enable; +} + +/** + * @brief Set prescale for MCPWM carrier source clock + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param prescale Prescale value + */ +static inline void mcpwm_ll_carrier_set_prescale(mcpwm_dev_t *mcpwm, int operator_id, uint8_t prescale) +{ + HAL_ASSERT(prescale > 0 && prescale <= 16); + mcpwm->operators[operator_id].carrier_cfg.chopper_prescale = prescale - 1; +} + +/** + * @brief Set duty cycle of MCPWM carrier + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param carrier_duty Duty cycle value + */ +static inline void mcpwm_ll_carrier_set_duty(mcpwm_dev_t *mcpwm, int operator_id, uint8_t carrier_duty) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_duty = carrier_duty; +} + +/** + * @brief Invert the signal after the carrier is applied + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_carrier_out_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_out_invert = invert; +} + +/** + * @brief Invert the signal before applying the carrier + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_carrier_in_invert(mcpwm_dev_t *mcpwm, int operator_id, bool invert) +{ + mcpwm->operators[operator_id].carrier_cfg.chopper_in_invert = invert; +} + +/** + * @brief Set the first pulse width of the carrier + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param pulse_width Pulse width + */ +static inline void mcpwm_ll_carrier_set_first_pulse_width(mcpwm_dev_t *mcpwm, int operator_id, uint8_t pulse_width) +{ + HAL_ASSERT(pulse_width >= 1); + mcpwm->operators[operator_id].carrier_cfg.chopper_oshtwth = pulse_width - 1; +} + +////////////////////////////////////////MCPWM Fault Specific//////////////////////////////////////////////////////////// + +/** + * @brief Enable GPIO fault detection + * + * @param mcpwm Peripheral instance address + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_fault_enable_detection(mcpwm_dev_t *mcpwm, int fault_sig, bool enable) +{ + if (enable) { + mcpwm->fault_detect.val |= 1 << fault_sig; + } else { + mcpwm->fault_detect.val &= ~(1 << fault_sig); + } +} + +/** + * @brief Set fault polarity (i.e. which level is treated as an active fault) + * + * @param mcpwm Peripheral instance address + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param level Active level, 0 for low, 1 for high + */ +static inline void mcpwm_ll_fault_set_active_level(mcpwm_dev_t *mcpwm, int fault_sig, bool level) +{ + if (level) { + mcpwm->fault_detect.val |= 1 << (fault_sig + 3); + } else { + mcpwm->fault_detect.val &= ~(1 << (fault_sig + 3)); + } +} + +/** + * @brief Clear the OST brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_brake_clear_ost(mcpwm_dev_t *mcpwm, int operator_id) +{ + // a posedge can clear the ost fault status + mcpwm->operators[operator_id].fh_cfg1.tz_clr_ost = 0; + mcpwm->operators[operator_id].fh_cfg1.tz_clr_ost = 1; +} + +/** + * @brief Enable the OST brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_oneshot_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg0.val |= (1 << (7 - fault_sig)); + } else { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(1 << (7 - fault_sig)); + } +} + +/** + * @brief Enable the CBC brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param fault_sig GPIO fault ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_cbc_mode(mcpwm_dev_t *mcpwm, int operator_id, int fault_sig, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg0.val |= (enable << (3 - fault_sig)); + } else { + mcpwm->operators[operator_id].fh_cfg0.val &= ~(1 << (3 - fault_sig)); + } +} + +/** + * @brief Enable refresh the CBC brake on TEZ event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_cbc_refresh_on_tez(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg1.val |= 1 << 1; + } else { + mcpwm->operators[operator_id].fh_cfg1.val &= ~(1 << 1); + } +} + +/** + * @brief Enable refresh the CBC brake on TEP event + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_fault_enable_cbc_refresh_on_tep(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + if (enable) { + mcpwm->operators[operator_id].fh_cfg1.val |= 1 << 2; + } else { + mcpwm->operators[operator_id].fh_cfg1.val &= ~(1 << 2); + } +} + +/** + * @brief Enable software CBC brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_soft_cbc(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].fh_cfg0.tz_sw_cbc = enable; +} + +/** + * @brief Enable software OST brake + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_brake_enable_soft_ost(mcpwm_dev_t *mcpwm, int operator_id, bool enable) +{ + mcpwm->operators[operator_id].fh_cfg0.tz_sw_ost = enable; +} + +/** + * @brief Trigger software CBC brake for once + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_brake_trigger_soft_cbc(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].fh_cfg1.tz_force_cbc = ~mcpwm->operators[operator_id].fh_cfg1.tz_force_cbc; +} + +/** + * @brief Trigger software OST brake for once + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + */ +static inline void mcpwm_ll_brake_trigger_soft_ost(mcpwm_dev_t *mcpwm, int operator_id) +{ + mcpwm->operators[operator_id].fh_cfg1.tz_force_ost = ~mcpwm->operators[operator_id].fh_cfg1.tz_force_ost; +} + +/** + * @brief Whether the OST brake is still active + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @return True if active, False if not + */ +static inline bool mcpwm_ll_ost_brake_active(mcpwm_dev_t *mcpwm, int operator_id) +{ + return mcpwm->operators[operator_id].fh_status.tz_ost_on; +} + +/** + * @brief Whether the CBC brake is still active + * + * @param mcpwm Peripheral instance address + * @param operator_id Operator ID, index from 0 to 2 + * @return True if active, False if not + */ +static inline bool mcpwm_ll_cbc_brake_active(mcpwm_dev_t *mcpwm, int operator_id) +{ + return mcpwm->operators[operator_id].fh_status.tz_cbc_on; +} + +////////////////////////////////////////MCPWM Capture Specific////////////////////////////////////////////////////////// + +/** + * @brief Enable capture timer + * + * @param mcpwm Peripheral instance address + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_timer(mcpwm_dev_t *mcpwm, bool enable) +{ + mcpwm->cap_timer_cfg.cap_timer_en = enable; +} + +/** + * @brief Enable capture channel + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_channel(mcpwm_dev_t *mcpwm, int channel, bool enable) +{ + mcpwm->cap_chn_cfg[channel].capn_en = enable; +} + +/** + * @brief Set sync phase for capture timer + * + * @param mcpwm Peripheral instance address + * @param phase_value Phase value + */ +static inline void mcpwm_ll_capture_set_sync_phase_value(mcpwm_dev_t *mcpwm, uint32_t phase_value) +{ + mcpwm->cap_timer_phase.cap_phase = phase_value; +} + +/** + * @brief Enable sync for capture timer + * + * @param mcpwm Peripheral instance address + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_timer_sync(mcpwm_dev_t *mcpwm, bool enable) +{ + mcpwm->cap_timer_cfg.cap_synci_en = enable; +} + +/** + * @brief Set the timer sync source for MCPWM capture timer + * + * @param mcpwm Peripheral instance address + * @param sync_out_timer MCPWM Timer ID, index from 0 to 2 + */ +static inline void mcpwm_ll_capture_set_timer_sync(mcpwm_dev_t *mcpwm, int sync_out_timer) +{ + mcpwm->cap_timer_cfg.cap_synci_sel = sync_out_timer + 1; +} + +/** + * @brief Set the GPIO sync source for MCPWM capture timer + * + * @param mcpwm Peripheral instance address + * @param gpio_sync GPIO sync ID, index from 0 to 2 + */ +static inline void mcpwm_ll_capture_set_gpio_sync(mcpwm_dev_t *mcpwm, int gpio_sync) +{ + mcpwm->cap_timer_cfg.cap_synci_sel = gpio_sync + 4; +} + +/** + * @brief Trigger a software sync for capture timer + * + * @param mcpwm Peripheral instance address + */ +static inline void mcpwm_ll_capture_trigger_sw_sync(mcpwm_dev_t *mcpwm) +{ + mcpwm->cap_timer_cfg.cap_sync_sw = 1; // auto clear +} + +/** + * @brief Enable capture on positive edge + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_posedge(mcpwm_dev_t *mcpwm, int channel, bool enable) +{ + if (enable) { + mcpwm->cap_chn_cfg[channel].val |= 1 << 2; + } else { + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 2); + } +} + +/** + * @brief Enable capture on negative edge + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param enable True to enable, False to disable + */ +static inline void mcpwm_ll_capture_enable_negedge(mcpwm_dev_t *mcpwm, int channel, bool enable) +{ + if (enable) { + mcpwm->cap_chn_cfg[channel].val |= 1 << 1; + } else { + mcpwm->cap_chn_cfg[channel].val &= ~(1 << 1); + } +} + +/** + * @brief Invert the capture input signal + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param invert True to invert, False to not invert + */ +static inline void mcpwm_ll_invert_input(mcpwm_dev_t *mcpwm, int channel, bool invert) +{ + mcpwm->cap_chn_cfg[channel].capn_in_invert = invert; +} + +/** + * @brief Trigger the software capture for once + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + */ +static inline void mcpwm_ll_trigger_soft_capture(mcpwm_dev_t *mcpwm, int channel) +{ + mcpwm->cap_chn_cfg[channel].capn_sw = 1; // auto clear +} + +/** + * @brief Get the captured value + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @return Captured value + */ +__attribute__((always_inline)) +static inline uint32_t mcpwm_ll_capture_get_value(mcpwm_dev_t *mcpwm, int channel) +{ + return mcpwm->cap_chn[channel].capn_value; +} + +/** + * @brief Get the captured edge + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @return Captured edge + */ +__attribute__((always_inline)) +static inline mcpwm_capture_edge_t mcpwm_ll_capture_get_edge(mcpwm_dev_t *mcpwm, int channel) +{ + return mcpwm->cap_status.val & (1 << channel) ? MCPWM_CAP_EDGE_NEG : MCPWM_CAP_EDGE_POS; +} + +/** + * @brief Set the prescale of the input capture signal + * + * @param mcpwm Peripheral instance address + * @param channel Channel ID, index from 0 to 2 + * @param prescale Prescale value + */ +static inline void mcpwm_ll_capture_set_prescale(mcpwm_dev_t *mcpwm, int channel, uint32_t prescale) +{ + HAL_ASSERT(prescale > 0); + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->cap_chn_cfg[channel], capn_prescale, prescale - 1); +} + +//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// +/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// +/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +static inline uint32_t mcpwm_ll_group_get_clock_prescale(mcpwm_dev_t *mcpwm) +{ + if (mcpwm == &MCPWM0) { + return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm0_clk_div_num) + 1; + } else if (mcpwm == &MCPWM1) { + return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl20, reg_mcpwm1_clk_div_num) + 1; + } +} + +static inline uint32_t mcpwm_ll_timer_get_clock_prescale(mcpwm_dev_t *mcpwm, int timer_id) +{ + mcpwm_timer_cfg0_reg_t cfg0 = mcpwm->timer[timer_id].timer_cfg0; + return cfg0.timer_prescale + 1; +} + +static inline uint32_t mcpwm_ll_timer_get_peak(mcpwm_dev_t *mcpwm, int timer_id, bool symmetric) +{ + return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->timer[timer_id].timer_cfg0, timer_period) + (symmetric ? 0 : 1); +} + +static inline mcpwm_timer_count_mode_t mcpwm_ll_timer_get_count_mode(mcpwm_dev_t *mcpwm, int timer_id) +{ + switch (mcpwm->timer[timer_id].timer_cfg1.timer_mod) { + case 1: + return MCPWM_TIMER_COUNT_MODE_UP; + case 2: + return MCPWM_TIMER_COUNT_MODE_DOWN; + case 3: + return MCPWM_TIMER_COUNT_MODE_UP_DOWN; + case 0: + default: + return MCPWM_TIMER_COUNT_MODE_PAUSE; + } +} + +static inline uint32_t mcpwm_ll_operator_get_compare_value(mcpwm_dev_t *mcpwm, int operator_id, int compare_id) +{ + return HAL_FORCE_READ_U32_REG_FIELD(mcpwm->operators[operator_id].timestamp[compare_id], cmpr); +} + +__attribute__((always_inline)) +static inline uint32_t mcpwm_ll_intr_get_capture_status(mcpwm_dev_t *mcpwm) +{ + return (mcpwm->int_st.val >> 27) & 0x07; +} + +__attribute__((always_inline)) +static inline void mcpwm_ll_intr_clear_capture_status(mcpwm_dev_t *mcpwm, uint32_t capture_mask) +{ + mcpwm->int_clr.val = (capture_mask & 0x07) << 27; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 2759eb9d199..b43748bbb9b 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -23,6 +23,10 @@ config SOC_GPTIMER_SUPPORTED bool default y +config SOC_MCPWM_SUPPORTED + bool + default y + config SOC_ASYNC_MEMCPY_SUPPORTED bool default y @@ -489,7 +493,7 @@ config SOC_RMT_SUPPORT_RC_FAST config SOC_MCPWM_GROUPS int - default 1 + default 2 config SOC_MCPWM_TIMERS_PER_GROUP int diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index d5b08f3e8c7..0fdf8a15ccc 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -228,6 +228,52 @@ typedef enum { //////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// +/** + * @brief Array initializer for all supported clock sources of MCPWM Timer + */ +#if SOC_CLK_TREE_SUPPORTED +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#else +#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief Type of MCPWM timer clock source + */ +typedef enum { + MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_TIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if SOC_CLK_TREE_SUPPORTED + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */ +#else + MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +#endif // SOC_CLK_TREE_SUPPORTED +} soc_periph_mcpwm_timer_clk_src_t; + +/** + * @brief Array initializer for all supported clock sources of MCPWM Capture Timer + */ +#if SOC_CLK_TREE_SUPPORTED +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#else +#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_XTAL} +#endif + +/** + * @brief Type of MCPWM capture clock source + */ +typedef enum { + MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ + MCPWM_CAPTURE_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ +#if SOC_CLK_TREE_SUPPORTED + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */ +#else + MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ +#endif // SOC_CLK_TREE_SUPPORTED +} soc_periph_mcpwm_capture_clk_src_t; + ///////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// /////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32p4/include/soc/mcpwm_struct.h b/components/soc/esp32p4/include/soc/mcpwm_struct.h index f48bd4cf691..a0fa37e83be 100644 --- a/components/soc/esp32p4/include/soc/mcpwm_struct.h +++ b/components/soc/esp32p4/include/soc/mcpwm_struct.h @@ -33,21 +33,21 @@ typedef union { */ typedef union { struct { - /** timer0_prescale : R/W; bitpos: [7:0]; default: 0; + /** timer_prescale : R/W; bitpos: [7:0]; default: 0; * Configures the prescaler value of timern, so that the period of PT0_clk = Period of * PWM_clk * (PWM_TIMERn_PRESCALE + 1) */ - uint32_t timer0_prescale:8; - /** timer0_period : R/W; bitpos: [23:8]; default: 255; + uint32_t timer_prescale:8; + /** timer_period : R/W; bitpos: [23:8]; default: 255; * Configures the period shadow of PWM timern */ - uint32_t timer0_period:16; - /** timer0_period_upmethod : R/W; bitpos: [25:24]; default: 0; + uint32_t timer_period:16; + /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0; * Configures the update method for active register of PWM timern period.\\0: * Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal * zero event */ - uint32_t timer0_period_upmethod:2; + uint32_t timer_period_upmethod:2; uint32_t reserved_26:6; }; uint32_t val; @@ -58,19 +58,19 @@ typedef union { */ typedef union { struct { - /** timer0_start : R/W/SC; bitpos: [2:0]; default: 0; + /** timer_start : R/W/SC; bitpos: [2:0]; default: 0; * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and * stops at the next TEP.\\TEP here and below means the event that happens when the * timer equals to period */ - uint32_t timer0_start:3; - /** timer0_mod : R/W; bitpos: [4:3]; default: 0; + uint32_t timer_start:3; + /** timer_mod : R/W; bitpos: [4:3]; default: 0; * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: * Decrease mode\\3: Up-down mode */ - uint32_t timer0_mod:2; + uint32_t timer_mod:2; uint32_t reserved_5:27; }; uint32_t val; @@ -81,203 +81,53 @@ typedef union { */ typedef union { struct { - /** timer0_synci_en : R/W; bitpos: [0]; default: 0; + /** timer_synci_en : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable timer$n reloading with phase on sync input * event is enabled.\\0: Disable\\1: Enable */ - uint32_t timer0_synci_en:1; - /** timer0_sync_sw : R/W; bitpos: [1]; default: 0; + uint32_t timer_synci_en:1; + /** timer_sync_sw : R/W; bitpos: [1]; default: 0; * Configures the generation of software sync. Toggling this bit will trigger a * software sync. */ - uint32_t timer0_sync_sw:1; - /** timer0_synco_sel : R/W; bitpos: [3:2]; default: 0; + uint32_t timer_sync_sw:1; + /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0; * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: * Invalid, sync_out selects noting */ - uint32_t timer0_synco_sel:2; - /** timer0_phase : R/W; bitpos: [19:4]; default: 0; + uint32_t timer_synco_sel:2; + /** timer_phase : R/W; bitpos: [19:4]; default: 0; * Configures the phase for timer$n reload on sync event. */ - uint32_t timer0_phase:16; - /** timer0_phase_direction : R/W; bitpos: [20]; default: 0; + uint32_t timer_phase:16; + /** timer_phase_direction : R/W; bitpos: [20]; default: 0; * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: * Increase\\1: Decrease */ - uint32_t timer0_phase_direction:1; + uint32_t timer_phase_direction:1; uint32_t reserved_21:11; }; uint32_t val; } mcpwm_timer_sync_reg_t; -/** Type of timer0_status register +/** Type of timer_status register * PWM timer$n status register. */ typedef union { struct { - /** timer0_value : RO; bitpos: [15:0]; default: 0; + /** timer_value : RO; bitpos: [15:0]; default: 0; * Represents current PWM timer$n counter value. */ - uint32_t timer0_value:16; - /** timer0_direction : RO; bitpos: [16]; default: 0; + uint32_t timer_value:16; + /** timer_direction : RO; bitpos: [16]; default: 0; * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement */ - uint32_t timer0_direction:1; + uint32_t timer_direction:1; uint32_t reserved_17:15; }; uint32_t val; } mcpwm_timer_status_reg_t; -/** Type of timer1_cfg1 register - * PWM timer$n working mode and start/stop control register. - */ -typedef union { - struct { - /** timer1_start : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ - uint32_t timer1_start:3; - /** timer1_mod : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ - uint32_t timer1_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timer1_cfg1_reg_t; - -/** Type of timer1_sync register - * PWM timer$n sync function configuration register. - */ -typedef union { - struct { - /** timer1_synci_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ - uint32_t timer1_synci_en:1; - /** timer1_sync_sw : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ - uint32_t timer1_sync_sw:1; - /** timer1_synco_sel : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ - uint32_t timer1_synco_sel:2; - /** timer1_phase : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ - uint32_t timer1_phase:16; - /** timer1_phase_direction : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ - uint32_t timer1_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timer1_sync_reg_t; - -/** Type of timer1_status register - * PWM timer$n status register. - */ -typedef union { - struct { - /** timer1_value : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ - uint32_t timer1_value:16; - /** timer1_direction : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ - uint32_t timer1_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timer1_status_reg_t; - -/** Type of timer2_cfg1 register - * PWM timer$n working mode and start/stop control register. - */ -typedef union { - struct { - /** timer2_start : R/W/SC; bitpos: [2:0]; default: 0; - * Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts, - * then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts - * and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and - * stops at the next TEP.\\TEP here and below means the event that happens when the - * timer equals to period - */ - uint32_t timer2_start:3; - /** timer2_mod : R/W; bitpos: [4:3]; default: 0; - * Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2: - * Decrease mode\\3: Up-down mode - */ - uint32_t timer2_mod:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} mcpwm_timer2_cfg1_reg_t; - -/** Type of timer2_sync register - * PWM timer$n sync function configuration register. - */ -typedef union { - struct { - /** timer2_synci_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable timer$n reloading with phase on sync input - * event is enabled.\\0: Disable\\1: Enable - */ - uint32_t timer2_synci_en:1; - /** timer2_sync_sw : R/W; bitpos: [1]; default: 0; - * Configures the generation of software sync. Toggling this bit will trigger a - * software sync. - */ - uint32_t timer2_sync_sw:1; - /** timer2_synco_sel : R/W; bitpos: [3:2]; default: 0; - * Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: - * Invalid, sync_out selects noting - */ - uint32_t timer2_synco_sel:2; - /** timer2_phase : R/W; bitpos: [19:4]; default: 0; - * Configures the phase for timer$n reload on sync event. - */ - uint32_t timer2_phase:16; - /** timer2_phase_direction : R/W; bitpos: [20]; default: 0; - * Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0: - * Increase\\1: Decrease - */ - uint32_t timer2_phase_direction:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} mcpwm_timer2_sync_reg_t; - -/** Type of timer2_status register - * PWM timer$n status register. - */ -typedef union { - struct { - /** timer2_value : RO; bitpos: [15:0]; default: 0; - * Represents current PWM timer$n counter value. - */ - uint32_t timer2_value:16; - /** timer2_direction : RO; bitpos: [16]; default: 0; - * Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement - */ - uint32_t timer2_direction:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} mcpwm_timer2_status_reg_t; - /** Group: timer_synci_cfg */ /** Type of timer_synci_cfg register @@ -357,337 +207,254 @@ typedef union { */ typedef union { struct { - /** cmpr0_a_upmethod : R/W; bitpos: [3:0]; default: 0; + /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0; * Configures the update method for PWM generator n time stamp A's active * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is * set to 1: Sync\\Bit3 is set to 1: Disable the update */ - uint32_t cmpr0_a_upmethod:4; - /** cmpr0_b_upmethod : R/W; bitpos: [7:4]; default: 0; + uint32_t cmpr_a_upmethod:4; + /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0; * Configures the update method for PWM generator n time stamp B's active * register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is * set to 1: Sync\\Bit3 is set to 1: Disable the update */ - uint32_t cmpr0_b_upmethod:4; - /** cmpr0_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; + uint32_t cmpr_b_upmethod:4; + /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0; * Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0: * A's active reg has been updated with shadow register latest value.\\1: A's shadow * reg is filled and waiting to be transferred to A's active reg */ - uint32_t cmpr0_a_shdw_full:1; - /** cmpr0_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; + uint32_t cmpr_a_shdw_full:1; + /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0; * Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0: * B's active reg has been updated with shadow register latest value.\\1: B's shadow * reg is filled and waiting to be transferred to B's active reg */ - uint32_t cmpr0_b_shdw_full:1; + uint32_t cmpr_b_shdw_full:1; uint32_t reserved_10:22; }; uint32_t val; } mcpwm_gen_stmp_cfg_reg_t; -/** Type of gen0_tstmp_a register +/** Type of gen_tstmp_a register * Generator$n time stamp A's shadow register */ typedef union { struct { - /** cmpr0_a : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp A's shadow register. + /** cmpr : R/W; bitpos: [15:0]; default: 0; + * Configures the value of PWM generator $n time stamp 's shadow register. */ - uint32_t cmpr0_a:16; + uint32_t cmpr:16; uint32_t reserved_16:16; }; uint32_t val; -} mcpwm_gen_tstmp_a_reg_t; +} mcpwm_gen_tstmp_reg_t; -/** Type of gen0_tstmp_b register - * Generator$n time stamp B's shadow register - */ -typedef union { - struct { - /** cmpr0_b : R/W; bitpos: [15:0]; default: 0; - * Configures the value of PWM generator $n time stamp B's shadow register. - */ - uint32_t cmpr0_b:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_gen_tstmp_b_reg_t; -/** Type of gen0_cfg0 register +/** Type of gen_cfg0 register * Generator$n fault event T0 and T1 configuration register */ typedef union { struct { - /** gen0_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; + /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0; * Configures update method for PWM generator $n's active register.\\0: * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: * Sync\\Bit3 is set to 1: Disable the update */ - uint32_t gen0_cfg_upmethod:4; - /** gen0_t0_sel : R/W; bitpos: [6:4]; default: 0; + uint32_t gen_cfg_upmethod:4; + /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0; * Configures source selection for PWM generator $n event_t0, take effect * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: * Invalid, Select nothing */ - uint32_t gen0_t0_sel:3; - /** gen0_t1_sel : R/W; bitpos: [9:7]; default: 0; + uint32_t gen_t0_sel:3; + /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0; * Configures source selection for PWM generator $n event_t1, take effect * immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: * Invalid, Select nothing */ - uint32_t gen0_t1_sel:3; + uint32_t gen_t1_sel:3; uint32_t reserved_10:22; }; uint32_t val; } mcpwm_gen_cfg0_reg_t; -/** Type of gen0_force register +/** Type of gen_force register * Generator$n output signal force mode register. */ typedef union { struct { - /** gen0_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; + /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32; * Configures update method for continuous software force of PWM generator$n.\\0: * Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: * TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable * update. TEA/B here and below means an event generated when the timer's value equals * to that of register A/B. */ - uint32_t gen0_cntuforce_upmethod:6; - /** gen0_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; + uint32_t gen_cntuforce_upmethod:6; + /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0; * Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2: * High\\3: Disabled */ - uint32_t gen0_a_cntuforce_mode:2; - /** gen0_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; + uint32_t gen_a_cntuforce_mode:2; + /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0; * Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2: * High\\3: Disabled */ - uint32_t gen0_b_cntuforce_mode:2; - /** gen0_a_nciforce : R/W; bitpos: [10]; default: 0; + uint32_t gen_b_cntuforce_mode:2; + /** gen_a_nciforce : R/W; bitpos: [10]; default: 0; * Configures the generation of non-continuous immediate software-force event for * PWM$n A, a toggle will trigger a force event. */ - uint32_t gen0_a_nciforce:1; - /** gen0_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; + uint32_t gen_a_nciforce:1; + /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0; * Configures non-continuous immediate software force mode for PWM$n A.\\0: * Disabled\\1: Low\\2: High\\3: Disabled */ - uint32_t gen0_a_nciforce_mode:2; - /** gen0_b_nciforce : R/W; bitpos: [13]; default: 0; + uint32_t gen_a_nciforce_mode:2; + /** gen_b_nciforce : R/W; bitpos: [13]; default: 0; * Configures the generation of non-continuous immediate software-force event for * PWM$n B, a toggle will trigger a force event. */ - uint32_t gen0_b_nciforce:1; - /** gen0_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; + uint32_t gen_b_nciforce:1; + /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0; * Configures non-continuous immediate software force mode for PWM$n B.\\0: * Disabled\\1: Low\\2: High\\3: Disabled */ - uint32_t gen0_b_nciforce_mode:2; + uint32_t gen_b_nciforce_mode:2; uint32_t reserved_16:16; }; uint32_t val; } mcpwm_gen_force_reg_t; -/** Type of gen0_a register +/** Type of gen register * PWM$n output signal A actions configuration register */ typedef union { struct { - /** gen0_a_utez : R/W; bitpos: [1:0]; default: 0; + /** gen_a_utez : R/W; bitpos: [1:0]; default: 0; * Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_utez:2; - /** gen0_a_utep : R/W; bitpos: [3:2]; default: 0; + uint32_t gen_utez:2; + /** gen_a_utep : R/W; bitpos: [3:2]; default: 0; * Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_utep:2; - /** gen0_a_utea : R/W; bitpos: [5:4]; default: 0; + uint32_t gen_utep:2; + /** gen_a_utea : R/W; bitpos: [5:4]; default: 0; * Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_utea:2; - /** gen0_a_uteb : R/W; bitpos: [7:6]; default: 0; + uint32_t gen_utea:2; + /** gen_a_uteb : R/W; bitpos: [7:6]; default: 0; * Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_uteb:2; - /** gen0_a_ut0 : R/W; bitpos: [9:8]; default: 0; + uint32_t gen_uteb:2; + /** gen_a_ut0 : R/W; bitpos: [9:8]; default: 0; * Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_ut0:2; - /** gen0_a_ut1 : R/W; bitpos: [11:10]; default: 0; + uint32_t gen_ut0:2; + /** gen_a_ut1 : R/W; bitpos: [11:10]; default: 0; * Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_ut1:2; - /** gen0_a_dtez : R/W; bitpos: [13:12]; default: 0; + uint32_t gen_ut1:2; + /** gen_a_dtez : R/W; bitpos: [13:12]; default: 0; * Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_dtez:2; - /** gen0_a_dtep : R/W; bitpos: [15:14]; default: 0; + uint32_t gen_dtez:2; + /** gen_a_dtep : R/W; bitpos: [15:14]; default: 0; * Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_dtep:2; - /** gen0_a_dtea : R/W; bitpos: [17:16]; default: 0; + uint32_t gen_dtep:2; + /** gen_a_dtea : R/W; bitpos: [17:16]; default: 0; * Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_dtea:2; - /** gen0_a_dteb : R/W; bitpos: [19:18]; default: 0; + uint32_t gen_dtea:2; + /** gen_a_dteb : R/W; bitpos: [19:18]; default: 0; * Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_dteb:2; - /** gen0_a_dt0 : R/W; bitpos: [21:20]; default: 0; + uint32_t gen_dteb:2; + /** gen_a_dt0 : R/W; bitpos: [21:20]; default: 0; * Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_dt0:2; - /** gen0_a_dt1 : R/W; bitpos: [23:22]; default: 0; + uint32_t gen_dt0:2; + /** gen_a_dt1 : R/W; bitpos: [23:22]; default: 0; * Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No * change\\1: Low\\2: High\\3: Toggle */ - uint32_t gen0_a_dt1:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} mcpwm_gen_a_reg_t; - -/** Type of gen0_b register - * PWM$n output signal B actions configuration register - */ -typedef union { - struct { - /** gen0_b_utez : R/W; bitpos: [1:0]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_utez:2; - /** gen0_b_utep : R/W; bitpos: [3:2]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_utep:2; - /** gen0_b_utea : R/W; bitpos: [5:4]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_utea:2; - /** gen0_b_uteb : R/W; bitpos: [7:6]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_uteb:2; - /** gen0_b_ut0 : R/W; bitpos: [9:8]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_ut0:2; - /** gen0_b_ut1 : R/W; bitpos: [11:10]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_ut1:2; - /** gen0_b_dtez : R/W; bitpos: [13:12]; default: 0; - * Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dtez:2; - /** gen0_b_dtep : R/W; bitpos: [15:14]; default: 0; - * Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dtep:2; - /** gen0_b_dtea : R/W; bitpos: [17:16]; default: 0; - * Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dtea:2; - /** gen0_b_dteb : R/W; bitpos: [19:18]; default: 0; - * Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dteb:2; - /** gen0_b_dt0 : R/W; bitpos: [21:20]; default: 0; - * Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dt0:2; - /** gen0_b_dt1 : R/W; bitpos: [23:22]; default: 0; - * Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No - * change\\1: Low\\2: High\\3: Toggle - */ - uint32_t gen0_b_dt1:2; + uint32_t gen_dt1:2; uint32_t reserved_24:8; }; uint32_t val; -} mcpwm_gen_b_reg_t; +} mcpwm_gen_reg_t; /** Type of dt0_cfg register * Dead time configuration register */ typedef union { struct { - /** db0_fed_upmethod : R/W; bitpos: [3:0]; default: 0; + /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0; * Configures update method for FED (Falling edge delay) active register.\\0: * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: * Sync\\Bit3 is set to 1: Disable the update */ - uint32_t db0_fed_upmethod:4; - /** db0_red_upmethod : R/W; bitpos: [7:4]; default: 0; + uint32_t db_fed_upmethod:4; + /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0; * Configures update method for RED (rising edge delay) active register.\\0: * Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: * Sync\\Bit3 is set to 1: Disable the update */ - uint32_t db0_red_upmethod:4; - /** db0_deb_mode : R/W; bitpos: [8]; default: 0; + uint32_t db_red_upmethod:4; + /** db_deb_mode : R/W; bitpos: [8]; default: 0; * Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path * separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode */ - uint32_t db0_deb_mode:1; - /** db0_a_outswap : R/W; bitpos: [9]; default: 0; + uint32_t db_deb_mode:1; + /** db_a_outswap : R/W; bitpos: [9]; default: 0; * Configures S6 in table. */ - uint32_t db0_a_outswap:1; - /** db0_b_outswap : R/W; bitpos: [10]; default: 0; + uint32_t db_a_outswap:1; + /** db_b_outswap : R/W; bitpos: [10]; default: 0; * Configures S7 in table. */ - uint32_t db0_b_outswap:1; - /** db0_red_insel : R/W; bitpos: [11]; default: 0; + uint32_t db_b_outswap:1; + /** db_red_insel : R/W; bitpos: [11]; default: 0; * Configures S4 in table. */ - uint32_t db0_red_insel:1; - /** db0_fed_insel : R/W; bitpos: [12]; default: 0; + uint32_t db_red_insel:1; + /** db_fed_insel : R/W; bitpos: [12]; default: 0; * Configures S5 in table. */ - uint32_t db0_fed_insel:1; - /** db0_red_outinvert : R/W; bitpos: [13]; default: 0; + uint32_t db_fed_insel:1; + /** db_red_outinvert : R/W; bitpos: [13]; default: 0; * Configures S2 in table. */ - uint32_t db0_red_outinvert:1; - /** db0_fed_outinvert : R/W; bitpos: [14]; default: 0; + uint32_t db_red_outinvert:1; + /** db_fed_outinvert : R/W; bitpos: [14]; default: 0; * Configures S3 in table. */ - uint32_t db0_fed_outinvert:1; - /** db0_a_outbypass : R/W; bitpos: [15]; default: 1; + uint32_t db_fed_outinvert:1; + /** db_a_outbypass : R/W; bitpos: [15]; default: 1; * Configures S1 in table. */ - uint32_t db0_a_outbypass:1; - /** db0_b_outbypass : R/W; bitpos: [16]; default: 1; + uint32_t db_a_outbypass:1; + /** db_b_outbypass : R/W; bitpos: [16]; default: 1; * Configures S0 in table. */ - uint32_t db0_b_outbypass:1; - /** db0_clk_sel : R/W; bitpos: [17]; default: 0; + uint32_t db_b_outbypass:1; + /** db_clk_sel : R/W; bitpos: [17]; default: 0; * Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk */ - uint32_t db0_clk_sel:1; + uint32_t db_clk_sel:1; uint32_t reserved_18:14; }; uint32_t val; @@ -698,10 +465,10 @@ typedef union { */ typedef union { struct { - /** db0_fed : R/W; bitpos: [15:0]; default: 0; + /** db_fed : R/W; bitpos: [15:0]; default: 0; * Configures shadow register for FED. */ - uint32_t db0_fed:16; + uint32_t db_fed:16; uint32_t reserved_16:16; }; uint32_t val; @@ -712,10 +479,10 @@ typedef union { */ typedef union { struct { - /** db0_red : R/W; bitpos: [15:0]; default: 0; + /** db_red : R/W; bitpos: [15:0]; default: 0; * Configures shadow register for RED. */ - uint32_t db0_red:16; + uint32_t db_red:16; uint32_t reserved_16:16; }; uint32_t val; @@ -726,33 +493,33 @@ typedef union { */ typedef union { struct { - /** chopper0_en : R/W; bitpos: [0]; default: 0; + /** chopper_en : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled */ - uint32_t chopper0_en:1; - /** chopper0_prescale : R/W; bitpos: [4:1]; default: 0; + uint32_t chopper_en:1; + /** chopper_prescale : R/W; bitpos: [4:1]; default: 0; * Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of * PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1) */ - uint32_t chopper0_prescale:4; - /** chopper0_duty : R/W; bitpos: [7:5]; default: 0; + uint32_t chopper_prescale:4; + /** chopper_duty : R/W; bitpos: [7:5]; default: 0; * Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8 */ - uint32_t chopper0_duty:3; - /** chopper0_oshtwth : R/W; bitpos: [11:8]; default: 0; + uint32_t chopper_duty:3; + /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0; * Configures width of the first pulse. Measurement unit: Periods of the carrier. */ - uint32_t chopper0_oshtwth:4; - /** chopper0_out_invert : R/W; bitpos: [12]; default: 0; + uint32_t chopper_oshtwth:4; + /** chopper_out_invert : R/W; bitpos: [12]; default: 0; * Configures whether or not to invert the output of PWM$n A and PWM$n B for this * submodule.\\0: Normal\\1: Invert */ - uint32_t chopper0_out_invert:1; - /** chopper0_in_invert : R/W; bitpos: [13]; default: 0; + uint32_t chopper_out_invert:1; + /** chopper_in_invert : R/W; bitpos: [13]; default: 0; * Configures whether or not to invert the input of PWM$n A and PWM$n B for this * submodule.\\0: Normal\\1: Invert */ - uint32_t chopper0_in_invert:1; + uint32_t chopper_in_invert:1; uint32_t reserved_14:18; }; uint32_t val; @@ -763,86 +530,86 @@ typedef union { */ typedef union { struct { - /** tz0_sw_cbc : R/W; bitpos: [0]; default: 0; + /** tz_sw_cbc : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable software force cycle-by-cycle mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_sw_cbc:1; - /** tz0_f2_cbc : R/W; bitpos: [1]; default: 0; + uint32_t tz_sw_cbc:1; + /** tz_f2_cbc : R/W; bitpos: [1]; default: 0; * Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_f2_cbc:1; - /** tz0_f1_cbc : R/W; bitpos: [2]; default: 0; + uint32_t tz_f2_cbc:1; + /** tz_f1_cbc : R/W; bitpos: [2]; default: 0; * Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_f1_cbc:1; - /** tz0_f0_cbc : R/W; bitpos: [3]; default: 0; + uint32_t tz_f1_cbc:1; + /** tz_f0_cbc : R/W; bitpos: [3]; default: 0; * Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_f0_cbc:1; - /** tz0_sw_ost : R/W; bitpos: [4]; default: 0; + uint32_t tz_f0_cbc:1; + /** tz_sw_ost : R/W; bitpos: [4]; default: 0; * Configures whether or not to enable software force one-shot mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_sw_ost:1; - /** tz0_f2_ost : R/W; bitpos: [5]; default: 0; + uint32_t tz_sw_ost:1; + /** tz_f2_ost : R/W; bitpos: [5]; default: 0; * Configures whether or not event_f2 will trigger one-shot mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_f2_ost:1; - /** tz0_f1_ost : R/W; bitpos: [6]; default: 0; + uint32_t tz_f2_ost:1; + /** tz_f1_ost : R/W; bitpos: [6]; default: 0; * Configures whether or not event_f1 will trigger one-shot mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_f1_ost:1; - /** tz0_f0_ost : R/W; bitpos: [7]; default: 0; + uint32_t tz_f1_ost:1; + /** tz_f0_ost : R/W; bitpos: [7]; default: 0; * Configures whether or not event_f0 will trigger one-shot mode action.\\0: * Disable\\1: Enable */ - uint32_t tz0_f0_ost:1; - /** tz0_a_cbc_d : R/W; bitpos: [9:8]; default: 0; + uint32_t tz_f0_ost:1; + /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0; * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_a_cbc_d:2; - /** tz0_a_cbc_u : R/W; bitpos: [11:10]; default: 0; + uint32_t tz_a_cbc_d:2; + /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0; * Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_a_cbc_u:2; - /** tz0_a_ost_d : R/W; bitpos: [13:12]; default: 0; + uint32_t tz_a_cbc_u:2; + /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0; * Configures one-shot mode action on PWM$n A when fault event occurs and timer is * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_a_ost_d:2; - /** tz0_a_ost_u : R/W; bitpos: [15:14]; default: 0; + uint32_t tz_a_ost_d:2; + /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0; * Configures one-shot mode action on PWM$n A when fault event occurs and timer is * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_a_ost_u:2; - /** tz0_b_cbc_d : R/W; bitpos: [17:16]; default: 0; + uint32_t tz_a_ost_u:2; + /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0; * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer * is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_b_cbc_d:2; - /** tz0_b_cbc_u : R/W; bitpos: [19:18]; default: 0; + uint32_t tz_b_cbc_d:2; + /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0; * Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer * is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_b_cbc_u:2; - /** tz0_b_ost_d : R/W; bitpos: [21:20]; default: 0; + uint32_t tz_b_cbc_u:2; + /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0; * Configures one-shot mode action on PWM$n B when fault event occurs and timer is * decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_b_ost_d:2; - /** tz0_b_ost_u : R/W; bitpos: [23:22]; default: 0; + uint32_t tz_b_ost_d:2; + /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0; * Configures one-shot mode action on PWM$n B when fault event occurs and timer is * increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle */ - uint32_t tz0_b_ost_u:2; + uint32_t tz_b_ost_u:2; uint32_t reserved_24:8; }; uint32_t val; @@ -853,26 +620,26 @@ typedef union { */ typedef union { struct { - /** tz0_clr_ost : R/W; bitpos: [0]; default: 0; + /** tz_clr_ost : R/W; bitpos: [0]; default: 0; * Configures the generation of software one-shot mode action clear. A toggle * (software negate its value) triggers a clear for on going one-shot mode action. */ - uint32_t tz0_clr_ost:1; - /** tz0_cbcpulse : R/W; bitpos: [2:1]; default: 0; + uint32_t tz_clr_ost:1; + /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0; * Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select * nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP */ - uint32_t tz0_cbcpulse:2; - /** tz0_force_cbc : R/W; bitpos: [3]; default: 0; + uint32_t tz_cbcpulse:2; + /** tz_force_cbc : R/W; bitpos: [3]; default: 0; * Configures the generation of software cycle-by-cycle mode action. A toggle * (software negate its value) triggers a cycle-by-cycle mode action. */ - uint32_t tz0_force_cbc:1; - /** tz0_force_ost : R/W; bitpos: [4]; default: 0; + uint32_t tz_force_cbc:1; + /** tz_force_ost : R/W; bitpos: [4]; default: 0; * Configures the generation of software one-shot mode action. A toggle (software * negate its value) triggers a one-shot mode action. */ - uint32_t tz0_force_ost:1; + uint32_t tz_force_ost:1; uint32_t reserved_5:27; }; uint32_t val; @@ -883,16 +650,16 @@ typedef union { */ typedef union { struct { - /** tz0_cbc_on : RO; bitpos: [0]; default: 0; + /** tz_cbc_on : RO; bitpos: [0]; default: 0; * Represents whether or not an cycle-by-cycle mode action is on going.\\0:No * action\\1: On going */ - uint32_t tz0_cbc_on:1; - /** tz0_ost_on : RO; bitpos: [1]; default: 0; + uint32_t tz_cbc_on:1; + /** tz_ost_on : RO; bitpos: [1]; default: 0; * Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On * going */ - uint32_t tz0_ost_on:1; + uint32_t tz_ost_on:1; uint32_t reserved_2:30; }; uint32_t val; @@ -1002,31 +769,31 @@ typedef union { */ typedef union { struct { - /** cap0_en : R/W; bitpos: [0]; default: 0; + /** capn_en : R/W; bitpos: [0]; default: 0; * Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable */ - uint32_t cap0_en:1; - /** cap0_mode : R/W; bitpos: [2:1]; default: 0; + uint32_t capn_en:1; + /** capn_mode : R/W; bitpos: [2:1]; default: 0; * Configures which edge of capture on channel n after prescaling is used.\\0: * None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: * Enable capture on the positive edge */ - uint32_t cap0_mode:2; - /** cap0_prescale : R/W; bitpos: [10:3]; default: 0; + uint32_t capn_mode:2; + /** capn_prescale : R/W; bitpos: [10:3]; default: 0; * Configures prescale value on possitive edge of CAPn. Prescale value = * PWM_CAPn_PRESCALE + 1 */ - uint32_t cap0_prescale:8; - /** cap0_in_invert : R/W; bitpos: [11]; default: 0; + uint32_t capn_prescale:8; + /** capn_in_invert : R/W; bitpos: [11]; default: 0; * Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0: * Normal\\1: Invert */ - uint32_t cap0_in_invert:1; - /** cap0_sw : WT; bitpos: [12]; default: 0; + uint32_t capn_in_invert:1; + /** capn_sw : WT; bitpos: [12]; default: 0; * Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a * software forced capture on channel n */ - uint32_t cap0_sw:1; + uint32_t capn_sw:1; uint32_t reserved_13:19; }; uint32_t val; @@ -1039,10 +806,10 @@ typedef union { */ typedef union { struct { - /** cap0_value : RO; bitpos: [31:0]; default: 0; + /** capn_value : RO; bitpos: [31:0]; default: 0; * Represents value of last capture on CAPn */ - uint32_t cap0_value:32; + uint32_t capn_value:32; }; uint32_t val; } mcpwm_cap_chn_reg_t; @@ -2048,28 +1815,14 @@ typedef union { */ typedef union { struct { - /** op0_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; + /** op_tstmp_e1 : R/W; bitpos: [15:0]; default: 0; * Configures generatorn timer stamp E1 value register */ - uint32_t op0_tstmp_e1:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} mcpwm_op_tstmp_e1_reg_t; - -/** Type of op0_tstmp_e2 register - * Generator$n timer stamp E2 value register - */ -typedef union { - struct { - /** op0_tstmp_e2 : R/W; bitpos: [15:0]; default: 0; - * Configures generator$n timer stamp E2 value register - */ - uint32_t op0_tstmp_e2:16; + uint32_t op_tstmp_e:16; uint32_t reserved_16:16; }; uint32_t val; -} mcpwm_op_tstmp_e2_reg_t; +} mcpwm_op_tstmp_reg_t; /** Type of clk register * Global configuration register @@ -2103,20 +1856,18 @@ typedef union { } mcpwm_version_reg_t; typedef struct { - volatile mcpwm_timer_cfg0_reg_t cfg0; - volatile mcpwm_timer_cfg1_reg_t cfg1; - volatile mcpwm_timer_sync_reg_t sync; - volatile mcpwm_timer_status_reg_t status; + volatile mcpwm_timer_cfg0_reg_t timer_cfg0; + volatile mcpwm_timer_cfg1_reg_t timer_cfg1; + volatile mcpwm_timer_sync_reg_t timer_sync; + volatile mcpwm_timer_status_reg_t timer_status; } mcpwm_timer_regs_t; typedef struct { volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg; - volatile mcpwm_gen_tstmp_a_reg_t gen_tstmp_a; - volatile mcpwm_gen_tstmp_b_reg_t gen_tstmp_b; + volatile mcpwm_gen_tstmp_reg_t timestamp[2]; volatile mcpwm_gen_cfg0_reg_t gen_cfg0; volatile mcpwm_gen_force_reg_t gen_force; - volatile mcpwm_gen_a_reg_t gen_a; - volatile mcpwm_gen_b_reg_t gen_b; + volatile mcpwm_gen_reg_t generator[2]; volatile mcpwm_dt_cfg_reg_t dt_cfg; volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg; volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg; @@ -2127,8 +1878,7 @@ typedef struct { } mcpwm_operator_reg_t; typedef struct { - volatile mcpwm_op_tstmp_e1_reg_t tstmp_e1; - volatile mcpwm_op_tstmp_e2_reg_t tstmp_e2; + volatile mcpwm_op_tstmp_reg_t timestamp[2]; } mcpwm_operator_tstmp_reg_t; typedef struct { @@ -2151,11 +1901,13 @@ typedef struct { volatile mcpwm_evt_en_reg_t evt_en; volatile mcpwm_task_en_reg_t task_en; volatile mcpwm_evt_en2_reg_t evt_en2; - volatile mcpwm_operator_tstmp_reg_t op_tstmp[3]; + volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3]; volatile mcpwm_clk_reg_t clk; volatile mcpwm_version_reg_t version; } mcpwm_dev_t; +extern mcpwm_dev_t MCPWM0; +extern mcpwm_dev_t MCPWM1; #ifndef __cplusplus _Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index b0000a6cbc3..ecbae661217 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -34,7 +34,7 @@ #define SOC_AXI_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 // #define SOC_PCNT_SUPPORTED 1 //TODO: IDF-7475 -// #define SOC_MCPWM_SUPPORTED 1 //TODO: IDF-7493 +#define SOC_MCPWM_SUPPORTED 1 // #define SOC_TWAI_SUPPORTED 1 //TODO: IDF-7470 // #define SOC_ETM_SUPPORTED 1 //TODO: IDF-7478 // #define SOC_PARLIO_SUPPORTED 1 //TODO: IDF-7471, TODO: IDF-7472 @@ -273,7 +273,7 @@ #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */ /*-------------------------- MCPWM CAPS --------------------------------------*/ -#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +#define SOC_MCPWM_GROUPS (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has diff --git a/components/soc/esp32p4/mcpwm_periph.c b/components/soc/esp32p4/mcpwm_periph.c index fea03e5a8d4..9fe408099c5 100644 --- a/components/soc/esp32p4/mcpwm_periph.c +++ b/components/soc/esp32p4/mcpwm_periph.c @@ -9,5 +9,144 @@ #include "soc/gpio_sig_map.h" const mcpwm_signal_conn_t mcpwm_periph_signals = { - + .groups = { + [0] = { + .module = PERIPH_MCPWM0_MODULE, + .irq_id = ETS_PWM0_INTR_SOURCE, + .operators = { + [0] = { + .generators = { + [0] = { + .pwm_sig = PWM0_CH0_A_PAD_OUT_IDX + }, + [1] = { + .pwm_sig = PWM0_CH0_B_PAD_OUT_IDX + } + } + }, + [1] = { + .generators = { + [0] = { + .pwm_sig = PWM0_CH1_A_PAD_OUT_IDX + }, + [1] = { + .pwm_sig = PWM0_CH1_B_PAD_OUT_IDX + } + } + }, + [2] = { + .generators = { + [0] = { + .pwm_sig = PWM0_CH2_A_PAD_OUT_IDX + }, + [1] = { + .pwm_sig = PWM0_CH2_B_PAD_OUT_IDX + } + } + } + }, + .gpio_faults = { + [0] = { + .fault_sig = PWM0_F0_PAD_IN_IDX + }, + [1] = { + .fault_sig = PWM0_F1_PAD_IN_IDX + }, + [2] = { + .fault_sig = PWM0_F2_PAD_IN_IDX + } + }, + .captures = { + [0] = { + .cap_sig = PWM0_CAP0_PAD_IN_IDX + }, + [1] = { + .cap_sig = PWM0_CAP1_PAD_IN_IDX + }, + [2] = { + .cap_sig = PWM0_CAP2_PAD_IN_IDX + } + }, + .gpio_synchros = { + [0] = { + .sync_sig = PWM0_SYNC0_PAD_IN_IDX + }, + [1] = { + .sync_sig = PWM0_SYNC1_PAD_IN_IDX + }, + [2] = { + .sync_sig = PWM0_SYNC2_PAD_IN_IDX + } + } + }, + [1] = { + .module = PERIPH_MCPWM1_MODULE, + .irq_id = ETS_PWM1_INTR_SOURCE, + .operators = { + [0] = { + .generators = { + [0] = { + .pwm_sig = PWM1_CH0_A_PAD_OUT_IDX + }, + [1] = { + .pwm_sig = PWM1_CH0_B_PAD_OUT_IDX + } + } + }, + [1] = { + .generators = { + [0] = { + .pwm_sig = PWM1_CH1_A_PAD_OUT_IDX + }, + [1] = { + .pwm_sig = PWM1_CH1_B_PAD_OUT_IDX + } + } + }, + [2] = { + .generators = { + [0] = { + .pwm_sig = PWM1_CH2_A_PAD_OUT_IDX + }, + [1] = { + .pwm_sig = PWM1_CH2_B_PAD_OUT_IDX + } + } + } + }, + .gpio_faults = { + [0] = { + .fault_sig = PWM1_F0_PAD_IN_IDX + }, + [1] = { + .fault_sig = PWM1_F1_PAD_IN_IDX + }, + [2] = { + .fault_sig = PWM1_F2_PAD_IN_IDX + } + }, + .captures = { + [0] = { + .cap_sig = PWM1_CAP0_PAD_IN_IDX + }, + [1] = { + .cap_sig = PWM1_CAP1_PAD_IN_IDX + }, + [2] = { + .cap_sig = PWM1_CAP2_PAD_IN_IDX + } + }, + .gpio_synchros = { + [0] = { + .sync_sig = PWM1_SYNC0_PAD_IN_IDX + }, + [1] = { + .sync_sig = PWM1_SYNC1_PAD_IN_IDX + }, + [2] = { + .sync_sig = PWM1_SYNC2_PAD_IN_IDX + } + } + } + } };