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nvme.c
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/*
* QEMU NVM Express Controller
*
* Copyright (c) 2012, Intel Corporation
*
* Written by Keith Busch <[email protected]>
*
* This code is licensed under the GNU GPL v2 or later.
*/
/**
* Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
*
* http://www.nvmexpress.org/resources/
*/
/**
* Usage: add options:
* -drive file=<file>,if=none,id=<drive_id>
* -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>
*
* The "file" option must point to a path to a real file that you will use as
* the backing storage for your NVMe device. It must be a non-zero length, as
* this will be the disk image that your nvme controller will use to carve up
* namespaces for storage.
*
* Note the "drive" option's "id" name must match the "device nvme" drive's
* name to link the block device used for backing storage to the nvme
* interface.
*
* Advanced optional options:
*
* namespaces=<int> : Namespaces to make out of the backing storage, Default:1
* queues=<int> : Number of possible IO Queues, Default:64
* entries=<int> : Maximum number of Queue entires possible, Default:0x7ff
* max_cqes=<int> : Maximum completion queue entry size, Default:0x4
* max_sqes=<int> : Maximum submission queue entry size, Default:0x6
* mpsmin=<int> : Minimum page size supported, Default:0
* mpsmax=<int> : Maximum page size supported, Default:0
* stride=<int> : Doorbell stride, Default:0
* aerl=<int> : Async event request limit, Default:3
* acl=<int> : Abort command limit, Default:3
* elpe=<int> : Error log page entries, Default:3
* mdts=<int> : Maximum data transfer size, Default:5
* cqr=<int> : Contiguous queues required, Default:1
* vwc=<int> : Volatile write cache enabled, Default:0
* intc=<int> : Interrupt configuration disabled, Default:0
* intc_thresh=<int>: Interrupt coalesce threshold, Default:0
* intc_ttime=<int> : Interrupt coalesce time 100's of usecs, Default:0
* nlbaf=<int> : Number of logical block formats, Default:1
* lba_index=<int> : Default namespace block format index, Default:0
* extended=<int> : Use extended-lba for meta-data, Default:0
* dpc=<int> : Data protection capabilities, Default:0
* dps=<int> : Data protection settings, Default:0
* mc=<int> : Meta-data capabilities, Default:0
* meta=<int> : Meta-data size, Default:0
* oncs=<oncs> : Optional NVMe command support, Default:DSM
* oacs=<oacs> : Optional Admin command support, Default:Format
* cmbsz=<cmbsz> : Controller Memory Buffer CMBSZ register, Default:0
* cmbloc=<cmbloc> : Controller Memory Buffer CMBLOC register, Default:0
* lver=<int> : version of the LightNVM standard to use, Default:1
* ll2pmode=<int> : LightNVM op. mode. 1: hybrid, 0: full host-based. Default: 1
* lsec_size=<int> : Controller Sector Size. Default: 4096
* lsecs_per_pg=<int> : Number of sectors in a flash page. Default: 1
* lpgs_per_blk=<int> : Number of pages per flash block. Default: 256
* lmax_sec_per_rq=<int> : Maximum number of sectors per I/O request. Default: 64
* lmtype=<int> : Media type. Default: 0 (NAND Flash Memory)
* lfmtype=<int> : Flash media type. Default: 0 (SLC)
* lnum_ch=<int> : Number of controller channels. Default: 1
* lnum_lun=<int> : Number of LUNs per channel, Default:1
* lnum_pln=<int> : Number of flash planes per LUN. Supported single (1),
* dual (2) and quad (4) plane modes. Defult: 1
* lreadl2ptbl=<int> : Load logical to physical table. 1: yes, 0: no. Default: 1
* lbbtable=<file> : Load bad block table from file destination (Provide path
* to file. If no file is provided a bad block table will be generation. Look
* at lbbfrequency. Default: Null (no file).
* lbbfrequency:<int> : Bad block frequency for generating bad block table. If
* no frequency is provided LNVM_DEFAULT_BB_FREQ will be used.
* is_volt=<int> : Enable volatile SSD. 1-Enabled, 0-Disabled . Default: 0
*
*
* The logical block formats all start at 512 byte blocks and double for the
* next index. If meta-data is non-zero, half the logical block formats will
* have 0 meta-data, the remaining will start the block size over at 512, but
* with the meta-data size set accordingly. Multiple meta-data sizes are not
* supported.
*
* Parameters will be verified against conflicting capabilities and attributes
* and fail to load if there is a conflict or a configuration the emulated
* device is unable to handle.
*
* Note that when a CMB is requested the NVMe version is set to 1.2,
* for all other cases it is set to 1.1.
*
*/
/**
* Hot-plug support
*
* To hot add a new nvme device, startup the qemu monitor. The easiest way is
* to add '-monitor stdio' option on your startup. At the monitor command line,
* run:
*
* (qemu) drive_add "" if=none,id=<new_drive_id>,file=</path/to/backing/file>
* (qemu) device_add nvme,drive=<new_drive_id>,serial=<serial>,id=<new_id>[,<optional options>]
*
* To hot remove the device, run:
*
* (qemu) device_del <id>
*
* You must have provided the "id" field for device_del to work. You may query
* the available devices by running "info pci" from the qemu monitor.
*
* To query what disks are available to be used as a backing storage, run "info
* block". You cannot assign the same block device to more than one storage
* interface.
*/
/**
* Controller Memory Buffer: For now, you can only turn it on or off, but can't
* tune the exact settings.
*/
#include <block/block_int.h>
#include <block/qapi.h>
#include <exec/memory.h>
#include <hw/block/block.h>
#include <hw/hw.h>
#include <hw/pci/msix.h>
#include <hw/pci/msi.h>
#include <hw/pci/pci.h>
#include <qapi/visitor.h>
#include <qemu/bitops.h>
#include <qemu/bitmap.h>
#include <sysemu/sysemu.h>
#include <sysemu/block-backend.h>
#include <qemu/main-loop.h>
#include <time.h>
#include <sys/time.h>
#include "nvme.h"
#include "trace.h"
#include "volt_ssd.h"
#define NVME_MAX_QS PCI_MSIX_FLAGS_QSIZE
#define NVME_MAX_QUEUE_ENTRIES 0xffff
#define NVME_MAX_STRIDE 12
#define NVME_MAX_NUM_NAMESPACES 256
#define NVME_MAX_QUEUE_ES 0xf
#define NVME_MIN_CQUEUE_ES 0x4
#define NVME_MIN_SQUEUE_ES 0x6
#define NVME_SPARE_THRESHOLD 20
#define NVME_TEMPERATURE 0x143
#define NVME_OP_ABORTED 0xff
#define LNVM_MAX_GRPS_PR_IDENT (20)
#define LNVM_FEAT_EXT_START 64
#define LNVM_FEAT_EXT_END 127
#define LNVM_PBA_UNMAPPED UINT64_MAX
#define LNVM_LBA_UNMAPPED UINT64_MAX
static void nvme_process_sq(void *opaque);
static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (n->cmbsz && addr >= n->ctrl_mem.addr &&
addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
} else {
pci_dma_read(&n->parent_obj, addr, buf, size);
}
}
static void nvme_addr_write(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (n->cmbsz && addr >= n->ctrl_mem.addr &&
addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
memcpy((void *)&n->cmbuf[addr - n->ctrl_mem.addr], buf, size);
return;
} else {
pci_dma_write(&n->parent_obj, addr, buf, size);
}
}
static uint8_t lightnvm_dev(NvmeCtrl *n)
{
return (n->lightnvm_ctrl.id_ctrl.ver_id != 0);
}
static void lightnvm_tbl_initialize(NvmeNamespace *ns)
{
uint32_t len = ns->tbl_entries;
uint32_t i;
for (i = 0; i < len; i++)
ns->tbl[i] = LNVM_LBA_UNMAPPED;
}
static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
{
return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
}
static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
{
return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
}
static void nvme_inc_cq_tail(NvmeCQueue *cq)
{
cq->tail++;
if (cq->tail >= cq->size) {
cq->tail = 0;
cq->phase = !cq->phase;
}
}
static int nvme_cqes_pending(NvmeCQueue *cq)
{
return cq->tail > cq->head ?
cq->head + (cq->size - cq->tail) :
cq->head - cq->tail;
}
static void nvme_inc_sq_head(NvmeSQueue *sq)
{
sq->head = (sq->head + 1) % sq->size;
}
static void nvme_update_cq_head(NvmeCQueue *cq)
{
if (cq->db_addr) {
nvme_addr_read(cq->ctrl, cq->db_addr, &cq->head, sizeof(cq->head));
}
}
static uint8_t nvme_cq_full(NvmeCQueue *cq)
{
nvme_update_cq_head(cq);
return (cq->tail + 1) % cq->size == cq->head;
}
static uint8_t nvme_sq_empty(NvmeSQueue *sq)
{
return sq->head == sq->tail;
}
static void nvme_isr_notify(void *opaque)
{
NvmeCQueue *cq = opaque;
NvmeCtrl *n = cq->ctrl;
if (cq->irq_enabled) {
if (msix_enabled(&(n->parent_obj))) {
msix_notify(&(n->parent_obj), cq->vector);
} else if (msi_enabled(&(n->parent_obj))) {
if (!(n->bar.intms & (1 << cq->vector))) {
msi_notify(&(n->parent_obj), cq->vector);
}
} else {
pci_irq_pulse(&n->parent_obj);
}
}
}
static uint64_t *nvme_setup_discontig(NvmeCtrl *n, uint64_t prp_addr,
uint16_t queue_depth, uint16_t entry_size)
{
int i;
uint16_t prps_per_page = n->page_size >> 3;
uint64_t prp[prps_per_page];
uint16_t total_prps = DIV_ROUND_UP(queue_depth * entry_size, n->page_size);
uint64_t *prp_list = g_malloc0(total_prps * sizeof(*prp_list));
for (i = 0; i < total_prps; i++) {
if (i % prps_per_page == 0 && i < total_prps - 1) {
if (!prp_addr || prp_addr & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
nvme_addr_write(n, prp_addr, (uint8_t *)&prp, sizeof(prp));
prp_addr = le64_to_cpu(prp[prps_per_page - 1]);
}
prp_list[i] = le64_to_cpu(prp[i % prps_per_page]);
if (!prp_list[i] || prp_list[i] & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
}
return prp_list;
}
static hwaddr nvme_discontig(uint64_t *dma_addr, uint16_t page_size,
uint16_t queue_idx, uint16_t entry_size)
{
uint16_t entries_per_page = page_size / entry_size;
uint16_t prp_index = queue_idx / entries_per_page;
uint16_t index_in_prp = queue_idx % entries_per_page;
return dma_addr[prp_index] + index_in_prp * entry_size;
}
static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov,
uint64_t prp1, uint64_t prp2, uint32_t len, NvmeCtrl *n)
{
hwaddr trans_len = n->page_size - (prp1 % n->page_size);
trans_len = MIN(len, trans_len);
int num_prps = (len >> n->page_bits) + 1;
bool cmb = false;
if (!prp1) {
return NVME_INVALID_FIELD | NVME_DNR;
} else if (n->cmbsz && prp1 >= n->ctrl_mem.addr &&
prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) {
cmb = true;
qsg->nsg = 0;
qemu_iovec_init(iov, num_prps);
qemu_iovec_add(iov, (void *)&n->cmbuf[prp1 - n->ctrl_mem.addr], trans_len);
} else {
pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
qemu_sglist_add(qsg, prp1, trans_len);
}
len -= trans_len;
if (len) {
if (!prp2) {
goto unmap;
}
if (len > n->page_size) {
uint64_t prp_list[n->max_prp_ents];
uint32_t nents, prp_trans;
int i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
while (len != 0) {
uint64_t prp_ent = le64_to_cpu(prp_list[i]);
if (i == n->max_prp_ents - 1 && len > n->page_size) {
if (!prp_ent || prp_ent & (n->page_size - 1)) {
goto unmap;
}
i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp_ent, (void *)prp_list,
prp_trans);
prp_ent = le64_to_cpu(prp_list[i]);
}
if (!prp_ent || prp_ent & (n->page_size - 1)) {
goto unmap;
}
trans_len = MIN(len, n->page_size);
if (!cmb){
qemu_sglist_add(qsg, prp_ent, trans_len);
} else {
qemu_iovec_add(iov, (void *)&n->cmbuf[prp_ent - n->ctrl_mem.addr], trans_len);
}
len -= trans_len;
i++;
}
} else {
if (prp2 & (n->page_size - 1)) {
goto unmap;
}
if (!cmb) {
qemu_sglist_add(qsg, prp2, len);
} else {
qemu_iovec_add(iov, (void *)&n->cmbuf[prp2 - n->ctrl_mem.addr], trans_len);
}
}
}
return NVME_SUCCESS;
unmap:
if (!cmb){
qemu_sglist_destroy(qsg);
} else {
qemu_iovec_destroy(iov);
}
return NVME_INVALID_FIELD | NVME_DNR;
}
static uint16_t nvme_dma_write_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2)
{
QEMUSGList qsg;
QEMUIOVector iov;
uint16_t status = NVME_SUCCESS;
if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
return NVME_INVALID_FIELD | NVME_DNR;
}
if (qsg.nsg > 0) {
if (dma_buf_write(ptr, len, &qsg)) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
} else {
if (qemu_iovec_from_buf(&iov, 0, ptr, len) != len) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
}
return status;
}
static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2)
{
QEMUSGList qsg;
QEMUIOVector iov;
uint16_t status = NVME_SUCCESS;
if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
return NVME_INVALID_FIELD | NVME_DNR;
}
if (qsg.nsg > 0) {
if (dma_buf_read(ptr, len, &qsg)) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
} else {
if (qemu_iovec_to_buf(&iov, 0, ptr, len) != len) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
}
return status;
}
static void nvme_post_cqe(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
LnvmCtrl *ln = &n->lightnvm_ctrl;
NvmeSQueue *sq = req->sq;
NvmeCqe *cqe = &req->cqe;
uint8_t phase = cq->phase;
hwaddr addr;
if (cq->phys_contig) {
addr = cq->dma_addr + cq->tail * n->cqe_size;
} else {
addr = nvme_discontig(cq->prp_list, cq->tail, n->page_size,
n->cqe_size);
}
if (ln->err_write && req->is_write) {
if ((ln->err_write_cnt + req->nlb + 1) > ln->err_write) {
int bit = ln->err_write - ln->err_write_cnt;
cqe->res64 = cpu_to_le64(1ULL << bit); /* kill first sector in ppa list */
req->status = 0x40ff; /* FAIL WRITE status code */
ln->err_write_cnt = 0;
printf("nvme: injected error: %u\n", bit);
}
ln->err_write_cnt += req->nlb + 1;
}
cqe->status = cpu_to_le16((req->status << 1) | phase);
cqe->sq_id = cpu_to_le16(sq->sqid);
cqe->sq_head = cpu_to_le16(sq->head);
nvme_addr_write(n, addr, (void *)cqe, sizeof(*cqe));
nvme_inc_cq_tail(cq);
QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
}
static void nvme_post_cqes(void *opaque)
{
NvmeCQueue *cq = opaque;
NvmeRequest *req, *next;
QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
if (nvme_cq_full(cq)) {
break;
}
QTAILQ_REMOVE(&cq->req_list, req, entry);
nvme_post_cqe(cq, req);
}
nvme_isr_notify(cq);
}
static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
uint64_t time_ns = NVME_INTC_TIME(n->features.int_coalescing) * 100 * 1000;
uint8_t thresh = NVME_INTC_THR(n->features.int_coalescing) + 1;
uint8_t coalesce_disabled =
(n->features.int_vector_config[cq->vector] >> 16) & 1;
uint8_t notify;
assert(cq->cqid == req->sq->cqid);
QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
if (nvme_cq_full(cq) || !QTAILQ_EMPTY(&cq->req_list)) {
QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
return;
}
clock_t end = clock();
long double cpu_time_used = ((long double)(end-req->start)) / CLOCKS_PER_SEC * 1000000;
printf("Time spent: %Lf us.\n",cpu_time_used);
nvme_post_cqe(cq, req);
notify = coalesce_disabled || !req->sq->sqid || !time_ns ||
req->status != NVME_SUCCESS || nvme_cqes_pending(cq) >= thresh;
if (!notify) {
if (!timer_pending(cq->timer)) {
timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
time_ns);
}
} else {
nvme_isr_notify(cq);
if (timer_pending(cq->timer)) {
timer_del(cq->timer);
}
}
}
static void nvme_set_error_page(NvmeCtrl *n, uint16_t sqid, uint16_t cid,
uint16_t status, uint16_t location, uint64_t lba, uint32_t nsid)
{
NvmeErrorLog *elp;
elp = &n->elpes[n->elp_index];
elp->error_count = n->error_count++;
elp->sqid = sqid;
elp->cid = cid;
elp->status_field = status;
elp->param_error_location = location;
elp->lba = lba;
elp->nsid = nsid;
n->elp_index = (n->elp_index + 1) % n->elpe;
++n->num_errors;
}
static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type,
uint8_t event_info, uint8_t log_page)
{
NvmeAsyncEvent *event;
if (!(n->bar.csts & NVME_CSTS_READY))
return;
event = (NvmeAsyncEvent *)g_malloc(sizeof(*event));
event->result.event_type = event_type;
event->result.event_info = event_info;
event->result.log_page = log_page;
QSIMPLEQ_INSERT_TAIL(&(n->aer_queue), event, entry);
timer_mod(n->aer_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
static void nvme_aer_process_cb(void *param)
{
NvmeCtrl *n = param;
NvmeRequest *req;
NvmeAerResult *result;
NvmeAsyncEvent *event, *next;;
QSIMPLEQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) {
if (n->outstanding_aers <= 0) {
break;
}
if (n->aer_mask & (1 << event->result.event_type)) {
continue;
}
QSIMPLEQ_REMOVE_HEAD(&n->aer_queue, entry);
n->aer_mask |= 1 << event->result.event_type;
n->outstanding_aers--;
req = n->aer_reqs[n->outstanding_aers];
result = (NvmeAerResult *)&req->cqe.n.result;
result->event_type = event->result.event_type;
result->event_info = event->result.event_info;
result->log_page = event->result.log_page;
g_free(event);
req->status = NVME_SUCCESS;
nvme_enqueue_req_completion(n->cq[0], req);
}
}
static void nvme_rw_cb(void *opaque, int ret)
{
NvmeRequest *req = opaque;
NvmeSQueue *sq = req->sq;
NvmeCtrl *n = sq->ctrl;
NvmeCQueue *cq = n->cq[sq->cqid];
NvmeNamespace *ns = req->ns;
block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
if (!ret) {
req->status = NVME_SUCCESS;
} else {
req->status = NVME_INTERNAL_DEV_ERROR;
}
if (req->status != NVME_SUCCESS) {
nvme_set_error_page(n, sq->sqid, req->cqe.cid, req->status,
offsetof(NvmeRwCmd, slba), req->slba, ns->id);
if (req->is_write) {
bitmap_clear(ns->util, req->slba, req->nlb);
}
} else {
if (lightnvm_dev(n) && req->is_write) {
if (req->nlb > 1) {
int i;
for (i = 0; i < req->nlb; i++)
ns->tbl[req->lightnvm_slba + i] = req->lightnvm_ppa_list[i];
} else {
ns->tbl[req->lightnvm_slba] = req->slba;
}
g_free(req->lightnvm_ppa_list);
}
}
if (req->qsg.nsg) {
qemu_sglist_destroy(&req->qsg);
} else {
qemu_iovec_destroy(&req->iov);
}
nvme_enqueue_req_completion(cq, req);
}
static uint16_t nvme_rw_check_req(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
NvmeRequest *req, uint64_t slba, uint64_t elba, uint32_t nlb, uint16_t ctrl,
uint64_t data_size, uint64_t meta_size)
{
if (elba > le64_to_cpu(ns->id_ns.nsze)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(NvmeRwCmd, nlb), elba, ns->id);
return NVME_LBA_RANGE | NVME_DNR;
}
if (n->id_ctrl.mdts && data_size > n->page_size * (1 << n->id_ctrl.mdts)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, nlb), nlb, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if (meta_size) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, control), ctrl, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if ((ctrl & NVME_RW_PRINFO_PRACT) && !(ns->id_ns.dps & DPS_TYPE_MASK)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, control), ctrl, ns->id);
/* Not contemplated in LightNVM for now */
if (lightnvm_dev(n))
return 0;
return NVME_INVALID_FIELD | NVME_DNR;
}
if (!req->is_write && find_next_bit(ns->uncorrectable, elba, slba) < elba) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_UNRECOVERED_READ,
offsetof(NvmeRwCmd, slba), elba, ns->id);
return NVME_UNRECOVERED_READ;
}
return 0;
}
static inline uint64_t nvme_gen_to_dev_addr(LnvmCtrl *ln, struct ppa_addr *r)
{
uint64_t pln_off = r->g.pl * ln->params.sec_per_log_pl;
uint64_t lun_of = r->g.lun * ln->params.sec_per_lun;
uint64_t blk_off = r->g.blk * ln->params.sec_per_blk;
uint64_t pg_off = r->g.pg * ln->params.secs_per_pg;
uint64_t ret;
ret = r->g.sec + pg_off + blk_off + lun_of + pln_off;
if (ret > ln->params.total_secs)
printf("Lnvm: sector out of bounds\n");
return ret;
}
static uint16_t nvme_lnvm_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
NvmeRequest *req)
{
/* In the case of a LightNVM device. The slba is the logical address, while the actual
* physical block address is stored in Command Dword 11-10. */
LnvmCtrl *ln = &n->lightnvm_ctrl;
LnvmRwCmd *lrw = (LnvmRwCmd *)cmd;
struct ppa_addr psl[ln->params.max_sec_per_rq];
uint64_t msl[ln->params.max_sec_per_rq];
uint64_t sppa;
uint64_t eppa;
uint64_t ppa;
uint64_t *sector_list;
uint64_t *aio_sector_list;
uint32_t nlb = le16_to_cpu(lrw->nlb) + 1;
uint64_t prp1 = le64_to_cpu(lrw->prp1);
uint64_t prp2 = le64_to_cpu(lrw->prp2);
uint64_t spba = le64_to_cpu(lrw->spba);
uint64_t meta = le64_to_cpu(lrw->metadata);
const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
const uint16_t ms = le16_to_cpu(ns->id_ns.lbaf[lba_index].ms);
uint64_t data_size = nlb << data_shift;
uint64_t meta_size = nlb * ms;
uint32_t n_pages = data_size / ln->params.sec_size;
uint16_t is_write = (lrw->opcode == LNVM_CMD_PHYS_WRITE ||
lrw->opcode == LNVM_CMD_HYBRID_WRITE);
uint16_t ctrl = 0;
uint16_t err;
uint8_t i;
printf("\nCommand to namespace %d\n",ns->id);
printf("Cmd opcode: 0x%02x\n",lrw->opcode);
sector_list = g_malloc(sizeof(uint64_t) * ln->params.max_sec_per_rq);
if (!sector_list)
return -ENOMEM;
aio_sector_list = g_malloc(sizeof(uint64_t) * ln->params.max_sec_per_rq);
if (!aio_sector_list) {
g_free(sector_list);
return -ENOMEM;
}
if (n_pages > ln->params.max_sec_per_rq) {
printf("npages too large (%u). Max:%u supported\n",
n_pages, ln->params.max_sec_per_rq);
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(LnvmRwCmd, spba), lrw->slba + nlb, ns->id);
g_free(aio_sector_list);
g_free(sector_list);
return NVME_INVALID_FIELD | NVME_DNR;
} else if ((is_write) && (n_pages < ln->params.sec_per_phys_pl)) {
printf("lnvm: I/O does not respect device write constrains."
"Sectors send: (%u). Min:%u sectors required\n",
n_pages, ln->params.sec_per_phys_pl);
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(LnvmRwCmd, spba), lrw->slba + nlb, ns->id);
g_free(aio_sector_list);
g_free(sector_list);
return NVME_INVALID_FIELD | NVME_DNR;
} else if (n_pages > 1) {
nvme_addr_read(n, spba, (void *)psl, n_pages * sizeof(void *));
nvme_addr_read(n, meta, (void *)msl, n_pages * sizeof(void *));
} else {
psl[0].ppa = spba;
msl[0] = meta;
}
if (spba == LNVM_PBA_UNMAPPED) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(LnvmRwCmd, spba), lrw->slba + nlb, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
ctrl = le16_to_cpu(lrw->control);
req->lightnvm_ppa_list = sector_list;
req->lightnvm_slba = le64_to_cpu(lrw->slba);
req->is_write = is_write;
/* If several LUNs are set up, the ppa list sent by the host will not be
* sequential. In this case, we need to pass on the list of ppas to the dma
* handlers to write/read data to/from the right pysical sector
*/
for (i = 0; i < n_pages; i++) {
ppa = nvme_gen_to_dev_addr(ln, &psl[i]);
sector_list[i] = ppa;
aio_sector_list[i] =
ns->start_block + (ppa << (data_shift - BDRV_SECTOR_BITS));
}
/* If volatile device is active, the aio_sector_list should be the ppa_list */
if(n->is_volt)
memcpy(aio_sector_list, &psl, sizeof(uint64_t)*n_pages);
/* Reuse check logic from nvme_rw */
sppa = nvme_gen_to_dev_addr(ln, &psl[0]);
eppa = nvme_gen_to_dev_addr(ln, &psl[n_pages - 1]);
err = nvme_rw_check_req(n, ns, cmd, req, sppa, eppa, nlb, ctrl,
data_size, meta_size);
if (err)
return err;
if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, prp1), 0, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
req->slba = sppa;
req->meta_size = 0;
req->status = NVME_SUCCESS;
req->nlb = nlb;
req->ns = ns;
dma_acct_start(n->conf.blk, &req->acct, &req->qsg, req->is_write ?
BLOCK_ACCT_WRITE : BLOCK_ACCT_READ);
if (req->qsg.nsg > 0) {
if(n->is_volt){
req->aiocb = req->is_write ?
nvme_volt_dma_blk_write_list(n->conf.blk, &req->qsg, aio_sector_list,
nvme_rw_cb, req) :
nvme_volt_dma_blk_read_list(n->conf.blk, &req->qsg, aio_sector_list,
nvme_rw_cb, req);
}else{
req->aiocb = req->is_write ?
dma_blk_write_list(n->conf.blk, &req->qsg, aio_sector_list,
nvme_rw_cb, req) :
dma_blk_read_list(n->conf.blk, &req->qsg, aio_sector_list,
nvme_rw_cb, req);
}
} else {
uint64_t aio_sector = aio_sector_list[0];
req->aiocb = req->is_write ?
blk_aio_writev(n->conf.blk, aio_sector, &req->iov,
data_size >> 9, nvme_rw_cb, req) :
blk_aio_readv(n->conf.blk, aio_sector, &req->iov,
data_size >> 9, nvme_rw_cb, req);
g_free(aio_sector_list);
}
return NVME_NO_COMPLETE;
}
static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
NvmeRequest *req)
{
NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
uint16_t ctrl = 0;
uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
uint64_t prp1 = le64_to_cpu(rw->prp1);
uint64_t prp2 = le64_to_cpu(rw->prp2);
uint64_t slba;
uint64_t elba;
const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
const uint16_t ms = le16_to_cpu(ns->id_ns.lbaf[lba_index].ms);
uint64_t data_size = nlb << data_shift;
uint64_t meta_size = nlb * ms;
uint64_t aio_slba;
uint16_t err;
slba = le64_to_cpu(rw->slba);
elba = slba + nlb;
req->is_write = rw->opcode == NVME_CMD_WRITE;
aio_slba = ns->start_block + (slba << (data_shift - BDRV_SECTOR_BITS));
ctrl = le16_to_cpu(rw->control);
err = nvme_rw_check_req(n, ns, cmd, req, slba, elba, nlb, ctrl,
data_size, meta_size);
if (err)
return err;
if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, prp1), 0, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
req->slba = slba;
req->meta_size = 0;
req->status = NVME_SUCCESS;
req->nlb = nlb;
req->ns = ns;
dma_acct_start(n->conf.blk, &req->acct, &req->qsg, req->is_write ?
BLOCK_ACCT_WRITE : BLOCK_ACCT_READ);
if (req->qsg.nsg > 0) {
req->aiocb = req->is_write ?
dma_blk_write(n->conf.blk, &req->qsg, aio_slba, nvme_rw_cb, req) :
dma_blk_read(n->conf.blk, &req->qsg, aio_slba, nvme_rw_cb, req);
} else {
req->aiocb = req->is_write ?
blk_aio_writev(n->conf.blk, aio_slba, &req->iov, data_size >> 9, nvme_rw_cb, req) :
blk_aio_readv(n->conf.blk, aio_slba, &req->iov, data_size >> 9, nvme_rw_cb, req);
}
return NVME_NO_COMPLETE;
}
static void nvme_discard_cb(void *opaque, int ret)
{
NvmeRequest *req = opaque;
if (!ret) {
req->status = NVME_SUCCESS;
} else {
req->status = NVME_INTERNAL_DEV_ERROR;
}
}
static uint16_t nvme_dsm(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
NvmeRequest *req)
{
uint32_t dw10 = le32_to_cpu(cmd->cdw10);
uint32_t dw11 = le32_to_cpu(cmd->cdw11);
uint64_t prp1 = le64_to_cpu(cmd->prp1);
uint64_t prp2 = le64_to_cpu(cmd->prp2);
if (dw11 & NVME_DSMGMT_AD) {
uint16_t nr = (dw10 & 0xff) + 1;
uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds - BDRV_SECTOR_BITS;
int i;
uint64_t slba;
uint32_t nlb;
NvmeDsmRange range[nr];
if (nvme_dma_write_prp(n, (uint8_t *)range, sizeof(range), prp1, prp2)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeCmd, prp1), 0, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
req->status = NVME_SUCCESS;
for (i = 0; i < nr; i++) {
slba = le64_to_cpu(range[i].slba);
nlb = le32_to_cpu(range[i].nlb);
if (slba + nlb > le64_to_cpu(ns->id_ns.nsze)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(NvmeCmd, cdw10), slba + nlb, ns->id);
return NVME_LBA_RANGE | NVME_DNR;
}
req->aiocb = blk_aio_discard(n->conf.blk,
ns->start_block + (slba << data_shift),
nlb << data_shift, nvme_discard_cb, req);
aio_poll(blk_get_aio_context(n->conf.blk), true);
if (req->status != NVME_SUCCESS)
return req->status;
bitmap_clear(ns->util, slba, nlb);
}
}
return NVME_SUCCESS;
}
static uint16_t nvme_compare(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
NvmeRequest *req)
{
NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
uint64_t slba = le64_to_cpu(rw->slba);
uint64_t prp1 = le64_to_cpu(rw->prp1);
uint64_t prp2 = le64_to_cpu(rw->prp2);
uint64_t elba = slba + nlb;
uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
uint64_t data_size = nlb << data_shift;
uint64_t offset = ns->start_block + (slba << data_shift);
int i;
if ((slba + nlb) > le64_to_cpu(ns->id_ns.nsze)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(NvmeRwCmd, nlb), elba, ns->id);
return NVME_LBA_RANGE | NVME_DNR;
}
if (n->id_ctrl.mdts && data_size > n->page_size * (1 << n->id_ctrl.mdts)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, nlb), nlb, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, prp1), 0, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if (find_next_bit(ns->uncorrectable, elba, slba) < elba) {
return NVME_UNRECOVERED_READ;
}
for (i = 0; i < req->qsg.nsg; i++) {
uint32_t len = req->qsg.sg[i].len;
uint8_t tmp[2][len];
if (blk_pread(n->conf.blk, offset, tmp[0], len) != len) {
qemu_sglist_destroy(&req->qsg);
nvme_set_error_page(n, req->sq->sqid, req->cqe.cid,
NVME_INTERNAL_DEV_ERROR, offsetof(NvmeRwCmd, slba),
req->slba, ns->id);
return NVME_INTERNAL_DEV_ERROR;
}
nvme_addr_read(n, req->qsg.sg[i].base, tmp[1], len);
if (memcmp(tmp[0], tmp[1], len)) {
qemu_sglist_destroy(&req->qsg);
return NVME_CMP_FAILURE;
}
offset += len;
}
qemu_sglist_destroy(&req->qsg);
return NVME_SUCCESS;
}
static void nvme_misc_cb(void *opaque, int ret)