diff --git a/tdx-compliance/tdx-compliance-cpuid.h b/tdx-compliance/tdx-compliance-cpuid.h
index c996426e..feee2926 100644
--- a/tdx-compliance/tdx-compliance-cpuid.h
+++ b/tdx-compliance/tdx-compliance-cpuid.h
@@ -304,7 +304,9 @@ void initial_cpuid(void)
 	EXP_CPUID_RES_BITS(0x7, 0x1, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0);	//Reserved
 
 	/* CPUID(0x7, 0x1).EDX */
-	EXP_CPUID_RES_BITS(0x7, 0x1, edx, 0, 31, VER1_0 | VER1_5 | VER2_0);	//Reserved
+	EXP_CPUID_RES_BITS(0x7, 0x1, edx, 0, 31, VER2_0);	//Reserved
+	EXP_CPUID_BIT(0x7, 0x1, edx, 4, 1, VER1_5);
+	EXP_CPUID_BIT(0x7, 0x1, edx, 5, 1, VER1_5);
 
 	/* CPUID(0x7, 0x2).EAX */
 	EXP_CPUID_RES_BITS(0x7, 0x2, eax, 0, 31, VER1_5);	//Reserved
diff --git a/tdx-compliance/tdx-compliance-msr.h b/tdx-compliance/tdx-compliance-msr.h
index cad6e158..6ed6ae33 100644
--- a/tdx-compliance/tdx-compliance-msr.h
+++ b/tdx-compliance/tdx-compliance-msr.h
@@ -322,8 +322,9 @@ struct test_msr msr_cases[] = {
 	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER1_0 | VER1_5),
 	DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER2_0),
 	DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x1, VER2_0),
-	DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
-	DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
+//TBD for v1.5: Not in SDM 2019_10 Arch. MSRs list.
+	DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon,  VER2_0),
+	DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER2_0),
 
 	DEF_WRITE_MSR(MSR_IA32_PERF_CAPABILITIES, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
 	DEF_READ_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
@@ -344,8 +345,11 @@ struct test_msr msr_cases[] = {
 	DEF_WRITE_MSR(MSR_PEBS_DATA_CFG, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
 	DEF_READ_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
 	DEF_WRITE_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
-	DEF_READ_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
-	DEF_WRITE_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0),
+
+//TBD for v1.5: Not in SDM 2019_10 Arch. MSRs list.
+	DEF_READ_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER2_0),
+	DEF_WRITE_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER2_0),
+
 	DEF_READ_MSR(MSR_IA32_VMX_BASIC, X86_TRAP_GP, NO_PRE_COND, VER1_0),
 	DEF_READ_MSR(MSR_IA32_VMX_BASIC, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0),
 	DEF_WRITE_MSR(MSR_IA32_VMX_BASIC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0),