diff --git a/IGC/Compiler/CISACodeGen/CISABuilder.cpp b/IGC/Compiler/CISACodeGen/CISABuilder.cpp
index fc20b8508ea4..989e71b2b6d2 100644
--- a/IGC/Compiler/CISACodeGen/CISABuilder.cpp
+++ b/IGC/Compiler/CISACodeGen/CISABuilder.cpp
@@ -5048,7 +5048,8 @@ namespace IGC
             SaveOption(vISA_IncSpillCostAllAddrTaken, false);
         }
 
-        if (IGC_GET_FLAG_VALUE(LscImmOffsMatch) > 0) {
+        if ((IGC_GET_FLAG_VALUE(LscImmOffsMatch) > 0 && m_program->m_DriverInfo->supportsLSCImmediateGlobalBaseOffsetForA32()) ||
+            IGC_GET_FLAG_VALUE(LscImmOffsMatch) > 1) {
             auto val = IGC_GET_FLAG_VALUE(LscImmOffsVisaOpts);
             SaveOption(vISA_lscEnableImmOffsFor, val);
         } else {
diff --git a/IGC/Compiler/CISACodeGen/DriverInfo.hpp b/IGC/Compiler/CISACodeGen/DriverInfo.hpp
index c4ca1f5c0af1..62fc1732e0e0 100644
--- a/IGC/Compiler/CISACodeGen/DriverInfo.hpp
+++ b/IGC/Compiler/CISACodeGen/DriverInfo.hpp
@@ -363,6 +363,13 @@ namespace IGC
 
         // Specifies alignment of indirect data
         virtual unsigned getCrossThreadDataAlignment() const { return 32; }
+
+        // Informs if LSC immediate global offset for A64 is supported
+        virtual bool supportsLSCImmediateGlobalBaseOffsetForA64() const { return true; }
+
+        // Informs if LSC immediate global offset for A32 is supported
+        virtual bool supportsLSCImmediateGlobalBaseOffsetForA32() const { return true; }
+
 protected:
     bool autoGRFSelection = false;
     };
diff --git a/IGC/Compiler/CISACodeGen/PatternMatchPass.cpp b/IGC/Compiler/CISACodeGen/PatternMatchPass.cpp
index 047e98fe60e6..da05f3e621ca 100644
--- a/IGC/Compiler/CISACodeGen/PatternMatchPass.cpp
+++ b/IGC/Compiler/CISACodeGen/PatternMatchPass.cpp
@@ -46,7 +46,6 @@ IGC_INITIALIZE_PASS_END(CodeGenPatternMatch, PASS_FLAG, PASS_DESCRIPTION, PASS_C
 
 namespace IGC
 {
-
     CodeGenPatternMatch::CodeGenPatternMatch() : FunctionPass(ID),
         m_rootIsSubspanUse(false),
         m_blocks(nullptr),
@@ -397,6 +396,15 @@ namespace IGC
         ConstantPlacement[C] = LCA;
     }
 
+    bool CodeGenPatternMatch::supportsLSCImmediateGlobalBaseOffset()
+    {
+        bool res = IGC_GET_FLAG_VALUE(LscImmOffsMatch) > 1 ||
+            (m_Platform.matchImmOffsetsLSC() &&
+                (m_ctx->m_DriverInfo.supportsLSCImmediateGlobalBaseOffsetForA64() ||
+                    m_ctx->m_DriverInfo.supportsLSCImmediateGlobalBaseOffsetForA32()));
+        return res;
+    }
+
     // Check bool values that can be emitted as a single element predicate.
     void CodeGenPatternMatch::gatherUniformBools(Value* Val)
     {
@@ -1281,7 +1289,7 @@ namespace IGC
             case GenISAIntrinsic::GenISA_ldraw_indexed:
             case GenISAIntrinsic::GenISA_storerawvector_indexed:
             case GenISAIntrinsic::GenISA_storeraw_indexed:
-                match = m_Platform.matchImmOffsetsLSC() ?
+                match = supportsLSCImmediateGlobalBaseOffset() ?
                     MatchImmOffsetLSC(I) || MatchSingleInstruction(I) :
                     MatchSingleInstruction(I);
                 break;
@@ -1454,7 +1462,7 @@ namespace IGC
     void CodeGenPatternMatch::visitStoreInst(StoreInst& I)
     {
         bool match = false;
-        if (m_Platform.matchImmOffsetsLSC()) {
+        if (supportsLSCImmediateGlobalBaseOffset()) {
             match = MatchImmOffsetLSC(I);
             if (match) return;
         }
@@ -1465,7 +1473,7 @@ namespace IGC
     void CodeGenPatternMatch::visitLoadInst(LoadInst& I)
     {
         bool match = false;
-        if (m_Platform.matchImmOffsetsLSC()) {
+        if (supportsLSCImmediateGlobalBaseOffset()) {
             match = MatchImmOffsetLSC(I);
             if (match)
                 return;
@@ -2609,11 +2617,25 @@ namespace IGC
 
         llvm::Instruction *addSubInst =
             llvm::dyn_cast<llvm::Instruction>(I.getOperand((unsigned)addrOpnd));
-        llvm::Instruction *intToPtrInst = nullptr;
         if (!addSubInst) {
             // e.g. the address is a constant
             return false;
         }
+
+        Type* addInstType = addSubInst->getType();
+        // Note that the A64 addressing mode can be only connected with load and store instructions
+        bool isA64AddressingModel = addInstType->isPointerTy() &&
+            IGC::isA64Ptr(cast<PointerType>(addInstType), m_ctx);
+
+        bool isSupportedCase =
+            (isA64AddressingModel && m_ctx->m_DriverInfo.supportsLSCImmediateGlobalBaseOffsetForA64()) ||
+            (!isA64AddressingModel && m_ctx->m_DriverInfo.supportsLSCImmediateGlobalBaseOffsetForA32()) ||
+            IGC_GET_FLAG_VALUE(LscImmOffsMatch) > 1;
+        if (!isSupportedCase)
+        {
+            return false;
+        }
+        llvm::Instruction* intToPtrInst = nullptr;
         if (addSubInst->getOpcode() == llvm::Instruction::IntToPtr) {
             intToPtrInst = addSubInst;
             addSubInst = llvm::dyn_cast<llvm::Instruction>(addSubInst->getOperand(0));
diff --git a/IGC/Compiler/CISACodeGen/PatternMatchPass.hpp b/IGC/Compiler/CISACodeGen/PatternMatchPass.hpp
index 98e2d011b77a..53efe5eff9bd 100644
--- a/IGC/Compiler/CISACodeGen/PatternMatchPass.hpp
+++ b/IGC/Compiler/CISACodeGen/PatternMatchPass.hpp
@@ -293,6 +293,9 @@ namespace IGC
             return m_WI && (m_WI->isUniform(V));
         };
 
+        bool supportsLSCImmediateGlobalBaseOffset();
+
+
     public:
         llvm::DenseSet<llvm::Instruction*>       m_usedInstructions;
         bool                  m_rootIsSubspanUse;