From 97911b96ce108c78fd6060f3f302ab79341e83c4 Mon Sep 17 00:00:00 2001 From: "Sastriawan, Joko" Date: Wed, 18 Sep 2024 07:41:28 -0700 Subject: [PATCH] feat: LNL PMT XML release --- xml/LNL/0/lnla0_0r5_aggregator.xml | 6629 ++++++++++++++++ xml/LNL/0/lnla0_0r5_aggregator_interface.xml | 7055 ++++++++++++++++++ xml/LNL/0/lnla0_0r5_common.xml | 268 + xml/LNL/1/lnla0_1r5_aggregator.xml | 1541 ++++ xml/LNL/1/lnla0_1r5_aggregator_interface.xml | 1956 +++++ xml/LNL/1/lnla0_1r5_common.xml | 268 + xml/pmt.xml | 26 +- 7 files changed, 17742 insertions(+), 1 deletion(-) create mode 100644 xml/LNL/0/lnla0_0r5_aggregator.xml create mode 100644 xml/LNL/0/lnla0_0r5_aggregator_interface.xml create mode 100644 xml/LNL/0/lnla0_0r5_common.xml create mode 100644 xml/LNL/1/lnla0_1r5_aggregator.xml create mode 100644 xml/LNL/1/lnla0_1r5_aggregator_interface.xml create mode 100644 xml/LNL/1/lnla0_1r5_common.xml diff --git a/xml/LNL/0/lnla0_0r5_aggregator.xml b/xml/LNL/0/lnla0_0r5_aggregator.xml new file mode 100644 index 0000000..b80ff79 --- /dev/null +++ b/xml/LNL/0/lnla0_0r5_aggregator.xml @@ -0,0 +1,6629 @@ + +]> + + + &otherfile; + LNL + LNL M/P PMT Telemetry aggregator 0 samples definition and transformation rules + 0x03072005 + LNL + 0 + + + Groupname 0x82e8 + 64 + + Local Revision ID for this product (revision of the xml) + GLOBAL_ID + Snapshot + 8 + 0 + 7 + + + 1' for Fixed block telemetry ID, '0' for rest. Default is '0' + GLOBAL_ID + Snapshot + 1 + 8 + 8 + + + Product ID= 22 | TGLUY= 23 | TGLH= 24 | TGLS= 79 | ADL-P= 80 | ADL-S= 90 | RPL= 91 | RPL-P= 92 | RPL-S= 103 | MTL-M= 104 | MTL-P= 105 | MTL-S= 106 | ARL= 114 | LNL-M= 134 | PTL-P= 135 | PTL-H + GLOBAL_ID + Snapshot + 12 + 12 + 23 + + + source id for data provider + GLOBAL_ID + Snapshot + 6 + 24 + 29 + + + reserved + GLOBAL_ID + Snapshot + 2 + 30 + 31 + + + Represents the clock rate of the XTAL on this silicon.= 0 | 24MHz= 1 | 19.2MHz= 2 | 38.4MHz= 3 | 25MHz + STRAPS + Snapshot + 2 + 32 + 33 + + + reserved + STRAPS + Snapshot + 30 + 34 + 63 + + + + Groupname 0x82f0 + 64 + + ICCMAX level for the IPU's IS system + IPU_WORKPOINT + Snapshot + 8 + 0 + 7 + + + ICCMAX level for the IPU's PS system + IPU_WORKPOINT + Snapshot + 8 + 8 + 15 + + + Processing system frequency. Frequency is ratio*25MHz. Zero means power down. + IPU_WORKPOINT + Snapshot + 8 + 16 + 23 + + + IS system frequency. Frequency is ratio*16MHz. Zero means power down. + IPU_WORKPOINT + Snapshot + 8 + 24 + 31 + + + IS voltage requirement + IPU_WORKPOINT + Snapshot + 8 + 32 + 39 + + + PS voltage requirement + IPU_WORKPOINT + Snapshot + 8 + 40 + 47 + + + reserved + IPU_WORKPOINT + Snapshot + 16 + 48 + 63 + + + + Groupname 0x82f8 + 64 + + Qclk frequency for Mem SS in units of 33MHz + SA_OTHERS_WORKPOINT0 + Snapshot + 8 + 0 + 7 + + + Mem SS voltage requirement + SA_OTHERS_WORKPOINT0 + Snapshot + 8 + 8 + 15 + + + CDCLK frequency for display + SA_OTHERS_WORKPOINT0 + Snapshot + 10 + 16 + 25 + + + Display voltage requirement + SA_OTHERS_WORKPOINT0 + Snapshot + 8 + 26 + 33 + + + NCLK frequency + SA_OTHERS_WORKPOINT0 + Snapshot + 8 + 34 + 41 + + + NCLK voltage requirement + SA_OTHERS_WORKPOINT0 + Snapshot + 8 + 42 + 49 + + + D2D frequency in units of 50MHz + SA_OTHERS_WORKPOINT0 + Snapshot + 8 + 50 + 57 + + + reserved + SA_OTHERS_WORKPOINT0 + Snapshot + 6 + 58 + 63 + + + + Groupname 0x8300 + 64 + + VPU frequency in units of 50MHz + VPU_WORKPOINT + Snapshot + 8 + 0 + 7 + + + VPU voltage requirement + VPU_WORKPOINT + Snapshot + 8 + 8 + 15 + + + Indicates the tile configuration internal to VPU + VPU_WORKPOINT + Snapshot + 8 + 16 + 23 + + + reserved + VPU_WORKPOINT + Snapshot + 8 + 24 + 31 + + + Media voltage requirement + MEDIA_WORKPOINT + Snapshot + 8 + 32 + 39 + + + Media ratio in units of 50MHz + MEDIA_WORKPOINT + Snapshot + 8 + 48 + 55 + + + Reserved + MEDIA_WORKPOINT + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8308 + 64 + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + LLC_WORKPOINT + Snapshot + 11 + 0 + 10 + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + LLC_WORKPOINT + Snapshot + 10 + 11 + 20 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + LLC_WORKPOINT + Snapshot + 3 + 21 + 23 + + + IA Module clock ratio, in units of 100MHz. + LLC_WORKPOINT + Snapshot + 8 + 24 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT0 + Snapshot + 11 + 32 + 42 + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT0 + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT0 + Snapshot + 3 + 53 + 55 + + + IA Module clock ratio, in units of 100MHz. + CCP_WORKPOINT0 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8310 + 64 + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT1 + Snapshot + 11 + 0 + 10 + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT1 + Snapshot + 10 + 11 + 20 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT1 + Snapshot + 3 + 21 + 23 + + + IA Module clock ratio, in units of 100MHz. + CCP_WORKPOINT1 + Snapshot + 8 + 24 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT2 + Snapshot + 11 + 32 + 42 + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT2 + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT2 + Snapshot + 3 + 53 + 55 + + + IA Module clock ratio, in units of 100MHz. + CCP_WORKPOINT2 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8318 + 64 + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT3 + Snapshot + 11 + 0 + 10 + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT3 + Snapshot + 10 + 11 + 20 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT3 + Snapshot + 3 + 21 + 23 + + + IA Module clock ratio, in units of 100MHz. + CCP_WORKPOINT3 + Snapshot + 8 + 24 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT4 + Snapshot + 11 + 32 + 42 + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT4 + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + CCP_WORKPOINT4 + Snapshot + 3 + 53 + 55 + + + IA Module clock ratio, in units of 100MHz. + CCP_WORKPOINT4 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8320 + 64 + + reserved + RSVD_8320 + Snapshot + 32 + 0 + 31 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if GT modules are supplied by internal VR, otherwise value should be ignored. + GT_WORKPOINT + Snapshot + 11 + 32 + 42 + + + Reserved + GT_WORKPOINT + Snapshot + 10 + 43 + 52 + + + Internal VR power state (PS). valid only if GT modules are supplied by internal VR, otherwise value should be ignored. + GT_WORKPOINT + Snapshot + 3 + 53 + 55 + + + GT clock ratio, in units of 50MHz + GT_WORKPOINT + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8328 + 64 + + Indicates systolic config + GT_CONFIG_REQ + Snapshot + 1 + 1 + 1 + + + EUs active + GT_CONFIG_REQ + Snapshot + 8 + 2 + 9 + + + unused in LNL + GT_CONFIG_REQ + Snapshot + 3 + 10 + 12 + + + subslice count + GT_CONFIG_REQ + Snapshot + 5 + 13 + 17 + + + active slices in GT + GT_CONFIG_REQ + Snapshot + 4 + 18 + 21 + + + reserved + GT_CONFIG_REQ + Snapshot + 10 + 22 + 31 + + + Graphics Security Controller (GSC). 0 - GSC is power-gated. 1 - GSC is not power-gated. + MEDIA_CONFIG_REQ + Snapshot + 1 + 32 + 32 + + + Total number of active media engines in Media. Inactive means power-gated, that is, no leakage. The range in LNL is 0-1, since LNL Media has only 1 slice. + MEDIA_CONFIG_REQ + Snapshot + 3 + 33 + 35 + + + Reserved + MEDIA_CONFIG_REQ + Snapshot + 28 + 36 + 63 + + + + Groupname 0x8330 + 64 + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_0_1 + Snapshot + 8 + 0 + 7 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_0_1 + Snapshot + 3 + 8 + 10 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 11 + 11 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 12 + 12 + + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_0_1 + Snapshot + 8 + 16 + 23 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_0_1 + Snapshot + 3 + 24 + 26 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 27 + 27 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_0_1 + Snapshot + 1 + 28 + 28 + + + reserved + SVID_WORKPOINT_0_1 + Snapshot + 3 + 29 + 31 + + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_2_3 + Snapshot + 8 + 32 + 39 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_2_3 + Snapshot + 3 + 40 + 42 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 43 + 43 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 44 + 44 + + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_2_3 + Snapshot + 8 + 48 + 55 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_2_3 + Snapshot + 3 + 56 + 58 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 59 + 59 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_2_3 + Snapshot + 1 + 60 + 60 + + + reserved + SVID_WORKPOINT_2_3 + Snapshot + 3 + 61 + 63 + + + + Groupname 0x8338 + 64 + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_4_5 + Snapshot + 8 + 0 + 7 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_4_5 + Snapshot + 3 + 8 + 10 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_4_5 + Snapshot + 1 + 11 + 11 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_4_5 + Snapshot + 1 + 12 + 12 + + + VID Code. Encoding is based on SVID spec. + SVID_WORKPOINT_4_5 + Snapshot + 8 + 16 + 23 + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + SVID_WORKPOINT_4_5 + Snapshot + 3 + 24 + 26 + + + Issue FAST ramp, instead of SLOW ramp. + SVID_WORKPOINT_4_5 + Snapshot + 1 + 27 + 27 + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + SVID_WORKPOINT_4_5 + Snapshot + 1 + 28 + 28 + + + reserved + SVID_WORKPOINT_4_5 + Snapshot + 3 + 29 + 31 + + + last SVID0 VR current reading - translated IMON version for VCCIA, in amps. U16.8.8 + SVID_ICC_0_1 + Snapshot + 16 + 32 + 47 + + + last SVID1 VR current reading - translated IMON version for VCCGT, in amps. U16.8.8 + SVID_ICC_0_1 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8340 + 64 + + last SVID2 VR current reading - translated IMON version for VCCSA, in amps. U16.8.8 + SVID_ICC_2_3 + Snapshot + 16 + 0 + 15 + + + last SVID3 VR current reading - translated IMON version for VCCATOM, in amps. U16.8.8 + SVID_ICC_2_3 + Snapshot + 16 + 16 + 31 + + + last SVID4 VR current reading - translated IMON version for VCCL2, in amps. U16.8.8 + SVID_ICC_4_5 + Snapshot + 16 + 32 + 47 + + + last SVID5 VR current reading - translated IMON version for VCCL2, in amps. U16.8.8 + SVID_ICC_4_5 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8348 + 64 + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 0 + 2 + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 3 + 5 + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 6 + 8 + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 9 + 11 + + + IA Core C-state of Atom core0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 12 + 14 + + + LLC/Ring C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + IA_CLUSTER_CSTATES + Snapshot + 3 + 24 + 26 + + + Iceland cluster C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + IA_CLUSTER_CSTATES + Snapshot + 3 + 27 + 29 + + + GT RC-state0: C01: C13: C67: CRST + IA_CLUSTER_CSTATES + Snapshot + 3 + 30 + 32 + + + reserved + IA_CLUSTER_CSTATES + Snapshot + 31 + 33 + 63 + + + + Groupname 0x8350 + 64 + + CDYN level granted that CORE0 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + CDYN_LEVEL + Snapshot + 4 + 0 + 3 + + + CDYN level granted that CORE1 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + CDYN_LEVEL + Snapshot + 4 + 4 + 7 + + + CDYN level granted that CORE2 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + CDYN_LEVEL + Snapshot + 4 + 8 + 11 + + + CDYN level granted that CORE3 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + CDYN_LEVEL + Snapshot + 4 + 12 + 15 + + + CDYN level granted that Atom module0 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + CDYN_LEVEL + Snapshot + 6 + 16 + 21 + + + reserved + CDYN_LEVEL + Snapshot + 42 + 22 + 63 + + + + Groupname 0x8358 + 64 + + Current PCH temperature + SOC_TEMPERATURES + Snapshot + 8 + 0 + 7 + + + Current reading from System Agent "always on" temperature sensor + SOC_TEMPERATURES + Snapshot + 8 + 16 + 23 + + + Current reading from IPU subsystem temperature sensor + SOC_TEMPERATURES + Snapshot + 8 + 24 + 31 + + + Current reading from Display subsystem temperature sensor + SOC_TEMPERATURES + Snapshot + 8 + 32 + 39 + + + Current reading from VPU subsystem temperature sensor + SOC_TEMPERATURES + Snapshot + 8 + 40 + 47 + + + Current reading from Media subsystem temperature sensor + SOC_TEMPERATURES + Snapshot + 8 + 48 + 55 + + + reserved + SOC_TEMPERATURES + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8360 + 64 + + Min temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 0 + 7 + + + Max temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 8 + 15 + + + Min temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 16 + 23 + + + Max temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 24 + 31 + + + Min temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 32 + 39 + + + Max temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 40 + 47 + + + Min temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 48 + 55 + + + Max temp across the core + BIG_CORE_TEMPERATURE + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8368 + 64 + + Min temp across the atom module + COMPUTE_TEMPERATURE + Snapshot + 8 + 0 + 7 + + + Max temp across the atom module + COMPUTE_TEMPERATURE + Snapshot + 8 + 8 + 15 + + + reserved + COMPUTE_TEMPERATURE + Snapshot + 8 + 24 + 31 + + + LLC Min temp + COMPUTE_TEMPERATURE + Snapshot + 8 + 32 + 39 + + + LLC Max temp + COMPUTE_TEMPERATURE + Snapshot + 8 + 40 + 47 + + + Graphics Min temp + COMPUTE_TEMPERATURE + Snapshot + 8 + 48 + 55 + + + Graphics Max temp + COMPUTE_TEMPERATURE + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8370 + 64 + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE0_3 + Snapshot + 16 + 0 + 15 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE0_3 + Snapshot + 16 + 16 + 31 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE0_3 + Snapshot + 16 + 32 + 47 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE0_3 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8378 + 64 + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE4_7 + Snapshot + 16 + 0 + 15 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE4_7 + Snapshot + 16 + 16 + 31 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE4_7 + Snapshot + 16 + 32 + 47 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + IA_SCALABILITY_CORE4_7 + Snapshot + 16 + 48 + 63 + + + + Groupname 0x8380 + 64 + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 0 + 7 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 8 + 15 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 16 + 23 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE0_3 + Snapshot + 8 + 24 + 31 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 32 + 39 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 40 + 47 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 48 + 55 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + IA_P_ALPHA_TARGET_CORE4_7 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8388 + 64 + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE0_3 + Snapshot + 8 + 0 + 7 + + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE0_3 + Snapshot + 8 + 8 + 15 + + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE0_3 + Snapshot + 8 + 16 + 23 + + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE0_3 + Snapshot + 8 + 24 + 31 + + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE4_7 + Snapshot + 8 + 32 + 39 + + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE4_7 + Snapshot + 8 + 40 + 47 + + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE4_7 + Snapshot + 8 + 48 + 55 + + + Current autonomous frequency target for that IA Core + IA_AUTONOMOUS_TARGET_CORE4_7 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8390 + 64 + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 0 + 7 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 8 + 15 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 16 + 23 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE0_3 + Snapshot + 8 + 24 + 31 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 32 + 39 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 40 + 47 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 48 + 55 + + + Current efficient frequency target for that IA Core + IA_EFFICIENT_FREQUENCY_CORE4_7 + Snapshot + 8 + 56 + 63 + + + + Groupname 0x8398 + 64 + + Current GT Efficient P-state (used as the floor for autonomous control) + GT_EFFICIENT_FREQUENCY + Snapshot + 8 + 0 + 7 + + + reserved + GT_EFFICIENT_FREQUENCY + Snapshot + 56 + 8 + 63 + + + + Groupname 0x83a0 + 64 + + Temperature of PECI sensor in 1/32 DegC + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 0 + 15 + + + Temperature of PECI sensor in 1/32 DegC + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 16 + 31 + + + Temperature of PECI sensor in 1/32 DegC + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 32 + 47 + + + reserved + PLATFORM_TEMPERATURE_EC + Snapshot + 16 + 48 + 63 + + + + Groupname 0x83a8 + 64 + + Contains EC settings for sensor 0. + PLATFORM_TEMPERATURE_EC_SETTINGS_0 + Snapshot + 32 + 0 + 31 + + + Contains EC settings for sensor 1. + PLATFORM_TEMPERATURE_EC_SETTINGS_0 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83b0 + 64 + + Contains EC settings for sensor 2. + PLATFORM_TEMPERATURE_EC_SETTINGS_1 + Snapshot + 32 + 0 + 31 + + + reserved + PLATFORM_TEMPERATURE_EC_SETTINGS_1 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83b8 + 64 + + Contains MMIO settings for sensor 0. + PLATFORM_TEMPERATURE_MMIO_SETTINGS_0 + Snapshot + 32 + 0 + 31 + + + Contains MMIO settings for sensor 1. + PLATFORM_TEMPERATURE_MMIO_SETTINGS_0 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83c0 + 64 + + Contains MMIO settings for sensor 2. + PLATFORM_TEMPERATURE_MMIO_SETTINGS_1 + Snapshot + 32 + 0 + 31 + + + reserved + PLATFORM_TEMPERATURE_MMIO_SETTINGS_1 + Snapshot + 32 + 32 + 63 + + + + Groupname 0x83c8 + 64 + + Big core clock ratio, in units of 100MHz. + AVG_FREQ_CORE0_3_RESERVED_83C8 + Snapshot + 8 + 0 + 7 + + + Big core clock ratio, in units of 100MHz. + AVG_FREQ_CORE0_3_RESERVED_83C8 + Snapshot + 8 + 8 + 15 + + + Big core clock ratio, in units of 100MHz. + AVG_FREQ_CORE0_3_RESERVED_83C8 + Snapshot + 8 + 16 + 23 + + + Big core clock ratio, in units of 100MHz. + AVG_FREQ_CORE0_3_RESERVED_83C8 + Snapshot + 8 + 24 + 31 + + + Atom core clock ratio, in units of 100MHz. + AVG_FREQ_CORE4_7_RESERVED_83CC + Snapshot + 8 + 32 + 39 + + + Atom core clock ratio, in units of 100MHz. + AVG_FREQ_CORE4_7_RESERVED_83CC + Snapshot + 8 + 40 + 47 + + + Atom core clock ratio, in units of 100MHz. + AVG_FREQ_CORE4_7_RESERVED_83CC + Snapshot + 8 + 48 + 55 + + + Atom core clock ratio, in units of 100MHz. + AVG_FREQ_CORE4_7_RESERVED_83CC + Snapshot + 8 + 56 + 63 + + + + Groupname 0x83d0 + 64 + + reserved + SMPL_RESERVED_0_83D0 + Snapshot + 64 + 0 + 63 + + + + Groupname 0x83d8 + 64 + + reserved + SMPL_RESERVED_1_to_69[0] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x83e0 + 64 + + reserved + SMPL_RESERVED_1_to_69[1] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x83e8 + 64 + + reserved + SMPL_RESERVED_1_to_69[2] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x83f0 + 64 + + reserved + SMPL_RESERVED_1_to_69[3] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x83f8 + 64 + + reserved + SMPL_RESERVED_1_to_69[4] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8400 + 64 + + reserved + SMPL_RESERVED_1_to_69[5] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8408 + 64 + + reserved + SMPL_RESERVED_1_to_69[6] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8410 + 64 + + reserved + SMPL_RESERVED_1_to_69[7] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8418 + 64 + + reserved + SMPL_RESERVED_1_to_69[8] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8420 + 64 + + reserved + SMPL_RESERVED_1_to_69[9] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8428 + 64 + + reserved + SMPL_RESERVED_1_to_69[10] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8430 + 64 + + reserved + SMPL_RESERVED_1_to_69[11] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8438 + 64 + + reserved + SMPL_RESERVED_1_to_69[12] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8440 + 64 + + reserved + SMPL_RESERVED_1_to_69[13] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8448 + 64 + + reserved + SMPL_RESERVED_1_to_69[14] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8450 + 64 + + reserved + SMPL_RESERVED_1_to_69[15] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8458 + 64 + + reserved + SMPL_RESERVED_1_to_69[16] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8460 + 64 + + reserved + SMPL_RESERVED_1_to_69[17] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8468 + 64 + + reserved + SMPL_RESERVED_1_to_69[18] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8470 + 64 + + reserved + SMPL_RESERVED_1_to_69[19] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8478 + 64 + + reserved + SMPL_RESERVED_1_to_69[20] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8480 + 64 + + reserved + SMPL_RESERVED_1_to_69[21] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8488 + 64 + + reserved + SMPL_RESERVED_1_to_69[22] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8490 + 64 + + reserved + SMPL_RESERVED_1_to_69[23] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8498 + 64 + + reserved + SMPL_RESERVED_1_to_69[24] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84a0 + 64 + + reserved + SMPL_RESERVED_1_to_69[25] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84a8 + 64 + + reserved + SMPL_RESERVED_1_to_69[26] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84b0 + 64 + + reserved + SMPL_RESERVED_1_to_69[27] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84b8 + 64 + + reserved + SMPL_RESERVED_1_to_69[28] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84c0 + 64 + + reserved + SMPL_RESERVED_1_to_69[29] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84c8 + 64 + + reserved + SMPL_RESERVED_1_to_69[30] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84d0 + 64 + + reserved + SMPL_RESERVED_1_to_69[31] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84d8 + 64 + + reserved + SMPL_RESERVED_1_to_69[32] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84e0 + 64 + + reserved + SMPL_RESERVED_1_to_69[33] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84e8 + 64 + + reserved + SMPL_RESERVED_1_to_69[34] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84f0 + 64 + + reserved + SMPL_RESERVED_1_to_69[35] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x84f8 + 64 + + reserved + SMPL_RESERVED_1_to_69[36] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8500 + 64 + + reserved + SMPL_RESERVED_1_to_69[37] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8508 + 64 + + reserved + SMPL_RESERVED_1_to_69[38] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8510 + 64 + + reserved + SMPL_RESERVED_1_to_69[39] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8518 + 64 + + reserved + SMPL_RESERVED_1_to_69[40] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8520 + 64 + + reserved + SMPL_RESERVED_1_to_69[41] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8528 + 64 + + reserved + SMPL_RESERVED_1_to_69[42] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8530 + 64 + + reserved + SMPL_RESERVED_1_to_69[43] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8538 + 64 + + reserved + SMPL_RESERVED_1_to_69[44] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8540 + 64 + + reserved + SMPL_RESERVED_1_to_69[45] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8548 + 64 + + reserved + SMPL_RESERVED_1_to_69[46] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8550 + 64 + + reserved + SMPL_RESERVED_1_to_69[47] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8558 + 64 + + reserved + SMPL_RESERVED_1_to_69[48] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8560 + 64 + + reserved + SMPL_RESERVED_1_to_69[49] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8568 + 64 + + reserved + SMPL_RESERVED_1_to_69[50] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8570 + 64 + + reserved + SMPL_RESERVED_1_to_69[51] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8578 + 64 + + reserved + SMPL_RESERVED_1_to_69[52] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8580 + 64 + + reserved + SMPL_RESERVED_1_to_69[53] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8588 + 64 + + reserved + SMPL_RESERVED_1_to_69[54] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8590 + 64 + + reserved + SMPL_RESERVED_1_to_69[55] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8598 + 64 + + reserved + SMPL_RESERVED_1_to_69[56] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85a0 + 64 + + reserved + SMPL_RESERVED_1_to_69[57] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85a8 + 64 + + reserved + SMPL_RESERVED_1_to_69[58] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85b0 + 64 + + reserved + SMPL_RESERVED_1_to_69[59] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85b8 + 64 + + reserved + SMPL_RESERVED_1_to_69[60] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85c0 + 64 + + reserved + SMPL_RESERVED_1_to_69[61] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85c8 + 64 + + reserved + SMPL_RESERVED_1_to_69[62] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85d0 + 64 + + reserved + SMPL_RESERVED_1_to_69[63] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85d8 + 64 + + reserved + SMPL_RESERVED_1_to_69[64] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85e0 + 64 + + reserved + SMPL_RESERVED_1_to_69[65] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85e8 + 64 + + reserved + SMPL_RESERVED_1_to_69[66] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85f0 + 64 + + reserved + SMPL_RESERVED_1_to_69[67] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x85f8 + 64 + + reserved + SMPL_RESERVED_1_to_69[68] + Snapshot + 64 + 0 + 63 + + + + Groupname 0x8600 + 64 + + slow limit THERM has limited performance for CCP0 + PERF_LIMIT_THERM_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8608 + 64 + + slow limit THERM has limited performance for CCP1 + PERF_LIMIT_THERM_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8610 + 64 + + slow limit THERM has limited performance for CCP2 + PERF_LIMIT_THERM_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x8618 + 64 + + slow limit THERM has limited performance for CCP3 + PERF_LIMIT_THERM_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8620 + 64 + + slow limit THERM has limited performance for CCP4 + PERF_LIMIT_THERM_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8628 + 64 + + slow limit THERM has limited performance for CLR + PERF_LIMIT_THERM_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8630 + 64 + + slow limit THERM has limited performance for GT. + PERF_LIMIT_THERM_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8638 + 64 + + slow limit THERM has limited performance for IPU. + PERF_LIMIT_THERM_IPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8640 + 64 + + slow limit THERM has limited performance for VPU. + PERF_LIMIT_THERM_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8648 + 64 + + slow limit THERM has limited performance for Media. + PERF_LIMIT_THERM_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8650 + 64 + + slow limit POWER has limited performance for CCP0 + PERF_LIMIT_POWER_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8658 + 64 + + slow limit POWER has limited performance for CCP1 + PERF_LIMIT_POWER_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8660 + 64 + + slow limit POWER has limited performance for CCP2 + PERF_LIMIT_POWER_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x8668 + 64 + + slow limit POWER has limited performance for CCP3 + PERF_LIMIT_POWER_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8670 + 64 + + slow limit POWER has limited performance for CCP4 + PERF_LIMIT_POWER_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8678 + 64 + + slow limit POWER has limited performance for CLR + PERF_LIMIT_POWER_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8680 + 64 + + slow limit POWER has limited performance for GT + PERF_LIMIT_POWER_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8688 + 64 + + slow limit POWER has limited performance for Media + PERF_LIMIT_POWER_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8690 + 64 + + slow limit POWER has limited performance for VPU + PERF_LIMIT_POWER_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8698 + 64 + + slow limit EDP has limited performance for CCP0 + PERF_LIMIT_EDP_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x86a0 + 64 + + slow limit EDP has limited performance for CCP1 + PERF_LIMIT_EDP_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x86a8 + 64 + + slow limit EDP has limited performance for CCP2 + PERF_LIMIT_EDP_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x86b0 + 64 + + slow limit EDP has limited performance for CCP3 + PERF_LIMIT_EDP_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x86b8 + 64 + + slow limit EDP has limited performance for CCP4 + PERF_LIMIT_EDP_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x86c0 + 64 + + slow limit EDP has limited performance for CLR + PERF_LIMIT_EDP_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86c8 + 64 + + slow limit EDP has limited performance for GT + PERF_LIMIT_EDP_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86d0 + 64 + + slow limit EDP has limited performance for Media + PERF_LIMIT_EDP_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86d8 + 64 + + slow limit EDP has limited performance for VPU + PERF_LIMIT_EDP_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x86e0 + 64 + + slow limit OTHER has limited performance for CCP0 + PERF_LIMIT_OTHER_CCP_RESIDENCY_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x86e8 + 64 + + slow limit OTHER has limited performance for CCP1 + PERF_LIMIT_OTHER_CCP_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x86f0 + 64 + + slow limit OTHER has limited performance for CCP2 + PERF_LIMIT_OTHER_CCP_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x86f8 + 64 + + slow limit OTHER has limited performance for CCP3 + PERF_LIMIT_OTHER_CCP_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x8700 + 64 + + slow limit OTHER has limited performance for CCP4 + PERF_LIMIT_OTHER_CCP_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x8708 + 64 + + slow limit OTHER has limited performance for CLR + PERF_LIMIT_OTHER_CLR_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8710 + 64 + + slow limit OTHER has limited performance for GT + PERF_LIMIT_OTHER_GT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8718 + 64 + + slow limit OTHER has limited performance for Media + PERF_LIMIT_OTHER_MEDIA_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8720 + 64 + + slow limit OTHER has limited performance for VPU + PERF_LIMIT_OTHER_VPU_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8728 + 64 + + prochot assertions. + PROCHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8730 + 64 + + VCCGT VR asserted VRHOT. + VCCIA_VRHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8738 + 64 + + VCCGT VR asserted VRHOT. + VCCGT_VRHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8740 + 64 + + VCCAUX VR asserted VRHOT. + VCCSA_VRHOT_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8748 + 64 + + SOC was PL3 limited + PL3_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8750 + 64 + + SOC was PL2 limited + PL2_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8758 + 64 + + SOC was PL1 limited + PL1_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8760 + 64 + + SOC was Psys PL3 limited + PSYS_PL3_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8768 + 64 + + SOC was Psys PL2 limited + PSYS_PL2_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8770 + 64 + + SOC was Psys PL1 limited + PSYS_PL1_LIMITED_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8778 + 64 + + GT RC6 + GT_RC6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8780 + 64 + + Media C6 residency + MEDIA_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8788 + 64 + + IPU IS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + IPU_IS_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8790 + 64 + + IPU PS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + IPU_PS_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8798 + 64 + + reserved + CNTR_RESERVED_8798 + Counter + 64 + 0 + 63 + + + + Groupname 0x87a0 + 64 + + reserved + CNTR_RESERVED_87A0 + Counter + 64 + 0 + 63 + + + + Groupname 0x87a8 + 64 + + reserved + CNTR_RESERVED_87A8 + Counter + 64 + 0 + 63 + + + + Groupname 0x87b0 + 64 + + reserved + CNTR_RESERVED_87B0 + Counter + 64 + 0 + 63 + + + + Groupname 0x87b8 + 64 + + reserved + CNTR_RESERVED_87B8 + Counter + 64 + 0 + 63 + + + + Groupname 0x87c0 + 64 + + reserved + CNTR_RESERVED_87C0 + Counter + 64 + 0 + 63 + + + + Groupname 0x87c8 + 64 + + C0 residency counter for Core0 + C0_RESIDENCY_CORE0 + Counter + 64 + 0 + 63 + + + + Groupname 0x87d0 + 64 + + C0 residency counter for Core1 + C0_RESIDENCY_CORE1 + Counter + 64 + 0 + 63 + + + + Groupname 0x87d8 + 64 + + C0 residency counter for Core2 + C0_RESIDENCY_CORE2 + Counter + 64 + 0 + 63 + + + + Groupname 0x87e0 + 64 + + C0 residency counter for Core3 + C0_RESIDENCY_CORE3 + Counter + 64 + 0 + 63 + + + + Groupname 0x87e8 + 64 + + C0 residency counter for Core4 + C0_RESIDENCY_CORE4 + Counter + 64 + 0 + 63 + + + + Groupname 0x87f0 + 64 + + C0 residency counter for Core5 + C0_RESIDENCY_CORE5 + Counter + 64 + 0 + 63 + + + + Groupname 0x87f8 + 64 + + C0 residency counter for Core6 + C0_RESIDENCY_CORE6 + Counter + 64 + 0 + 63 + + + + Groupname 0x8800 + 64 + + C0 residency counter for Core7 + C0_RESIDENCY_CORE7 + Counter + 64 + 0 + 63 + + + + Groupname 0x8808 + 64 + + Transition counter for when slow limit THERM has limited performance for CCP0 + PERF_LIMIT_THERM_CCP_COUNTER_0 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for CCP1 + PERF_LIMIT_THERM_CCP_COUNTER_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8810 + 64 + + Transition counter for when slow limit THERM has limited performance for CCP2 + PERF_LIMIT_THERM_CCP_COUNTER_2 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for CCP3 + PERF_LIMIT_THERM_CCP_COUNTER_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8818 + 64 + + Transition counter for when slow limit THERM has limited performance for CCP4 + PERF_LIMIT_THERM_CCP_COUNTER_4 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for CLR + PERF_LIMIT_THERM_CLR_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8820 + 64 + + Transition counter for when slow limit THERM has limited performance for GT + PERF_LIMIT_THERM_GT_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit THERM has limited performance for VPU + PERF_LIMIT_THERM_VPU_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8828 + 64 + + Transition counter for when slow limit THERM has limited performance for Media + PERF_LIMIT_THERM_MEDIA_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for CCP0 + PERF_LIMIT_POWER_CCP_COUNTER_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8830 + 64 + + Transition counter for when slow limit POWER has limited performance for CCP1 + PERF_LIMIT_POWER_CCP_COUNTER_1 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for CCP2 + PERF_LIMIT_POWER_CCP_COUNTER_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8838 + 64 + + Transition counter for when slow limit POWER has limited performance for CCP3 + PERF_LIMIT_POWER_CCP_COUNTER_3 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for CCP4 + PERF_LIMIT_POWER_CCP_COUNTER_4 + Counter + 32 + 32 + 63 + + + + Groupname 0x8840 + 64 + + Transition counter for when slow limit POWER has limited performance for CLR + PERF_LIMIT_POWER_CLR_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for GT + PERF_LIMIT_POWER_GT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8848 + 64 + + Transition counter for when slow limit POWER has limited performance for Media + PERF_LIMIT_POWER_MEDIA_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit POWER has limited performance for VPU + PERF_LIMIT_POWER_VPU_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8850 + 64 + + Transition counter for when slow limit EDP has limited performance for CCP0 + PERF_LIMIT_EDP_CCP_COUNTER_0 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for CCP1 + PERF_LIMIT_EDP_CCP_COUNTER_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8858 + 64 + + Transition counter for when slow limit EDP has limited performance for CCP2 + PERF_LIMIT_EDP_CCP_COUNTER_2 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for CCP3 + PERF_LIMIT_EDP_CCP_COUNTER_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8860 + 64 + + Transition counter for when slow limit EDP has limited performance for CCP4 + PERF_LIMIT_EDP_CCP_COUNTER_4 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for CLR + PERF_LIMIT_EDP_CLR_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8868 + 64 + + Transition counter for when slow limit EDP has limited performance for GT. + PERF_LIMIT_EDP_GT_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit EDP has limited performance for Media + PERF_LIMIT_EDP_MEDIA_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8870 + 64 + + Transition counter for when slow limit EDP has limited performance for VPU + PERF_LIMIT_EDP_VPU_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for CCP0 + PERF_LIMIT_OTHER_CCP_COUNTER_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8878 + 64 + + Transition counter for when slow limit OTHER has limited performance for CCP1 + PERF_LIMIT_OTHER_CCP_COUNTER_1 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for CCP2 + PERF_LIMIT_OTHER_CCP_COUNTER_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8880 + 64 + + Transition counter for when slow limit OTHER has limited performance for CCP3 + PERF_LIMIT_OTHER_CCP_COUNTER_3 + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for CCP4 + PERF_LIMIT_OTHER_CCP_COUNTER_4 + Counter + 32 + 32 + 63 + + + + Groupname 0x8888 + 64 + + Transition counter for when slow limit OTHER has limited performance for CLR. + PERF_LIMIT_OTHER_CLR_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for GT. + PERF_LIMIT_OTHER_GT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8890 + 64 + + Transition counter for when slow limit OTHER has limited performance for Media. + PERF_LIMIT_OTHER_MEDIA_COUNTER + Counter + 32 + 0 + 31 + + + Transition counter for when slow limit OTHER has limited performance for VPU. + PERF_LIMIT_OTHER_VPU_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8898 + 64 + + Energy reported by the Psys VR + PSYS_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x88a0 + 64 + + Total package energy including Compute+GT+PCH, (should be the same as MSR package_energy_status) + PACKAGE_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x88a8 + 64 + + IA VR energy (should be same as PRIMARY_PLANE_ENERGY_STATUS MSR) + VCCIA_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x88b0 + 64 + + GT VR energy (should be same as SECONDARY_PLANE_ENERGY_STATUS) + VCCGT_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x88b8 + 64 + + Energy estimated by Pcode using utilization factor from the VPU. Format is U18.14. https://docs.intel.com/documents/pm_doc/src/lnl/IP%20Integration/VPU%20PM%20HAS/VPU%20PM%20HAS.html#scalability-activity-factor + VPU_ENERGY + Counter + 64 + 0 + 63 + + + + Groupname 0x88c0 + 64 + + Total I/O read bandwidth for Display (VC1) + DISPLAY_IO_READ_BANDWIDTH + Counter + 64 + 0 + 63 + + + + Groupname 0x88c8 + 64 + + ReservedTotal I/O write bandwidth for display** NOT IMPLEMENTED ** + DISPLAY_IO_WRITE_BANDWIDTH + Counter + 64 + 0 + 63 + + + + Groupname 0x88d0 + 64 + + ReservedTotal display VC1 (non-coherent read) bandwidth.** NOT IMPLEMENTED **~same as DISPLAY_IO_READ_BANDWIDTH + DISPLAY_VC1_BANDWIDTH + Counter + 64 + 0 + 63 + + + + Groupname 0x88d8 + 64 + + Reserved. Moved to SoC die + IO_WRITE_BANDWIDTH_IP0_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x88e0 + 64 + + Reserved. Moved to SoC die + IO_READ_BANDWIDTH_IP0_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x88e8 + 64 + + Mufasa hit traffic + MUFASA_HIT_BW + Counter + 64 + 0 + 63 + + + + Groupname 0x88f0 + 64 + + Mufasa miss traffic + MUFASA_MISS_BW + Counter + 64 + 0 + 63 + + + + Groupname 0x88f8 + 64 + + HBO0 read and write traffic + HBO0_BW + Counter + 64 + 0 + 63 + + + + Groupname 0x8900 + 64 + + HBO1 read and write traffic + HBO1_BW + Counter + 64 + 0 + 63 + + + + Groupname 0x8908 + 64 + + SANTA (CCF) read traffic + SANTA_BW_READ + Counter + 64 + 0 + 63 + + + + Groupname 0x8910 + 64 + + SANTA (CCF) write traffic + SANTA_BW_WRITE + Counter + 64 + 0 + 63 + + + + Groupname 0x8918 + 64 + + IDI (Iceland) read traffic + IDIBR_BW_READ + Counter + 64 + 0 + 63 + + + + Groupname 0x8920 + 64 + + IDI (Iceland) write traffic + IDIBR_BW_WRITE + Counter + 64 + 0 + 63 + + + + Groupname 0x8928 + 64 + + Total MemSWITCH (previously I/O) read bandwidth. + NOC_BW_MEMSWITCH_READ + Counter + 64 + 0 + 63 + + + + Groupname 0x8930 + 64 + + Total MemSWITCH (previously I/O) write bandwidth. + NOC_BW_MEMSWITCH_WRITE + Counter + 64 + 0 + 63 + + + + Groupname 0x8938 + 64 + + Main NOC D2D read traffic + NOC_BW_D2D_READ + Counter + 64 + 0 + 63 + + + + Groupname 0x8940 + 64 + + Main NOC D2D write traffic + NOC_BW_D2D_WRITE + Counter + 64 + 0 + 63 + + + + Groupname 0x8948 + 64 + + Main NOC GT read traffic + NOC_BW_GT_READ + Counter + 64 + 0 + 63 + + + + Groupname 0x8950 + 64 + + Main NOC GT write traffic + NOC_BW_GT_WRITE + Counter + 64 + 0 + 63 + + + + Groupname 0x8958 + 64 + + HW counter disabled by default. Can be enabled through tap + NOC_BW_MEDIA_READ + Counter + 64 + 0 + 63 + + + + Groupname 0x8960 + 64 + + HW counter disabled by default. Can be enabled through tap + NOC_BW_MEDIA_WRITE + Counter + 64 + 0 + 63 + + + + Groupname 0x8968 + 64 + + HW counter disabled by default. Can be enabled through tap + NOC_BW_IPU_READ + Counter + 64 + 0 + 63 + + + + Groupname 0x8970 + 64 + + HW counter disabled by default. Can be enabled through tap + NOC_BW_IPU_WRITE + Counter + 64 + 0 + 63 + + + + Groupname 0x8978 + 64 + + CCE0 read and write traffic. HW counter disabled by default. Can be enabled through tap + NOC_BW_CCE0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8980 + 64 + + CCE1 read and write traffic. HW counter disabled by default. Can be enabled through tap + NOC_BW_CCE1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8988 + 64 + + ReservedDE has a joint counter for 2 linksValue is same as DISPLAY_IO_READ_BANDWIDTH + NOC_BW_DISP0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8990 + 64 + + ReservedDE has a joint counter for 2 linksValue is same as DISPLAY_IO_READ_BANDWIDTH + NOC_BW_DISP1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8998 + 64 + + Reserved. Covered in VPU_MEMORY_BW + NOC_BW_VPU0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89a0 + 64 + + Reserved. Covered in VPU_MEMORY_BW + NOC_BW_VPU1 + Counter + 64 + 0 + 63 + + + + Groupname 0x89a8 + 64 + + reserved + CNTR_RESERVED_89A8 + Counter + 64 + 0 + 63 + + + + Groupname 0x89b0 + 64 + + reserved + CNTR_RESERVED_89B0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89b8 + 64 + + reserved + CNTR_RESERVED_89B8 + Counter + 64 + 0 + 63 + + + + Groupname 0x89c0 + 64 + + reserved + CNTR_RESERVED_89C0 + Counter + 64 + 0 + 63 + + + + Groupname 0x89c8 + 64 + + prochot assertions. + PROCHOT_COUNTER + Counter + 32 + 0 + 31 + + + counts VCCIA VR asserted VRHOT. + VCCIA_VRHOT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x89d0 + 64 + + counts VCCGT VR asserted VRHOT. + VCCGT_VRHOT_COUNTER + Counter + 32 + 0 + 31 + + + counts VCCSA VR asserted VRHOT. + VCCSA_VRHOT_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x89d8 + 64 + + SOC was PL3 limited + PL3_LIMITED_COUNTER + Counter + 32 + 0 + 31 + + + SOC was PL2 limited + PL2_LIMITED_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x89e0 + 64 + + SOC was PL1 limited + PL1_LIMITED_COUNTER + Counter + 32 + 0 + 31 + + + SOC was Psys PL3 limited + PSYS_PL3_LIMITED_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x89e8 + 64 + + SOC was Psys PL2 limited + PSYS_PL2_LIMITED_COUNTER + Counter + 32 + 0 + 31 + + + SOC was Psys PL1 limited + PSYS_PL1_LIMITED_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x89f0 + 64 + + GT RC6 state transition counter + GT_RC6_COUNTER + Counter + 32 + 0 + 31 + + + Media C6 state transition counter + MEDIA_C6_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x89f8 + 64 + + IPU IS C6 state transition counter + IPU_IS_C6_COUNTER + Counter + 32 + 0 + 31 + + + IPU PS C6 state transition counter + IPU_PS_C6_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8a00 + 64 + + reserved + CNTR_RESERVED_8A00 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a08 + 64 + + reserved + CNTR_RESERVED_8A08 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a10 + 64 + + reserved + CNTR_RESERVED_8A10 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a18 + 64 + + This register increments every SBCLK cycle that MC0 is in self refresh + MC_IN_SR_COUNT_0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a20 + 64 + + This register increments every SBCLK cycle that MC1 is in self refresh + MC_IN_SR_COUNT_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a28 + 64 + + MC0 sends count Enable indications: 4 signals: two ChannelsSingle counter counts for both Channels, stands for channels 0-1Details:This register increments every SBCLK cycle that CKE of all ranks in a channel is low and all ranks are not yet in self-refresh or deep self-refresh. It will roll over to 0 when at the limit. Note: The counter will count CKE off cycles and increment even for an unpopulated channel. Software needs to detect if a channel is unpopulated (by seeing if MC_Init_State_0_0_0_MCHBAR.Rank_occupancy = 0x0) and not consume the value in this counter if channel is unpopulated.MC0_CKE_POWER_DOWN_COUNT = MC0_gv0+MC0_gv1+MC0_gv2+MC0_gv3 // stands for channels 0-1 + MC0_CKE_POWER_DOWN_COUNT + Counter + 64 + 0 + 63 + + + + Groupname 0x8a30 + 64 + + MC1 sends count Enable indications: 4 signals: two ChannelsSingle counter counts for both Channels, stands for channels 2-3Details:This register increments every SBCLK cycle that CKE of all ranks in a channel is low and all ranks are not yet in self-refresh or deep self-refresh. It will roll over to 0 when at the limit. Note: The counter will count CKE off cycles and increment even for an unpopulated channel. Software needs to detect if a channel is unpopulated (by seeing if MC_Init_State_0_0_0_MCHBAR.Rank_occupancy = 0x0) and not consume the value in this counter if channel is unpopulated.MC1_CKE_POWER_DOWN_COUNT = MC1_gv0+MC1_gv1+MC1_gv2+MC1_gv3 // stands for channels 2-3 + MC1_CKE_POWER_DOWN_COUNT + Counter + 64 + 0 + 63 + + + + Groupname 0x8a38 + 64 + + reserved + CNTR_RESERVED_8A38 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a40 + 64 + + reserved + CNTR_RESERVED_8A40 + Counter + 64 + 0 + 63 + + + + Groupname 0x8a48 + 64 + + increments the counter every sideband clock when CMI PLL is locked. + MC_ON_RATIO + Counter + 64 + 0 + 63 + + + + Groupname 0x8a50 + 64 + + increments the counter every sideband clock by '1' when CMI PLL is locked. Time_MC_ON = counter * SBclk_period + MC_ON_TIME + Counter + 64 + 0 + 63 + + + + Groupname 0x8a58 + 64 + + Counts total MC writes. Virtual bandwidth counter based on PWM_WRDATA bulkcr sample.i.e TOTAL_WRITE_BANDWIDTH = total PWM_WRDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + TOTAL_WRITE_BANDWIDTH + Counter + 64 + 0 + 63 + + + + Groupname 0x8a60 + 64 + + Counts total MC reads. Virtual bandwidth counter based on PWM_RDDATA bulkcr sample.i.e TOTAL_READ_BANDWIDTH = total PWM_RDDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + TOTAL_READ_BANDWIDTH + Counter + 64 + 0 + 63 + + + + Groupname 0x8a68 + 64 + + The counter value is incremented as a function of the number of cores that reside in C0 and active. If N cores are simultaneously in C0, then the number of "clock ticks" that are incremented is N. Counts in XTAL units. Should be same as MSR ANY_CORE_C0 0x659. + IO_PKG_IA_C0_ANY_SUM + Counter + 64 + 0 + 63 + + + + Groupname 0x8a70 + 64 + + This counter increments whenever GT slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. Should be same as MSR ANY_GFXE_C0 0x65a + IO_PKG_GT_C0_ANY + Counter + 64 + 0 + 63 + + + + Groupname 0x8a78 + 64 + + This counter increments whenever GT slices or unslices are active and in C0 state and in overlap with one of the IA cores that is active and in C0. Counts in XTAL units. Should be same as MSR CORE_GFXE_OVERLAP_C0 0x65b + IO_PKG_GT_AND_IA_OVERLAP + Counter + 64 + 0 + 63 + + + + Groupname 0x8a80 + 64 + + Follow exactly the IO_PKG_GT_C0_ANY_SLICE. The only change is that they do +N (GT ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock.PKG_GT_C0_ANY_SLICE Counts clocks that any GT slice is active. Reference clock is XTAL. + IO_PKG_GT_C0_ANY_RATIO + Counter + 64 + 0 + 63 + + + + Groupname 0x8a88 + 64 + + This counter increments whenever MEDIA slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. + IO_PKG_MEDIA_C0_ANY + Counter + 64 + 0 + 63 + + + + Groupname 0x8a90 + 64 + + Follow exactly the PKG_MEDIA_C0_ANY_SLICE. The only change is that they do +N (media ratio) instead of +1 on the relevant clock edge.PKG_MEDIA_C0_ANY_SLICE Counts clocks that any Media slice is active.Counter rate is in Xtal Clock. + IO_PKG_MEDIA_C0_ANY_RATIO + Counter + 64 + 0 + 63 + + + + Groupname 0x8a98 + 64 + + follow exactly the PKG_IA_C0_ANYThe only change is that they do +N (Max IA ratio) instead of +1 on the relevant clock edge and conditions (while any LP_AT_C0[i]=1):PCU_CR_PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU += PKG_IA_C0_CURRENT_RATIO.RATIOPKG_IA_C0_CURRENT_RATIO.RATIO = MAX(IO_WP_CV_P_STATE[IA_RATIO]).Reference clock is XTAL.More details [here](https://docs.intel.com/documents/pm_doc/src/LNL/MAS/CCP_PM/ccp_pm_mas.html#punit-counters) + IO_PKG_IA_C0_ANY_RATIO + Counter + 64 + 0 + 63 + + + + Groupname 0x8aa0 + 64 + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 0. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0 + Counter + 32 + 0 + 31 + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 1. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8aa8 + 64 + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 2. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2 + Counter + 32 + 0 + 31 + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 0. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0_MMIO + Counter + 32 + 32 + 63 + + + + Groupname 0x8ab0 + 64 + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 1. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1_MMIO + Counter + 32 + 0 + 31 + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 2. + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2_MMIO + Counter + 32 + 32 + 63 + + + + Groupname 0x8ab8 + 64 + + Time in state counter + IPU_PARTIAL_SLEEP_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8ac0 + 64 + + Time in state counter + VPU_PARTIAL_SLEEP_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8ac8 + 64 + + state transition counter + IPU_PARTIAL_SLEEP_ENTRY_COUNTERS + Counter + 32 + 0 + 31 + + + state transition counter + VPU_PARTIAL_SLEEP_ENTRY_COUNTERS + Counter + 32 + 32 + 63 + + + + Groupname 0x8ad0 + 64 + + reserved + CNTR_RESERVED_0_8AD0 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ad8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ae0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ae8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8af0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8af8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b00 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b08 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b10 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b18 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b20 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b28 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b30 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b38 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b40 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b48 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b50 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b58 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b60 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b68 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b70 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b78 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b80 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b88 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b90 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8b98 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ba0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ba8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bb0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bb8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bc0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bc8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bd0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bd8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8be0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8be8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bf0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8bf8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c00 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c08 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c10 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c18 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c20 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c28 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c30 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c38 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c40 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c48 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c50 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c58 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c60 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c68 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c70 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c78 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c80 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c88 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c90 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8c98 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ca0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ca8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cb0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cb8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cc0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cc8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cd0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cd8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ce0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ce8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cf0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8cf8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8d00 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8d08 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 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Counter + 64 + 0 + 63 + + + + Groupname 0x8e18 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e20 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e28 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e30 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e38 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e40 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e48 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e50 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e58 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e60 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e68 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e70 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e78 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e80 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e88 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e90 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8e98 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ea0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ea8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8eb0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8eb8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ec0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ec8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ed0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ed8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ee0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ee8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ef0 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ef8 + 64 + + reserved + CNTR_RESERVED_1_to_133 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f00 + 64 + + Average DDR BW over a time interval + VPU_MEMORY_BW + Counter + 32 + 0 + 31 + + + Cycle count of amount of times VPU is in D0 active state + VPU_D0_ACTIVE_RESIDENCY + Counter + 32 + 32 + 63 + + + + Groupname 0x8f08 + 64 + + Number of times VPU enters into D0 active state + VPU_D0_ACTIVE_ENTRY_COUNT + Counter + 32 + 0 + 31 + + + Cycle count of amount of time VPU is in D0I2 active state + VPU_D0i2_ACTIVE_RESIDENCY + Counter + 32 + 32 + 63 + + + + Groupname 0x8f10 + 64 + + Cycle count of amount of time VPU is in D0I2 Idle state + VPU_D0i2_IDLE_RESIDENCY + Counter + 32 + 0 + 31 + + + Number of times VPU enters into D0I2 active state + VPU_D0i2_ACTIVE_ENTRY_COUNT + Counter + 32 + 32 + 63 + + + + Groupname 0x8f18 + 64 + + Number of times VPU enters into D0I2 Idle state + VPU_D0i2_IDLE_ENTRY_COUNT + Counter + 32 + 0 + 31 + + + Overall number of cycles for a context in RealTime priority + VPU_REALTIME_PRIORITY_CONTEXT_CYCLE_COUNT + Counter + 32 + 32 + 63 + + + + Groupname 0x8f20 + 64 + + Overall number of cycles for a context in normal priority + VPU_NORMAL_PRIORITY_CONTEXT_CYCLE_COUNT + Counter + 32 + 0 + 31 + + + Overall number of cycles for a context in focus priority + VPU_FOCUS_PRIORITY_CONTEXT_CYCLE_COUNT + Counter + 32 + 32 + 63 + + + + Groupname 0x8f28 + 64 + + Overall number of cycles for a context in background priority + VPU_IDLE_PRIORITY_CONTEXT_CYCLE_COUNT + Counter + 32 + 0 + 31 + + + Current value of the FRC (fixed frequency) when data is reported out - VPU fixed frequency FRC(free running counter) value + VPU_FIXED_FREQ_FRC_VAL + Counter + 32 + 32 + 63 + + + + Groupname 0x8f30 + 64 + + Current value of the FRC (variable frequeny) when data is reported out. - VPU variable frequency (DVFS clock) FRC (free running counter) value + VPU_VAR_FREQ_FRC_VAL + Counter + 32 + 0 + 31 + + + reserved + VPU_RSVD0_8F34 + Counter + 32 + 32 + 63 + + + + Groupname 0x8f38 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f40 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f48 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f50 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f58 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f60 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f68 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f70 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f78 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f80 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f88 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f90 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8f98 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fa0 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fa8 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fb0 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fb8 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fc0 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fc8 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fd0 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fd8 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fe0 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8fe8 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ff0 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + + Groupname 0x8ff8 + 64 + + reserved + VPU_RSVD_1_to_25 + Counter + 64 + 0 + 63 + + + \ No newline at end of file diff --git a/xml/LNL/0/lnla0_0r5_aggregator_interface.xml b/xml/LNL/0/lnla0_0r5_aggregator_interface.xml new file mode 100644 index 0000000..bfef695 --- /dev/null +++ b/xml/LNL/0/lnla0_0r5_aggregator_interface.xml @@ -0,0 +1,7055 @@ + + + + + + + + + float + + parameter_0 + + $parameter_0 / ( 38.4 * 1e6 ) + + + float + + parameter_0 + + $parameter_0 * 0.0025 + + + float + + parameter_0 + + $parameter_0 * 64 / 1e6 + + + float + + parameter_0 + + $parameter_0 / 1e6 + + + float + + parameter_0 + + $parameter_0 * 32 / 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + ( ( ( $parameter_0 | ( ~ $parameter_0 + 1 ) ) >> 7 ) & 0x1 ) * ( 49 + $parameter_0 ) * 0.005 + + + integer + + parameter_0 + + ( ( ( 1 - ( ( $parameter_0 >> 7 ) & 0x1 ) ) * ( $parameter_0 & 0xff ) ) - ( ( ( $parameter_0 >> 7 ) & 0x1 ) * ( ( ( $parameter_0 & 0x7f ) ^ 0x7f ) + 1 ) ) ) + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + ( $parameter_0 & 0xff ) / ( 2**7 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x3ff ) / ( 2**3 ) + + + float + + parameter_0 + + $parameter_0 * 0.1 + + + float + + parameter_0 + + $parameter_0 * 0.01667 + + + float + + parameter_0 + + $parameter_0 * 0.025 + + + float + + parameter_0 + + $parameter_0 * 0.033 + + + float + + parameter_0 + + $parameter_0 * 0.05 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**8 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x1ff ) / ( 2**8 ) + + + float + + parameter_0 + + $parameter_0 * 100 / 128 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**15 ) + + + float + + parameter_0 + + $parameter_0 * 0.002 + + + float + + parameter_0 + + ( $parameter_0 & 0x7ff ) / ( 2**2 ) + + + float + + parameter_0 + + ( $parameter_0 & 0xffffffff ) / ( 2**14 ) + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + $parameter_0 * 64 + + + float + + parameter_0 + + $parameter_0 * 0.025 * 33.33 + + + float + + parameter_0 + + $parameter_0 / 400 * 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 * 1000 + + + float + + parameter_0 + + $parameter_0 / 32 + + + float + + parameter_0 + + $parameter_0 * 1024 / 1e6 + + + float + + parameter_0 + + $parameter_0 / ( 19.2 * 1e6 ) + + + integer + + parameter_0 + + $parameter_0 + + + + LNL + LNL M/P PMT Telemetry aggregator 0 samples definition and transformation rules + 0x03072005 + Public + 10 + 2024-09-18 + + + Local Revision ID for this product (revision of the xml) + Snapshot + + + Container_0 + LOCAL_REVISION_ID + + + passthru + + + 1' for Fixed block telemetry ID, '0' for rest. Default is '0' + Snapshot + + + Container_0 + FIXED_TELEMETRY_IDENTIFIER + + + passthru + + + Product ID= 22 | TGLUY= 23 | TGLH= 24 | TGLS= 79 | ADL-P= 80 | ADL-S= 90 | RPL= 91 | RPL-P= 92 | RPL-S= 103 | MTL-M= 104 | MTL-P= 105 | MTL-S= 106 | ARL= 114 | LNL-M= 134 | PTL-P= 135 | PTL-H + Snapshot + + + Container_0 + PRODUCT_ID + + + passthru + + + source id for data provider + Snapshot + + + Container_0 + RECORD_TYPE + + + passthru + + + reserved + Snapshot + + + Container_0 + reserved + + + passthru + + + Represents the clock rate of the XTAL on this silicon.= 0 | 24MHz= 1 | 19.2MHz= 2 | 38.4MHz= 3 | 25MHz + Snapshot + + + Container_0 + XTAL_FREQ + + + passthru + + + reserved + Snapshot + + + Container_0 + reserved_1 + + + passthru + + + ICCMAX level for the IPU's IS system + Snapshot + + + Container_1 + IS_ICCMAX_LEVEL + + + ipu_icc + + + ICCMAX level for the IPU's PS system + Snapshot + + + Container_1 + PS_ICCMAX_LEVEL + + + ipu_icc + + + Processing system frequency. Frequency is ratio*25MHz. Zero means power down. + Snapshot + + + Container_1 + PS_FREQ + + + ratio_25 + + + IS system frequency. Frequency is ratio*16MHz. Zero means power down. + Snapshot + + + Container_1 + IS_FREQ + + + ratio_16 + + + IS voltage requirement + Snapshot + + + Container_1 + IS_VOLTAGE + + + U8.1.7 + + + PS voltage requirement + Snapshot + + + Container_1 + PS_VOLTAGE + + + U8.1.7 + + + reserved + Snapshot + + + Container_1 + reserved_2 + + + passthru + + + Qclk frequency for Mem SS in units of 33MHz + Snapshot + + + Container_2 + MEMSS_FREQ + + + ratio_33 + + + Mem SS voltage requirement + Snapshot + + + Container_2 + MEMSS_VOLTAGE + + + U8.1.7 + + + CDCLK frequency for display + Snapshot + + + Container_2 + DISP_FREQ + + + clk_freq + + + Display voltage requirement + Snapshot + + + Container_2 + DISP_VOLTAGE + + + U8.1.7 + + + NCLK frequency + Snapshot + + + Container_2 + MAIN_NOC_FREQ + + + ratio_50 + + + NCLK voltage requirement + Snapshot + + + Container_2 + MAIN_NOC_VOLTAGE + + + U8.1.7 + + + D2D frequency in units of 50MHz + Snapshot + + + Container_2 + D2D_FREQ + + + ratio_50 + + + reserved + Snapshot + + + Container_2 + reserved_3 + + + passthru + + + VPU frequency in units of 50MHz + Snapshot + + + Container_3 + FREQ + + + ratio_50 + + + VPU voltage requirement + Snapshot + + + Container_3 + VOLTAGE + + + U8.1.7 + + + Indicates the tile configuration internal to VPU + Snapshot + + + Container_3 + TILE_CONFIG + + + passthru + + + reserved + Snapshot + + + Container_3 + reserved_4 + + + passthru + + + Media voltage requirement + Snapshot + + + Container_3 + VOLTAGE_1 + + + U8.1.7 + + + Media ratio in units of 50MHz + Snapshot + + + Container_3 + FREQ_1 + + + ratio_50 + + + Reserved + Snapshot + + + Container_3 + reserved_5 + + + passthru + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + VOLTAGE_2 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + CURRENT + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + PS_OVERRIDE + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_4 + FREQ_2 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + VOLTAGE_3 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + CURRENT_1 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_4 + PS_OVERRIDE_1 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_4 + FREQ_3 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + VOLTAGE_4 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + CURRENT_2 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + PS_OVERRIDE_2 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_5 + FREQ_4 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + VOLTAGE_5 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + CURRENT_3 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_5 + PS_OVERRIDE_3 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_5 + FREQ_5 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + VOLTAGE_6 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + CURRENT_4 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + PS_OVERRIDE_4 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_6 + FREQ_6 + + + ratio_100 + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + VOLTAGE_7 + + + wp_volts + + + Current, in U7.3 amps. This is the maximal virus current at state. valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + CURRENT_5 + + + U10.7.3 + + + Internal VR power state (PS). valid only if IA modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_6 + PS_OVERRIDE_5 + + + passthru + + + IA Module clock ratio, in units of 100MHz. + Snapshot + + + Container_6 + FREQ_7 + + + ratio_100 + + + reserved + Snapshot + + + Container_7 + rsvd + + + passthru + + + Voltage, to be sent as-is to Internal VR, linear, in steps of 2.5mV. valid only if GT modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_7 + VOLTAGE_8 + + + wp_volts + + + Reserved + Snapshot + + + Container_7 + reserved_6 + + + passthru + + + Internal VR power state (PS). valid only if GT modules are supplied by internal VR, otherwise value should be ignored. + Snapshot + + + Container_7 + PS_OVERRIDE_6 + + + passthru + + + GT clock ratio, in units of 50MHz + Snapshot + + + Container_7 + FREQ_8 + + + ratio_50 + + + Indicates systolic config + Snapshot + + + Container_8 + SYSTOLIC + + + passthru + + + EUs active + Snapshot + + + Container_8 + EU_COUNT + + + passthru + + + unused in LNL + Snapshot + + + Container_8 + MEDIA_ENGINE_COUNT + + + passthru + + + subslice count + Snapshot + + + Container_8 + SUBSLICE_COUNT + + + passthru + + + active slices in GT + Snapshot + + + Container_8 + RENDER_SLICE_COUNT + + + passthru + + + reserved + Snapshot + + + Container_8 + reserved_7 + + + passthru + + + Graphics Security Controller (GSC). 0 - GSC is power-gated. 1 - GSC is not power-gated. + Snapshot + + + Container_8 + GSC + + + passthru + + + Total number of active media engines in Media. Inactive means power-gated, that is, no leakage. The range in LNL is 0-1, since LNL Media has only 1 slice. + Snapshot + + + Container_8 + MEDIA_SLICE_COUNT + + + passthru + + + Reserved + Snapshot + + + Container_8 + reserved_8 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_9 + VID_IA + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_9 + PS_IA + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_9 + FAST_IA + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_9 + DECAY_IA + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_9 + VID_GT + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_9 + PS_GT + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_9 + FAST_GT + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_9 + DECAY_GT + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_9 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_9 + VID_SA + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_9 + PS_SA + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_9 + FAST_SA + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_9 + DECAY_SA + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_9 + VID_ATOM + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_9 + PS_ATOM + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_9 + FAST_ATOM + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_9 + DECAY_ATOM + + + passthru + + + reserved + Snapshot + + + Container_9 + reserved_10 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_10 + VID_L2 + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_10 + PS_L2 + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_10 + FAST_L2 + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_10 + DECAY_L2 + + + passthru + + + VID Code. Encoding is based on SVID spec. + Snapshot + + + Container_10 + VID_DDQ + + + vid + + + VR Power state.0: PS0 - 01: PS1 - 12: PS2 - 23: PS3 - 34: PS4 - 4 + Snapshot + + + Container_10 + PS_DDQ + + + passthru + + + Issue FAST ramp, instead of SLOW ramp. + Snapshot + + + Container_10 + FAST_DDQ + + + passthru + + + Issue DECAY ramp, instead of SLOW ramp. Only going down. + Snapshot + + + Container_10 + DECAY_DDQ + + + passthru + + + reserved + Snapshot + + + Container_10 + reserved_11 + + + passthru + + + last SVID0 VR current reading - translated IMON version for VCCIA, in amps. U16.8.8 + Snapshot + + + Container_10 + ICC_IA + + + U16.8.8 + + + last SVID1 VR current reading - translated IMON version for VCCGT, in amps. U16.8.8 + Snapshot + + + Container_10 + ICC_GT + + + U16.8.8 + + + last SVID2 VR current reading - translated IMON version for VCCSA, in amps. U16.8.8 + Snapshot + + + Container_11 + ICC_SA + + + U16.8.8 + + + last SVID3 VR current reading - translated IMON version for VCCATOM, in amps. U16.8.8 + Snapshot + + + Container_11 + ICC_ATOM + + + U16.8.8 + + + last SVID4 VR current reading - translated IMON version for VCCL2, in amps. U16.8.8 + Snapshot + + + Container_11 + ICC_L2 + + + U16.8.8 + + + last SVID5 VR current reading - translated IMON version for VCCL2, in amps. U16.8.8 + Snapshot + + + Container_11 + ICC_DDQ + + + U16.8.8 + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_12 + CORE0 + + + passthru + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_12 + CORE1 + + + passthru + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_12 + CORE2 + + + passthru + + + IA Core C-state of BigCore0: C01: C13: C67: CRST + Snapshot + + + Container_12 + CORE3 + + + passthru + + + IA Core C-state of Atom core0: C01: C13: C67: CRST + Snapshot + + + Container_12 + Atom_Module0 + + + passthru + + + LLC/Ring C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + Snapshot + + + Container_12 + Cluster0 + + + passthru + + + Iceland cluster C-state0: C0 - 01: C2 - 12: C3 - 23: C6 - 37: RST - 7 + Snapshot + + + Container_12 + Cluster1 + + + passthru + + + GT RC-state0: C01: C13: C67: CRST + Snapshot + + + Container_12 + GT + + + passthru + + + reserved + Snapshot + + + Container_12 + reserved_12 + + + passthru + + + CDYN level granted that CORE0 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_13 + CORE0_1 + + + passthru + + + CDYN level granted that CORE1 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_13 + CORE1_1 + + + passthru + + + CDYN level granted that CORE2 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_13 + CORE2_1 + + + passthru + + + CDYN level granted that CORE3 can use.Grant short period protected CDYN index (factor index over the CDYN_INDEX) Short period is 64 core cycles in BigCore Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.SHORT_CDYN_INDEX + Snapshot + + + Container_13 + CORE3_1 + + + passthru + + + CDYN level granted that Atom module0 can use.Grant long period protected CDYN index (factor index over the CDYN_INDEX) Long period is up to 100-200ns in Atom Following the Electrical request.Taken from PCU_CR_WP_RV_IA_CCP_WP3.LONG_CDYN_INDEX + Snapshot + + + Container_13 + MODULE0 + + + passthru + + + reserved + Snapshot + + + Container_13 + reserved_13 + + + passthru + + + Current PCH temperature + Snapshot + + + Container_14 + PCH_TEMP + + + S8.7.0 + + + Current reading from System Agent "always on" temperature sensor + Snapshot + + + Container_14 + SA_TEMP + + + S8.7.0 + + + Current reading from IPU subsystem temperature sensor + Snapshot + + + Container_14 + IPU_TEMP + + + S8.7.0 + + + Current reading from Display subsystem temperature sensor + Snapshot + + + Container_14 + DE_TEMP + + + S8.7.0 + + + Current reading from VPU subsystem temperature sensor + Snapshot + + + Container_14 + VPU_TEMP + + + S8.7.0 + + + Current reading from Media subsystem temperature sensor + Snapshot + + + Container_14 + Media_TEMP + + + S8.7.0 + + + reserved + Snapshot + + + Container_14 + reserved_14 + + + passthru + + + Min temp across the core + Snapshot + + + Container_15 + CCP0_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_15 + CCP0_MAX + + + S8.7.0 + + + Min temp across the core + Snapshot + + + Container_15 + CCP1_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_15 + CCP1_MAX + + + S8.7.0 + + + Min temp across the core + Snapshot + + + Container_15 + CCP2_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_15 + CCP2_MAX + + + S8.7.0 + + + Min temp across the core + Snapshot + + + Container_15 + CCP3_MIN + + + S8.7.0 + + + Max temp across the core + Snapshot + + + Container_15 + CCP3_MAX + + + S8.7.0 + + + Min temp across the atom module + Snapshot + + + Container_16 + CCP4_MIN + + + S8.7.0 + + + Max temp across the atom module + Snapshot + + + Container_16 + CCP4_MAX + + + S8.7.0 + + + reserved + Snapshot + + + Container_16 + reserved_15 + + + passthru + + + LLC Min temp + Snapshot + + + Container_16 + LLC_MIN + + + S8.7.0 + + + LLC Max temp + Snapshot + + + Container_16 + LLC_MAX + + + S8.7.0 + + + Graphics Min temp + Snapshot + + + Container_16 + GT_MIN + + + S8.7.0 + + + Graphics Max temp + Snapshot + + + Container_16 + GT_MAX + + + S8.7.0 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_17 + CORE0_2 + + + U9.1.8 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_17 + CORE1_2 + + + U9.1.8 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_17 + CORE2_2 + + + U9.1.8 + + + Current big core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_17 + CORE3_2 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE4 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE5 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE6 + + + U9.1.8 + + + Current atom core scalability measurement. Calculated as unstalled clocks divided by total active clocks. + Snapshot + + + Container_18 + CORE7 + + + U9.1.8 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_0 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_1 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_2 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_3 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_4 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_5 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_6 + + + ratio_100 + + + P_alpha calculation. This represents the maximum allowed clock frequency on that core. + Snapshot + + + Container_19 + RATIO_7 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_0_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_1_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_2_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_3_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_4_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_5_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_6_1 + + + ratio_100 + + + Current autonomous frequency target for that IA Core + Snapshot + + + Container_20 + RATIO_7_1 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_0 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_1 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_2 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_3 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_4 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_5 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_6 + + + ratio_100 + + + Current efficient frequency target for that IA Core + Snapshot + + + Container_21 + IA_PE_7 + + + ratio_100 + + + Current GT Efficient P-state (used as the floor for autonomous control) + Snapshot + + + Container_22 + GT_PE + + + ratio_100 + + + reserved + Snapshot + + + Container_22 + reserved_16 + + + passthru + + + Temperature of PECI sensor in 1/32 DegC + Snapshot + + + Container_23 + SENSOR_0 + + + platform_temperature + + + Temperature of PECI sensor in 1/32 DegC + Snapshot + + + Container_23 + SENSOR_1 + + + platform_temperature + + + Temperature of PECI sensor in 1/32 DegC + Snapshot + + + Container_23 + SENSOR_2 + + + platform_temperature + + + reserved + Snapshot + + + Container_23 + reserved_17 + + + platform_temperature + + + Contains EC settings for sensor 0. + Snapshot + + + Container_24 + EC_SETTINGS_SENSOR_0 + + + passthru + + + Contains EC settings for sensor 1. + Snapshot + + + Container_24 + EC_SETTINGS_SENSOR_1 + + + passthru + + + Contains EC settings for sensor 2. + Snapshot + + + Container_25 + EC_SETTINGS_SENSOR_2 + + + passthru + + + reserved + Snapshot + + + Container_25 + rsvd_1 + + + passthru + + + Contains MMIO settings for sensor 0. + Snapshot + + + Container_26 + MMIO_SETTINGS_SENSOR_0 + + + passthru + + + Contains MMIO settings for sensor 1. + Snapshot + + + Container_26 + MMIO_SETTINGS_SENSOR_1 + + + passthru + + + Contains MMIO settings for sensor 2. + Snapshot + + + Container_27 + MMIO_SETTINGS_SENSOR_2 + + + passthru + + + reserved + Snapshot + + + Container_27 + rsvd_2 + + + passthru + + + Big core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE0 + + + ratio_100 + + + Big core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE1 + + + ratio_100 + + + Big core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE2 + + + ratio_100 + + + Big core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE3 + + + ratio_100 + + + Atom core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE4 + + + ratio_100 + + + Atom core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE5 + + + ratio_100 + + + Atom core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE6 + + + ratio_100 + + + Atom core clock ratio, in units of 100MHz. + Snapshot + + + Container_28 + FREQ_CORE7 + + + ratio_100 + + + reserved + Snapshot + + + Container_29 + rsvd_3 + + + passthru + + + reserved + Snapshot + + + Container_30 + rsvd_4 + + + passthru + + + reserved + Snapshot + + + Container_31 + rsvd_5 + + + passthru + + + reserved + Snapshot + + + Container_32 + rsvd_6 + + + passthru + + + reserved + Snapshot + + + Container_33 + rsvd_7 + + + passthru + + + reserved + Snapshot + + + Container_34 + rsvd_8 + + + passthru + + + reserved + Snapshot + + + Container_35 + rsvd_9 + + + passthru + + + reserved + Snapshot + + + Container_36 + rsvd_10 + + + passthru + + + reserved + Snapshot + + + Container_37 + rsvd_11 + + + passthru + + + reserved + Snapshot + + + Container_38 + rsvd_12 + + + passthru + + + reserved + Snapshot + + + Container_39 + rsvd_13 + + + passthru + + + reserved + Snapshot + + + Container_40 + rsvd_14 + + + passthru + + + reserved + Snapshot + + + Container_41 + rsvd_15 + + + passthru + + + reserved + Snapshot + + + Container_42 + rsvd_16 + + + passthru + + + reserved + Snapshot + + + Container_43 + rsvd_17 + + + passthru + + + reserved + Snapshot + + + Container_44 + rsvd_18 + + + passthru + + + reserved + Snapshot + + + Container_45 + rsvd_19 + + + passthru + + + reserved + Snapshot + + + Container_46 + rsvd_20 + + + passthru + + + reserved + Snapshot + + + Container_47 + rsvd_21 + + + passthru + + + reserved + Snapshot + + + Container_48 + rsvd_22 + + + passthru + + + reserved + Snapshot + + + Container_49 + rsvd_23 + + + passthru + + + reserved + Snapshot + + + Container_50 + rsvd_24 + + + passthru + + + reserved + Snapshot + + + Container_51 + rsvd_25 + + + passthru + + + reserved + Snapshot + + + Container_52 + rsvd_26 + + + passthru + + + reserved + Snapshot + + + Container_53 + rsvd_27 + + + passthru + + + reserved + Snapshot + + + Container_54 + rsvd_28 + + + passthru + + + reserved + Snapshot + + + Container_55 + rsvd_29 + + + passthru + + + reserved + Snapshot + + + Container_56 + rsvd_30 + + + passthru + + + reserved + Snapshot + + + Container_57 + rsvd_31 + + + passthru + + + reserved + Snapshot + + + Container_58 + rsvd_32 + + + passthru + + + reserved + Snapshot + + + Container_59 + rsvd_33 + + + passthru + + + reserved + Snapshot + + + Container_60 + rsvd_34 + + + passthru + + + reserved + Snapshot + + + Container_61 + rsvd_35 + + + passthru + + + reserved + Snapshot + + + Container_62 + rsvd_36 + + + passthru + + + reserved + Snapshot + + + Container_63 + rsvd_37 + + + passthru + + + reserved + Snapshot + + + Container_64 + rsvd_38 + + + passthru + + + reserved + Snapshot + + + Container_65 + rsvd_39 + + + passthru + + + reserved + Snapshot + + + Container_66 + rsvd_40 + + + passthru + + + reserved + Snapshot + + + Container_67 + rsvd_41 + + + passthru + + + reserved + Snapshot + + + Container_68 + rsvd_42 + + + passthru + + + reserved + Snapshot + + + Container_69 + rsvd_43 + + + passthru + + + reserved + Snapshot + + + Container_70 + rsvd_44 + + + passthru + + + reserved + Snapshot + + + Container_71 + rsvd_45 + + + passthru + + + reserved + Snapshot + + + Container_72 + rsvd_46 + + + passthru + + + reserved + Snapshot + + + Container_73 + rsvd_47 + + + passthru + + + reserved + Snapshot + + + Container_74 + rsvd_48 + + + passthru + + + reserved + Snapshot + + + Container_75 + rsvd_49 + + + passthru + + + reserved + Snapshot + + + Container_76 + rsvd_50 + + + passthru + + + reserved + Snapshot + + + Container_77 + rsvd_51 + + + passthru + + + reserved + Snapshot + + + Container_78 + rsvd_52 + + + passthru + + + reserved + Snapshot + + + Container_79 + rsvd_53 + + + passthru + + + reserved + Snapshot + + + Container_80 + rsvd_54 + + + passthru + + + reserved + Snapshot + + + Container_81 + rsvd_55 + + + passthru + + + reserved + Snapshot + + + Container_82 + rsvd_56 + + + passthru + + + reserved + Snapshot + + + Container_83 + rsvd_57 + + + passthru + + + reserved + Snapshot + + + Container_84 + rsvd_58 + + + passthru + + + reserved + Snapshot + + + Container_85 + rsvd_59 + + + passthru + + + reserved + Snapshot + + + Container_86 + rsvd_60 + + + passthru + + + reserved + Snapshot + + + Container_87 + rsvd_61 + + + passthru + + + reserved + Snapshot + + + Container_88 + rsvd_62 + + + passthru + + + reserved + Snapshot + + + Container_89 + rsvd_63 + + + passthru + + + reserved + Snapshot + + + Container_90 + rsvd_64 + + + passthru + + + reserved + Snapshot + + + Container_91 + rsvd_65 + + + passthru + + + reserved + Snapshot + + + Container_92 + rsvd_66 + + + passthru + + + reserved + Snapshot + + + Container_93 + rsvd_67 + + + passthru + + + reserved + Snapshot + + + Container_94 + rsvd_68 + + + passthru + + + reserved + Snapshot + + + Container_95 + rsvd_69 + + + passthru + + + reserved + Snapshot + + + Container_96 + rsvd_70 + + + passthru + + + reserved + Snapshot + + + Container_97 + rsvd_71 + + + passthru + + + reserved + Snapshot + + + Container_98 + rsvd_72 + + + passthru + + + slow limit THERM has limited performance for CCP0 + Counter + + + Container_99 + PERF_LIMIT_THERM_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit THERM has limited performance for CCP1 + Counter + + + Container_100 + PERF_LIMIT_THERM_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit THERM has limited performance for CCP2 + Counter + + + Container_101 + PERF_LIMIT_THERM_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit THERM has limited performance for CCP3 + Counter + + + Container_102 + PERF_LIMIT_THERM_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit THERM has limited performance for CCP4 + Counter + + + Container_103 + PERF_LIMIT_THERM_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit THERM has limited performance for CLR + Counter + + + Container_104 + PERF_LIMIT_THERM_CLR_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for GT. + Counter + + + Container_105 + PERF_LIMIT_THERM_GT_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for IPU. + Counter + + + Container_106 + PERF_LIMIT_THERM_IPU_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for VPU. + Counter + + + Container_107 + PERF_LIMIT_THERM_VPU_RESIDENCY + + + xtal_time + + + slow limit THERM has limited performance for Media. + Counter + + + Container_108 + PERF_LIMIT_THERM_MEDIA_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for CCP0 + Counter + + + Container_109 + PERF_LIMIT_POWER_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit POWER has limited performance for CCP1 + Counter + + + Container_110 + PERF_LIMIT_POWER_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit POWER has limited performance for CCP2 + Counter + + + Container_111 + PERF_LIMIT_POWER_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit POWER has limited performance for CCP3 + Counter + + + Container_112 + PERF_LIMIT_POWER_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit POWER has limited performance for CCP4 + Counter + + + Container_113 + PERF_LIMIT_POWER_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit POWER has limited performance for CLR + Counter + + + Container_114 + PERF_LIMIT_POWER_CLR_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for GT + Counter + + + Container_115 + PERF_LIMIT_POWER_GT_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for Media + Counter + + + Container_116 + PERF_LIMIT_POWER_MEDIA_RESIDENCY + + + xtal_time + + + slow limit POWER has limited performance for VPU + Counter + + + Container_117 + PERF_LIMIT_POWER_VPU_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for CCP0 + Counter + + + Container_118 + PERF_LIMIT_EDP_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit EDP has limited performance for CCP1 + Counter + + + Container_119 + PERF_LIMIT_EDP_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit EDP has limited performance for CCP2 + Counter + + + Container_120 + PERF_LIMIT_EDP_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit EDP has limited performance for CCP3 + Counter + + + Container_121 + PERF_LIMIT_EDP_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit EDP has limited performance for CCP4 + Counter + + + Container_122 + PERF_LIMIT_EDP_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit EDP has limited performance for CLR + Counter + + + Container_123 + PERF_LIMIT_EDP_CLR_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for GT + Counter + + + Container_124 + PERF_LIMIT_EDP_GT_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for Media + Counter + + + Container_125 + PERF_LIMIT_EDP_MEDIA_RESIDENCY + + + xtal_time + + + slow limit EDP has limited performance for VPU + Counter + + + Container_126 + PERF_LIMIT_EDP_VPU_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for CCP0 + Counter + + + Container_127 + PERF_LIMIT_OTHER_CCP_RESIDENCY_0 + + + xtal_time + + + slow limit OTHER has limited performance for CCP1 + Counter + + + Container_128 + PERF_LIMIT_OTHER_CCP_RESIDENCY_1 + + + xtal_time + + + slow limit OTHER has limited performance for CCP2 + Counter + + + Container_129 + PERF_LIMIT_OTHER_CCP_RESIDENCY_2 + + + xtal_time + + + slow limit OTHER has limited performance for CCP3 + Counter + + + Container_130 + PERF_LIMIT_OTHER_CCP_RESIDENCY_3 + + + xtal_time + + + slow limit OTHER has limited performance for CCP4 + Counter + + + Container_131 + PERF_LIMIT_OTHER_CCP_RESIDENCY_4 + + + xtal_time + + + slow limit OTHER has limited performance for CLR + Counter + + + Container_132 + PERF_LIMIT_OTHER_CLR_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for GT + Counter + + + Container_133 + PERF_LIMIT_OTHER_GT_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for Media + Counter + + + Container_134 + PERF_LIMIT_OTHER_MEDIA_RESIDENCY + + + xtal_time + + + slow limit OTHER has limited performance for VPU + Counter + + + Container_135 + PERF_LIMIT_OTHER_VPU_RESIDENCY + + + xtal_time + + + prochot assertions. + Counter + + + Container_136 + PROCHOT_RESIDENCY + + + xtal_time + + + VCCGT VR asserted VRHOT. + Counter + + + Container_137 + VCCIA_VRHOT_RESIDENCY + + + xtal_time + + + VCCGT VR asserted VRHOT. + Counter + + + Container_138 + VCCGT_VRHOT_RESIDENCY + + + xtal_time + + + VCCAUX VR asserted VRHOT. + Counter + + + Container_139 + VCCSA_VRHOT_RESIDENCY + + + xtal_time + + + SOC was PL3 limited + Counter + + + Container_140 + PL3_LIMITED_RESIDENCY + + + xtal_time + + + SOC was PL2 limited + Counter + + + Container_141 + PL2_LIMITED_RESIDENCY + + + xtal_time + + + SOC was PL1 limited + Counter + + + Container_142 + PL1_LIMITED_RESIDENCY + + + xtal_time + + + SOC was Psys PL3 limited + Counter + + + Container_143 + PSYS_PL3_LIMITED_RESIDENCY + + + xtal_time + + + SOC was Psys PL2 limited + Counter + + + Container_144 + PSYS_PL2_LIMITED_RESIDENCY + + + xtal_time + + + SOC was Psys PL1 limited + Counter + + + Container_145 + PSYS_PL1_LIMITED_RESIDENCY + + + xtal_time + + + GT RC6 + Counter + + + Container_146 + GT_RC6_RESIDENCY + + + xtal_time + + + Media C6 residency + Counter + + + Container_147 + MEDIA_C6_RESIDENCY + + + xtal_time + + + IPU IS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + Counter + + + Container_148 + IPU_IS_C6_RESIDENCY + + + xtal_time + + + IPU PS C6// IPU Powerdown Telemetry (IS/PS Residency Counters)// --------------------------------------------------// - If the above WP issue caused a IS or PS powerdown, we want to detect that transition// and trigger the IS/PS C6 Residency Counters to resume counting//// - Note that the above WP is the only one that can cause a powerdown since both IS and PS poweroff// are represented by ratio (or divisor) equal to 0, which will get captured by the Min WP above.// ------------------------------------------------------------------------------------------------- + Counter + + + Container_149 + IPU_PS_C6_RESIDENCY + + + xtal_time + + + reserved + Counter + + + Container_150 + CNTR_RESERVED_8798 + + + passthru + + + reserved + Counter + + + Container_151 + CNTR_RESERVED_87A0 + + + passthru + + + reserved + Counter + + + Container_152 + CNTR_RESERVED_87A8 + + + passthru + + + reserved + Counter + + + Container_153 + CNTR_RESERVED_87B0 + + + passthru + + + reserved + Counter + + + Container_154 + CNTR_RESERVED_87B8 + + + passthru + + + reserved + Counter + + + Container_155 + CNTR_RESERVED_87C0 + + + passthru + + + C0 residency counter for Core0 + Counter + + + Container_156 + C0_RESIDENCY_CORE0 + + + xtal_time + + + C0 residency counter for Core1 + Counter + + + Container_157 + C0_RESIDENCY_CORE1 + + + xtal_time + + + C0 residency counter for Core2 + Counter + + + Container_158 + C0_RESIDENCY_CORE2 + + + xtal_time + + + C0 residency counter for Core3 + Counter + + + Container_159 + C0_RESIDENCY_CORE3 + + + xtal_time + + + C0 residency counter for Core4 + Counter + + + Container_160 + C0_RESIDENCY_CORE4 + + + xtal_time + + + C0 residency counter for Core5 + Counter + + + Container_161 + C0_RESIDENCY_CORE5 + + + xtal_time + + + C0 residency counter for Core6 + Counter + + + Container_162 + C0_RESIDENCY_CORE6 + + + xtal_time + + + C0 residency counter for Core7 + Counter + + + Container_163 + C0_RESIDENCY_CORE7 + + + xtal_time + + + Transition counter for when slow limit THERM has limited performance for CCP0 + Counter + + + Container_164 + PERF_LIMIT_THERM_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP1 + Counter + + + Container_164 + PERF_LIMIT_THERM_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP2 + Counter + + + Container_165 + PERF_LIMIT_THERM_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP3 + Counter + + + Container_165 + PERF_LIMIT_THERM_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CCP4 + Counter + + + Container_166 + PERF_LIMIT_THERM_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for CLR + Counter + + + Container_166 + PERF_LIMIT_THERM_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for GT + Counter + + + Container_167 + PERF_LIMIT_THERM_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for VPU + Counter + + + Container_167 + PERF_LIMIT_THERM_VPU_COUNTER + + + event_counter + + + Transition counter for when slow limit THERM has limited performance for Media + Counter + + + Container_168 + PERF_LIMIT_THERM_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP0 + Counter + + + Container_168 + PERF_LIMIT_POWER_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP1 + Counter + + + Container_169 + PERF_LIMIT_POWER_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP2 + Counter + + + Container_169 + PERF_LIMIT_POWER_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP3 + Counter + + + Container_170 + PERF_LIMIT_POWER_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CCP4 + Counter + + + Container_170 + PERF_LIMIT_POWER_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for CLR + Counter + + + Container_171 + PERF_LIMIT_POWER_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for GT + Counter + + + Container_171 + PERF_LIMIT_POWER_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for Media + Counter + + + Container_172 + PERF_LIMIT_POWER_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit POWER has limited performance for VPU + Counter + + + Container_172 + PERF_LIMIT_POWER_VPU_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP0 + Counter + + + Container_173 + PERF_LIMIT_EDP_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP1 + Counter + + + Container_173 + PERF_LIMIT_EDP_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP2 + Counter + + + Container_174 + PERF_LIMIT_EDP_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP3 + Counter + + + Container_174 + PERF_LIMIT_EDP_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CCP4 + Counter + + + Container_175 + PERF_LIMIT_EDP_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for CLR + Counter + + + Container_175 + PERF_LIMIT_EDP_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for GT. + Counter + + + Container_176 + PERF_LIMIT_EDP_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for Media + Counter + + + Container_176 + PERF_LIMIT_EDP_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit EDP has limited performance for VPU + Counter + + + Container_177 + PERF_LIMIT_EDP_VPU_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP0 + Counter + + + Container_177 + PERF_LIMIT_OTHER_CCP_COUNTER_0 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP1 + Counter + + + Container_178 + PERF_LIMIT_OTHER_CCP_COUNTER_1 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP2 + Counter + + + Container_178 + PERF_LIMIT_OTHER_CCP_COUNTER_2 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP3 + Counter + + + Container_179 + PERF_LIMIT_OTHER_CCP_COUNTER_3 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CCP4 + Counter + + + Container_179 + PERF_LIMIT_OTHER_CCP_COUNTER_4 + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for CLR. + Counter + + + Container_180 + PERF_LIMIT_OTHER_CLR_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for GT. + Counter + + + Container_180 + PERF_LIMIT_OTHER_GT_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for Media. + Counter + + + Container_181 + PERF_LIMIT_OTHER_MEDIA_COUNTER + + + event_counter + + + Transition counter for when slow limit OTHER has limited performance for VPU. + Counter + + + Container_181 + PERF_LIMIT_OTHER_VPU_COUNTER + + + event_counter + + + Energy reported by the Psys VR + Counter + + + Container_182 + PSYS_ENERGY + + + energy_J + + + Total package energy including Compute+GT+PCH, (should be the same as MSR package_energy_status) + Counter + + + Container_183 + PACKAGE_ENERGY + + + energy_J + + + IA VR energy (should be same as PRIMARY_PLANE_ENERGY_STATUS MSR) + Counter + + + Container_184 + VCCIA_ENERGY + + + vr_energy + + + GT VR energy (should be same as SECONDARY_PLANE_ENERGY_STATUS) + Counter + + + Container_185 + VCCGT_ENERGY + + + vr_energy + + + Energy estimated by Pcode using utilization factor from the VPU. Format is U18.14. https://docs.intel.com/documents/pm_doc/src/lnl/IP%20Integration/VPU%20PM%20HAS/VPU%20PM%20HAS.html#scalability-activity-factor + Counter + + + Container_186 + VPU_ENERGY + + + U32.18.14 + + + Total I/O read bandwidth for Display (VC1) + Counter + + + Container_187 + DISPLAY_IO_READ_BANDWIDTH + + + bw_64B + + + ReservedTotal I/O write bandwidth for display** NOT IMPLEMENTED ** + Counter + + + Container_188 + DISPLAY_IO_WRITE_BANDWIDTH + + + bw_32B + + + ReservedTotal display VC1 (non-coherent read) bandwidth.** NOT IMPLEMENTED **~same as DISPLAY_IO_READ_BANDWIDTH + Counter + + + Container_189 + DISPLAY_VC1_BANDWIDTH + + + bw_32B + + + Reserved. Moved to SoC die + Counter + + + Container_190 + IO_WRITE_BANDWIDTH_IP0_3 + + + bw_B + + + Reserved. Moved to SoC die + Counter + + + Container_191 + IO_READ_BANDWIDTH_IP0_3 + + + bw_B + + + Mufasa hit traffic + Counter + + + Container_192 + MUFASA_HIT_BW + + + bw_32B + + + Mufasa miss traffic + Counter + + + Container_193 + MUFASA_MISS_BW + + + bw_32B + + + HBO0 read and write traffic + Counter + + + Container_194 + HBO0_BW + + + bw_32B + + + HBO1 read and write traffic + Counter + + + Container_195 + HBO1_BW + + + bw_32B + + + SANTA (CCF) read traffic + Counter + + + Container_196 + SANTA_BW_READ + + + bw_32B + + + SANTA (CCF) write traffic + Counter + + + Container_197 + SANTA_BW_WRITE + + + bw_32B + + + IDI (Iceland) read traffic + Counter + + + Container_198 + IDIBR_BW_READ + + + bw_32B + + + IDI (Iceland) write traffic + Counter + + + Container_199 + IDIBR_BW_WRITE + + + bw_32B + + + Total MemSWITCH (previously I/O) read bandwidth. + Counter + + + Container_200 + NOC_BW_MEMSWITCH_READ + + + bw_32B + + + Total MemSWITCH (previously I/O) write bandwidth. + Counter + + + Container_201 + NOC_BW_MEMSWITCH_WRITE + + + bw_32B + + + Main NOC D2D read traffic + Counter + + + Container_202 + NOC_BW_D2D_READ + + + bw_32B + + + Main NOC D2D write traffic + Counter + + + Container_203 + NOC_BW_D2D_WRITE + + + bw_32B + + + Main NOC GT read traffic + Counter + + + Container_204 + NOC_BW_GT_READ + + + bw_32B + + + Main NOC GT write traffic + Counter + + + Container_205 + NOC_BW_GT_WRITE + + + bw_32B + + + HW counter disabled by default. Can be enabled through tap + Counter + + + Container_206 + NOC_BW_MEDIA_READ + + + bw_32B + + + HW counter disabled by default. Can be enabled through tap + Counter + + + Container_207 + NOC_BW_MEDIA_WRITE + + + bw_32B + + + HW counter disabled by default. Can be enabled through tap + Counter + + + Container_208 + NOC_BW_IPU_READ + + + bw_32B + + + HW counter disabled by default. Can be enabled through tap + Counter + + + Container_209 + NOC_BW_IPU_WRITE + + + bw_32B + + + CCE0 read and write traffic. HW counter disabled by default. Can be enabled through tap + Counter + + + Container_210 + NOC_BW_CCE0 + + + bw_32B + + + CCE1 read and write traffic. HW counter disabled by default. Can be enabled through tap + Counter + + + Container_211 + NOC_BW_CCE1 + + + bw_32B + + + ReservedDE has a joint counter for 2 linksValue is same as DISPLAY_IO_READ_BANDWIDTH + Counter + + + Container_212 + NOC_BW_DISP0 + + + bw_32B + + + ReservedDE has a joint counter for 2 linksValue is same as DISPLAY_IO_READ_BANDWIDTH + Counter + + + Container_213 + NOC_BW_DISP1 + + + bw_32B + + + Reserved. Covered in VPU_MEMORY_BW + Counter + + + Container_214 + NOC_BW_VPU0 + + + bw_32B + + + Reserved. Covered in VPU_MEMORY_BW + Counter + + + Container_215 + NOC_BW_VPU1 + + + bw_32B + + + reserved + Counter + + + Container_216 + CNTR_RESERVED_89A8 + + + passthru + + + reserved + Counter + + + Container_217 + CNTR_RESERVED_89B0 + + + passthru + + + reserved + Counter + + + Container_218 + CNTR_RESERVED_89B8 + + + passthru + + + reserved + Counter + + + Container_219 + CNTR_RESERVED_89C0 + + + passthru + + + prochot assertions. + Counter + + + Container_220 + PROCHOT_COUNTER + + + event_counter + + + counts VCCIA VR asserted VRHOT. + Counter + + + Container_220 + VCCIA_VRHOT_COUNTER + + + event_counter + + + counts VCCGT VR asserted VRHOT. + Counter + + + Container_221 + VCCGT_VRHOT_COUNTER + + + event_counter + + + counts VCCSA VR asserted VRHOT. + Counter + + + Container_221 + VCCSA_VRHOT_COUNTER + + + event_counter + + + SOC was PL3 limited + Counter + + + Container_222 + PL3_LIMITED_COUNTER + + + event_counter + + + SOC was PL2 limited + Counter + + + Container_222 + PL2_LIMITED_COUNTER + + + event_counter + + + SOC was PL1 limited + Counter + + + Container_223 + PL1_LIMITED_COUNTER + + + event_counter + + + SOC was Psys PL3 limited + Counter + + + Container_223 + PSYS_PL3_LIMITED_COUNTER + + + event_counter + + + SOC was Psys PL2 limited + Counter + + + Container_224 + PSYS_PL2_LIMITED_COUNTER + + + event_counter + + + SOC was Psys PL1 limited + Counter + + + Container_224 + PSYS_PL1_LIMITED_COUNTER + + + event_counter + + + GT RC6 state transition counter + Counter + + + Container_225 + GT_RC6_COUNTER + + + event_counter + + + Media C6 state transition counter + Counter + + + Container_225 + MEDIA_C6_COUNTER + + + event_counter + + + IPU IS C6 state transition counter + Counter + + + Container_226 + IPU_IS_C6_COUNTER + + + event_counter + + + IPU PS C6 state transition counter + Counter + + + Container_226 + IPU_PS_C6_COUNTER + + + event_counter + + + reserved + Counter + + + Container_227 + CNTR_RESERVED_8A00 + + + passthru + + + reserved + Counter + + + Container_228 + CNTR_RESERVED_8A08 + + + passthru + + + reserved + Counter + + + Container_229 + CNTR_RESERVED_8A10 + + + passthru + + + This register increments every SBCLK cycle that MC0 is in self refresh + Counter + + + Container_230 + MC_IN_SR_COUNT_0 + + + sb_time + + + This register increments every SBCLK cycle that MC1 is in self refresh + Counter + + + Container_231 + MC_IN_SR_COUNT_1 + + + sb_time + + + MC0 sends count Enable indications: 4 signals: two ChannelsSingle counter counts for both Channels, stands for channels 0-1Details:This register increments every SBCLK cycle that CKE of all ranks in a channel is low and all ranks are not yet in self-refresh or deep self-refresh. It will roll over to 0 when at the limit. Note: The counter will count CKE off cycles and increment even for an unpopulated channel. Software needs to detect if a channel is unpopulated (by seeing if MC_Init_State_0_0_0_MCHBAR.Rank_occupancy = 0x0) and not consume the value in this counter if channel is unpopulated.MC0_CKE_POWER_DOWN_COUNT = MC0_gv0+MC0_gv1+MC0_gv2+MC0_gv3 // stands for channels 0-1 + Counter + + + Container_232 + MC0_CKE_POWER_DOWN_COUNT + + + sb_time + + + MC1 sends count Enable indications: 4 signals: two ChannelsSingle counter counts for both Channels, stands for channels 2-3Details:This register increments every SBCLK cycle that CKE of all ranks in a channel is low and all ranks are not yet in self-refresh or deep self-refresh. It will roll over to 0 when at the limit. Note: The counter will count CKE off cycles and increment even for an unpopulated channel. Software needs to detect if a channel is unpopulated (by seeing if MC_Init_State_0_0_0_MCHBAR.Rank_occupancy = 0x0) and not consume the value in this counter if channel is unpopulated.MC1_CKE_POWER_DOWN_COUNT = MC1_gv0+MC1_gv1+MC1_gv2+MC1_gv3 // stands for channels 2-3 + Counter + + + Container_233 + MC1_CKE_POWER_DOWN_COUNT + + + sb_time + + + reserved + Counter + + + Container_234 + CNTR_RESERVED_8A38 + + + passthru + + + reserved + Counter + + + Container_235 + CNTR_RESERVED_8A40 + + + passthru + + + increments the counter every sideband clock when CMI PLL is locked. + Counter + + + Container_236 + MC_ON_RATIO + + + mc_cycles + + + increments the counter every sideband clock by '1' when CMI PLL is locked. Time_MC_ON = counter * SBclk_period + Counter + + + Container_237 + MC_ON_TIME + + + sb_time + + + Counts total MC writes. Virtual bandwidth counter based on PWM_WRDATA bulkcr sample.i.e TOTAL_WRITE_BANDWIDTH = total PWM_WRDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + Counter + + + Container_238 + TOTAL_WRITE_BANDWIDTH + + + bw_32B + + + Counts total MC reads. Virtual bandwidth counter based on PWM_RDDATA bulkcr sample.i.e TOTAL_READ_BANDWIDTH = total PWM_RDDATA_COUNT_0_0_0_MCHBAR (per MC, channel, sub-channel) + Counter + + + Container_239 + TOTAL_READ_BANDWIDTH + + + bw_32B + + + The counter value is incremented as a function of the number of cores that reside in C0 and active. If N cores are simultaneously in C0, then the number of "clock ticks" that are incremented is N. Counts in XTAL units. Should be same as MSR ANY_CORE_C0 0x659. + Counter + + + Container_240 + IO_PKG_IA_C0_ANY_SUM + + + xtal_time + + + This counter increments whenever GT slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. Should be same as MSR ANY_GFXE_C0 0x65a + Counter + + + Container_241 + IO_PKG_GT_C0_ANY + + + xtal_time + + + This counter increments whenever GT slices or unslices are active and in C0 state and in overlap with one of the IA cores that is active and in C0. Counts in XTAL units. Should be same as MSR CORE_GFXE_OVERLAP_C0 0x65b + Counter + + + Container_242 + IO_PKG_GT_AND_IA_OVERLAP + + + xtal_time + + + Follow exactly the IO_PKG_GT_C0_ANY_SLICE. The only change is that they do +N (GT ratio) instead of +1 on the relevant clock edge. Counter rate is in Xtal Clock.PKG_GT_C0_ANY_SLICE Counts clocks that any GT slice is active. Reference clock is XTAL. + Counter + + + Container_243 + IO_PKG_GT_C0_ANY_RATIO + + + xtal_time + + + This counter increments whenever MEDIA slices or unslices are ON and in C0 state. Counter rate is the Xtal clock. + Counter + + + Container_244 + IO_PKG_MEDIA_C0_ANY + + + xtal_time + + + Follow exactly the PKG_MEDIA_C0_ANY_SLICE. The only change is that they do +N (media ratio) instead of +1 on the relevant clock edge.PKG_MEDIA_C0_ANY_SLICE Counts clocks that any Media slice is active.Counter rate is in Xtal Clock. + Counter + + + Container_245 + IO_PKG_MEDIA_C0_ANY_RATIO + + + xtal_time + + + follow exactly the PKG_IA_C0_ANYThe only change is that they do +N (Max IA ratio) instead of +1 on the relevant clock edge and conditions (while any LP_AT_C0[i]=1):PCU_CR_PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU += PKG_IA_C0_CURRENT_RATIO.RATIOPKG_IA_C0_CURRENT_RATIO.RATIO = MAX(IO_WP_CV_P_STATE[IA_RATIO]).Reference clock is XTAL.More details [here](https://docs.intel.com/documents/pm_doc/src/LNL/MAS/CCP_PM/ccp_pm_mas.html#punit-counters) + Counter + + + Container_246 + IO_PKG_IA_C0_ANY_RATIO + + + xtal_time + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 0. + Counter + + + Container_247 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0 + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 1. + Counter + + + Container_247 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1 + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in PECI sensor 2. + Counter + + + Container_248 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2 + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 0. + Counter + + + Container_248 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_0_MMIO + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 1. + Counter + + + Container_249 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_1_MMIO + + + slowloop + + + Time in ms during which SoC was throttled because of platform temperature reported in MMIO sensor 2. + Counter + + + Container_249 + PERF_LIMIT_PLATFORM_TEMPERATURE_SENSOR_2_MMIO + + + slowloop + + + Time in state counter + Counter + + + Container_250 + IPU_PARTIAL_SLEEP_RESIDENCY + + + xtal_time + + + Time in state counter + Counter + + + Container_251 + VPU_PARTIAL_SLEEP_RESIDENCY + + + xtal_time + + + state transition counter + Counter + + + Container_252 + IPU_PARTIAL_SLEEP_ENTRY_COUNTERS + + + event_counter + + + state transition counter + Counter + + + Container_252 + VPU_PARTIAL_SLEEP_ENTRY_COUNTERS + + + event_counter + + + reserved + Counter + + + Container_253 + CNTR_RESERVED_0_8AD0 + + + passthru + + + reserved + Counter + + + Container_254 + CNTR_RESERVED_1_to_133 + + + passthru + + + reserved + Counter + + + Container_255 + CNTR_RESERVED_1_to_133_1 + + + passthru + + + reserved + Counter + + + Container_256 + CNTR_RESERVED_1_to_133_2 + + + passthru + + + reserved + Counter + + + Container_257 + CNTR_RESERVED_1_to_133_3 + + + passthru + + + reserved + Counter + + + Container_258 + CNTR_RESERVED_1_to_133_4 + + + passthru + + + reserved + Counter + + + Container_259 + CNTR_RESERVED_1_to_133_5 + + + passthru + + + reserved + Counter + + + Container_260 + CNTR_RESERVED_1_to_133_6 + + + passthru + + + reserved + Counter + + + Container_261 + CNTR_RESERVED_1_to_133_7 + + + passthru + + + reserved + Counter + + + Container_262 + CNTR_RESERVED_1_to_133_8 + + + passthru + + + reserved + Counter + + + Container_263 + CNTR_RESERVED_1_to_133_9 + + + passthru + + + reserved + Counter + + + Container_264 + CNTR_RESERVED_1_to_133_10 + + + passthru + + + reserved + Counter + + + Container_265 + CNTR_RESERVED_1_to_133_11 + + + passthru + + + reserved + Counter + + + Container_266 + CNTR_RESERVED_1_to_133_12 + + + passthru + + + reserved + Counter + + + Container_267 + CNTR_RESERVED_1_to_133_13 + + + passthru + + + reserved + Counter + + + Container_268 + CNTR_RESERVED_1_to_133_14 + + + passthru + + + reserved + Counter + + + Container_269 + CNTR_RESERVED_1_to_133_15 + + + passthru + + + reserved + Counter + + + Container_270 + CNTR_RESERVED_1_to_133_16 + + + passthru + + + reserved + Counter + + + Container_271 + CNTR_RESERVED_1_to_133_17 + + + passthru + + + reserved + Counter + + + Container_272 + CNTR_RESERVED_1_to_133_18 + + + passthru + + + reserved + Counter + + + Container_273 + CNTR_RESERVED_1_to_133_19 + + + passthru + + + reserved + Counter + + + Container_274 + CNTR_RESERVED_1_to_133_20 + + + passthru + + + reserved + Counter + + + Container_275 + CNTR_RESERVED_1_to_133_21 + + + passthru + + + reserved + Counter + + + Container_276 + CNTR_RESERVED_1_to_133_22 + + + passthru + + + reserved + Counter + + + Container_277 + CNTR_RESERVED_1_to_133_23 + + + passthru + + + reserved + Counter + + + Container_278 + CNTR_RESERVED_1_to_133_24 + + + passthru + + + reserved + Counter + + + Container_279 + CNTR_RESERVED_1_to_133_25 + + + passthru + + + reserved + Counter + + + Container_280 + CNTR_RESERVED_1_to_133_26 + + + passthru + + + reserved + Counter + + + Container_281 + CNTR_RESERVED_1_to_133_27 + + + passthru + + + reserved + Counter + + + Container_282 + CNTR_RESERVED_1_to_133_28 + + + passthru + + + reserved + Counter + + + Container_283 + CNTR_RESERVED_1_to_133_29 + + + passthru + + + reserved + Counter + + + Container_284 + CNTR_RESERVED_1_to_133_30 + + + passthru + + + reserved + Counter + + + Container_285 + CNTR_RESERVED_1_to_133_31 + + + passthru + + + reserved + Counter + + + Container_286 + CNTR_RESERVED_1_to_133_32 + + + passthru + + + reserved + Counter + + + Container_287 + CNTR_RESERVED_1_to_133_33 + + + passthru + + + reserved + Counter + + + Container_288 + CNTR_RESERVED_1_to_133_34 + + + passthru + + + reserved + Counter + + + Container_289 + CNTR_RESERVED_1_to_133_35 + + + passthru + + + reserved + Counter + + + Container_290 + CNTR_RESERVED_1_to_133_36 + + + passthru + + + reserved + Counter + + + Container_291 + CNTR_RESERVED_1_to_133_37 + + + passthru + + + reserved + Counter + + + Container_292 + CNTR_RESERVED_1_to_133_38 + + + passthru + + + reserved + Counter + + + Container_293 + CNTR_RESERVED_1_to_133_39 + + + passthru + + + reserved + Counter + + + Container_294 + CNTR_RESERVED_1_to_133_40 + + + passthru + + + reserved + Counter + + + Container_295 + CNTR_RESERVED_1_to_133_41 + + + passthru + + + reserved + Counter + + + Container_296 + CNTR_RESERVED_1_to_133_42 + + + passthru + + + reserved + Counter + + + Container_297 + CNTR_RESERVED_1_to_133_43 + + + passthru + + + reserved + Counter + + + Container_298 + CNTR_RESERVED_1_to_133_44 + + + passthru + + + reserved + Counter + + + Container_299 + CNTR_RESERVED_1_to_133_45 + + + passthru + + + reserved + Counter + + + Container_300 + CNTR_RESERVED_1_to_133_46 + + + passthru + + + reserved + Counter + + + Container_301 + CNTR_RESERVED_1_to_133_47 + + + passthru + + + reserved + Counter + + + Container_302 + CNTR_RESERVED_1_to_133_48 + + + passthru + + + reserved + Counter + + + Container_303 + CNTR_RESERVED_1_to_133_49 + + + passthru + + + reserved + Counter + + + Container_304 + CNTR_RESERVED_1_to_133_50 + + + passthru + + + reserved + Counter + + + Container_305 + CNTR_RESERVED_1_to_133_51 + + + passthru + + + reserved + Counter + + + Container_306 + CNTR_RESERVED_1_to_133_52 + + + passthru + + + reserved + Counter + + + Container_307 + CNTR_RESERVED_1_to_133_53 + + + passthru + + + reserved + Counter + + + Container_308 + CNTR_RESERVED_1_to_133_54 + + + passthru + + + reserved + Counter + + + Container_309 + CNTR_RESERVED_1_to_133_55 + + + passthru + + + reserved + Counter + + + Container_310 + CNTR_RESERVED_1_to_133_56 + + + passthru + + + reserved + Counter + + + Container_311 + CNTR_RESERVED_1_to_133_57 + + + passthru + + + reserved + Counter + + + Container_312 + CNTR_RESERVED_1_to_133_58 + + + passthru + + + reserved + Counter + + + Container_313 + CNTR_RESERVED_1_to_133_59 + + + passthru + + + reserved + Counter + + + Container_314 + CNTR_RESERVED_1_to_133_60 + + + passthru + + + reserved + Counter + + + Container_315 + CNTR_RESERVED_1_to_133_61 + + + passthru + + + reserved + Counter + + + Container_316 + CNTR_RESERVED_1_to_133_62 + + + passthru + + + reserved + Counter + + + Container_317 + CNTR_RESERVED_1_to_133_63 + + + passthru + + + reserved + Counter + + + Container_318 + CNTR_RESERVED_1_to_133_64 + + + passthru + + + reserved + Counter + + + Container_319 + CNTR_RESERVED_1_to_133_65 + + + passthru + + + reserved + Counter + + + Container_320 + CNTR_RESERVED_1_to_133_66 + + + passthru + + + reserved + Counter + + + Container_321 + CNTR_RESERVED_1_to_133_67 + + + passthru + + + reserved + Counter + + + Container_322 + CNTR_RESERVED_1_to_133_68 + + + passthru + + + reserved + Counter + + + Container_323 + CNTR_RESERVED_1_to_133_69 + + + passthru + + + reserved + Counter + + + Container_324 + CNTR_RESERVED_1_to_133_70 + + + passthru + + + reserved + Counter + + + Container_325 + CNTR_RESERVED_1_to_133_71 + + + passthru + + + reserved + Counter + + + Container_326 + CNTR_RESERVED_1_to_133_72 + + + passthru + + + reserved + Counter + + + Container_327 + CNTR_RESERVED_1_to_133_73 + + + passthru + + + reserved + Counter + + + Container_328 + CNTR_RESERVED_1_to_133_74 + + + passthru + + + reserved + Counter + + + Container_329 + CNTR_RESERVED_1_to_133_75 + + + passthru + + + reserved + Counter + + + Container_330 + CNTR_RESERVED_1_to_133_76 + + + passthru + + + reserved + Counter + + + Container_331 + CNTR_RESERVED_1_to_133_77 + + + passthru + + + reserved + Counter + + + Container_332 + CNTR_RESERVED_1_to_133_78 + + + passthru + + + reserved + Counter + + + Container_333 + CNTR_RESERVED_1_to_133_79 + + + passthru + + + reserved + Counter + + + Container_334 + CNTR_RESERVED_1_to_133_80 + + + passthru + + + reserved + Counter + + + Container_335 + CNTR_RESERVED_1_to_133_81 + + + passthru + + + reserved + Counter + + + Container_336 + CNTR_RESERVED_1_to_133_82 + + + passthru + + + reserved + Counter + + + Container_337 + CNTR_RESERVED_1_to_133_83 + + + passthru + + + reserved + Counter + + + Container_338 + CNTR_RESERVED_1_to_133_84 + + + passthru + + + reserved + Counter + + + Container_339 + CNTR_RESERVED_1_to_133_85 + + + passthru + + + reserved + Counter + + + Container_340 + CNTR_RESERVED_1_to_133_86 + + + passthru + + + reserved + Counter + + + Container_341 + CNTR_RESERVED_1_to_133_87 + + + passthru + + + reserved + Counter + + + Container_342 + CNTR_RESERVED_1_to_133_88 + + + passthru + + + reserved + Counter + + + Container_343 + CNTR_RESERVED_1_to_133_89 + + + passthru + + + reserved + Counter + + + Container_344 + CNTR_RESERVED_1_to_133_90 + + + passthru + + + reserved + Counter + + + Container_345 + CNTR_RESERVED_1_to_133_91 + + + passthru + + + reserved + Counter + + + Container_346 + CNTR_RESERVED_1_to_133_92 + + + passthru + + + reserved + Counter + + + Container_347 + CNTR_RESERVED_1_to_133_93 + + + passthru + + + reserved + Counter + + + Container_348 + CNTR_RESERVED_1_to_133_94 + + + passthru + + + reserved + Counter + + + Container_349 + CNTR_RESERVED_1_to_133_95 + + + passthru + + + reserved + Counter + + + Container_350 + CNTR_RESERVED_1_to_133_96 + + + passthru + + + reserved + Counter + + + Container_351 + CNTR_RESERVED_1_to_133_97 + + + passthru + + + reserved + Counter + + + Container_352 + CNTR_RESERVED_1_to_133_98 + + + passthru + + + reserved + Counter + + + Container_353 + CNTR_RESERVED_1_to_133_99 + + + passthru + + + reserved + Counter + + + Container_354 + CNTR_RESERVED_1_to_133_100 + + + passthru + + + reserved + Counter + + + Container_355 + CNTR_RESERVED_1_to_133_101 + + + passthru + + + reserved + Counter + + + Container_356 + CNTR_RESERVED_1_to_133_102 + + + passthru + + + reserved + Counter + + + Container_357 + CNTR_RESERVED_1_to_133_103 + + + passthru + + + reserved + Counter + + + Container_358 + CNTR_RESERVED_1_to_133_104 + + + passthru + + + reserved + Counter + + + Container_359 + CNTR_RESERVED_1_to_133_105 + + + passthru + + + reserved + Counter + + + Container_360 + CNTR_RESERVED_1_to_133_106 + + + passthru + + + reserved + Counter + + + Container_361 + CNTR_RESERVED_1_to_133_107 + + + passthru + + + reserved + Counter + + + Container_362 + CNTR_RESERVED_1_to_133_108 + + + passthru + + + reserved + Counter + + + Container_363 + CNTR_RESERVED_1_to_133_109 + + + passthru + + + reserved + Counter + + + Container_364 + CNTR_RESERVED_1_to_133_110 + + + passthru + + + reserved + Counter + + + Container_365 + CNTR_RESERVED_1_to_133_111 + + + passthru + + + reserved + Counter + + + Container_366 + CNTR_RESERVED_1_to_133_112 + + + passthru + + + reserved + Counter + + + Container_367 + CNTR_RESERVED_1_to_133_113 + + + passthru + + + reserved + Counter + + + Container_368 + CNTR_RESERVED_1_to_133_114 + + + passthru + + + reserved + Counter + + + Container_369 + CNTR_RESERVED_1_to_133_115 + + + passthru + + + reserved + Counter + + + Container_370 + CNTR_RESERVED_1_to_133_116 + + + passthru + + + reserved + Counter + + + Container_371 + CNTR_RESERVED_1_to_133_117 + + + passthru + + + reserved + Counter + + + Container_372 + CNTR_RESERVED_1_to_133_118 + + + passthru + + + reserved + Counter + + + Container_373 + CNTR_RESERVED_1_to_133_119 + + + passthru + + + reserved + Counter + + + Container_374 + CNTR_RESERVED_1_to_133_120 + + + passthru + + + reserved + Counter + + + Container_375 + CNTR_RESERVED_1_to_133_121 + + + passthru + + + reserved + Counter + + + Container_376 + CNTR_RESERVED_1_to_133_122 + + + passthru + + + reserved + Counter + + + Container_377 + CNTR_RESERVED_1_to_133_123 + + + passthru + + + reserved + Counter + + + Container_378 + CNTR_RESERVED_1_to_133_124 + + + passthru + + + reserved + Counter + + + Container_379 + CNTR_RESERVED_1_to_133_125 + + + passthru + + + reserved + Counter + + + Container_380 + CNTR_RESERVED_1_to_133_126 + + + passthru + + + reserved + Counter + + + Container_381 + CNTR_RESERVED_1_to_133_127 + + + passthru + + + reserved + Counter + + + Container_382 + CNTR_RESERVED_1_to_133_128 + + + passthru + + + reserved + Counter + + + Container_383 + CNTR_RESERVED_1_to_133_129 + + + passthru + + + reserved + Counter + + + Container_384 + CNTR_RESERVED_1_to_133_130 + + + passthru + + + reserved + Counter + + + Container_385 + CNTR_RESERVED_1_to_133_131 + + + passthru + + + reserved + Counter + + + Container_386 + CNTR_RESERVED_1_to_133_132 + + + passthru + + + Average DDR BW over a time interval + Counter + + + Container_387 + VPU_MEMORY_BW + + + bw_1024B + + + Cycle count of amount of times VPU is in D0 active state + Counter + + + Container_387 + VPU_D0_ACTIVE_RESIDENCY + + + xtal_time_19_2 + + + Number of times VPU enters into D0 active state + Counter + + + Container_388 + VPU_D0_ACTIVE_ENTRY_COUNT + + + event_counter + + + Cycle count of amount of time VPU is in D0I2 active state + Counter + + + Container_388 + VPU_D0i2_ACTIVE_RESIDENCY + + + xtal_time_19_2 + + + Cycle count of amount of time VPU is in D0I2 Idle state + Counter + + + Container_389 + VPU_D0i2_IDLE_RESIDENCY + + + xtal_time_19_2 + + + Number of times VPU enters into D0I2 active state + Counter + + + Container_389 + VPU_D0i2_ACTIVE_ENTRY_COUNT + + + event_counter + + + Number of times VPU enters into D0I2 Idle state + Counter + + + Container_390 + VPU_D0i2_IDLE_ENTRY_COUNT + + + event_counter + + + Overall number of cycles for a context in RealTime priority + Counter + + + Container_390 + VPU_REALTIME_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + Overall number of cycles for a context in normal priority + Counter + + + Container_391 + VPU_NORMAL_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + Overall number of cycles for a context in focus priority + Counter + + + Container_391 + VPU_FOCUS_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + Overall number of cycles for a context in background priority + Counter + + + Container_392 + VPU_IDLE_PRIORITY_CONTEXT_CYCLE_COUNT + + + xtal_time_19_2 + + + Current value of the FRC (fixed frequency) when data is reported out - VPU fixed frequency FRC(free running counter) value + Counter + + + Container_392 + VPU_FIXED_FREQ_FRC_VAL + + + cycle_count + + + Current value of the FRC (variable frequeny) when data is reported out. - VPU variable frequency (DVFS clock) FRC (free running counter) value + Counter + + + Container_393 + VPU_VAR_FREQ_FRC_VAL + + + cycle_count + + + reserved + Counter + + + Container_393 + VPU_RSVD0_8F34 + + + passthru + + + reserved + Counter + + + Container_394 + VPU_RSVD_1_to_25 + + + passthru + + + reserved + Counter + + + Container_395 + VPU_RSVD_1_to_25_1 + + + passthru + + + reserved + Counter + + + Container_396 + VPU_RSVD_1_to_25_2 + + + passthru + + + reserved + Counter + + + Container_397 + VPU_RSVD_1_to_25_3 + + + passthru + + + reserved + Counter + + + Container_398 + VPU_RSVD_1_to_25_4 + + + passthru + + + reserved + Counter + + + Container_399 + VPU_RSVD_1_to_25_5 + + + passthru + + + reserved + Counter + + + Container_400 + VPU_RSVD_1_to_25_6 + + + passthru + + + reserved + Counter + + + Container_401 + VPU_RSVD_1_to_25_7 + + + passthru + + + reserved + Counter + + + Container_402 + VPU_RSVD_1_to_25_8 + + + passthru + + + reserved + Counter + + + Container_403 + VPU_RSVD_1_to_25_9 + + + passthru + + + reserved + Counter + + + Container_404 + VPU_RSVD_1_to_25_10 + + + passthru + + + reserved + Counter + + + Container_405 + VPU_RSVD_1_to_25_11 + + + passthru + + + reserved + Counter + + + Container_406 + VPU_RSVD_1_to_25_12 + + + passthru + + + reserved + Counter + + + Container_407 + VPU_RSVD_1_to_25_13 + + + passthru + + + reserved + Counter + + + Container_408 + VPU_RSVD_1_to_25_14 + + + passthru + + + reserved + Counter + + + Container_409 + VPU_RSVD_1_to_25_15 + + + passthru + + + reserved + Counter + + + Container_410 + VPU_RSVD_1_to_25_16 + + + passthru + + + reserved + Counter + + + Container_411 + VPU_RSVD_1_to_25_17 + + + passthru + + + reserved + Counter + + + Container_412 + VPU_RSVD_1_to_25_18 + + + passthru + + + reserved + Counter + + + Container_413 + VPU_RSVD_1_to_25_19 + + + passthru + + + reserved + Counter + + + Container_414 + VPU_RSVD_1_to_25_20 + + + passthru + + + reserved + Counter + + + Container_415 + VPU_RSVD_1_to_25_21 + + + passthru + + + reserved + Counter + + + Container_416 + VPU_RSVD_1_to_25_22 + + + passthru + + + reserved + Counter + + + Container_417 + VPU_RSVD_1_to_25_23 + + + passthru + + + reserved + Counter + + + Container_418 + VPU_RSVD_1_to_25_24 + + + passthru + + + \ No newline at end of file diff --git a/xml/LNL/0/lnla0_0r5_common.xml b/xml/LNL/0/lnla0_0r5_common.xml new file mode 100644 index 0000000..f626a82 --- /dev/null +++ b/xml/LNL/0/lnla0_0r5_common.xml @@ -0,0 +1,268 @@ + + + + + counter + + s + + ANY + + + counter + + % + + ANY + + + counter + + % + + ANY + + + status + + V + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + status + + us + + ANY + + + status + + MHz + + ANY + + + counter + + J + + ANY + + + status + + V + + ANY + + + status + + C + + S8.7.0 + + + counter + + + + ANY + + + status + + V + + U8.1.7 + + + status + + A + + U10.7.3 + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + A + + U16.8.8 + + + status + + + + U9.1.8 + + + status + + % + + ANY + + + status + + + + U16.1.15 + + + status + + V + + ANY + + + status + + A + + U11.9.2 + + + counter + + J + + U32.18.14 + + + counter + + J + + ANY + + + counter + + cycles + + ANY + + + counter + + + counter + + cycles + + ANY + + + counter + + s + + ANY + + + counter + + cycles + + ANY + + + status + + + counter + + s + + ANY + + + status + + C + + ANY + + + counter + + MB + + ANY + + + counter + + s + + ANY + + + string + + \ No newline at end of file diff --git a/xml/LNL/1/lnla0_1r5_aggregator.xml b/xml/LNL/1/lnla0_1r5_aggregator.xml new file mode 100644 index 0000000..b7c5034 --- /dev/null +++ b/xml/LNL/1/lnla0_1r5_aggregator.xml @@ -0,0 +1,1541 @@ + +]> + + + &otherfile; + LNL + LNL M/P PMT Telemetry aggregator 1 samples definition and transformation rules + 0x03072105 + LNL + 0 + + + Groupname 0x8000 + 64 + + Crystal clock count. Used as a reference count in converting many of the counters presented in this telemetry space. + XTAL + Counter + 64 + 0 + 63 + + + + Groupname 0x8008 + 64 + + Reference count for block cause counters. Counts the number of 1ms intervals during which PkgC entry was blocked at least once by any reason. To calculate percent blocked by a specific reason, divide corresponding block reason counter by this counter value. Sums all prevent cause to PKGC + PACKAGE_CSTATE_BLOCK_REFCNT + Counter + 32 + 0 + 31 + + + Candidate for removal. Reference count for wake cause counters. To calculate percent for each wake reason, divide by this number. Sums all wake cause from PKGC + PACKAGE_CSTATE_WAKE_REFCNT + Counter + 32 + 32 + 63 + + + + Groupname 0x8010 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 0. + PREVENT_PKGC6_INTERNAL_0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by VPU. + PREVENT_PKGC6_VPU_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8018 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Reserved 0. + PREVENT_PKGC_RESERVED_0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 0. + PREVENT_PKGC6_CHIPSET_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8020 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 1. + PREVENT_PKGC6_CHIPSET_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Media 0. + PREVENT_PKGC6_MEDIA_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8028 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Media 1. + PREVENT_PKGC6_MEDIA_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by GT_PB. + PREVENT_PKGC6_GT + Counter + 32 + 32 + 63 + + + + Groupname 0x8030 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 1. + PREVENT_PKGC6_INTERNAL_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 2. + PREVENT_PKGC6_CHIPSET_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8038 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 3. + PREVENT_PKGC6_CHIPSET_3 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by IPU. + PREVENT_PKGC6_IPU_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8040 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 2. + PREVENT_PKGC6_INTERNAL_2 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 3. + PREVENT_PKGC6_INTERNAL_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8048 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by DE. + PREVENT_PKGC6_DE_0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by CLUSTER0. + PREVENT_PKGC6_CLUSTER0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8050 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by CLUSTER1. + PREVENT_PKGC6_CLUSTER1 + Counter + 32 + 0 + 31 + + + reserved + PREVENT_PKGC6_RSVD_8054 + Counter + 32 + 32 + 63 + + + + Groupname 0x8058 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by VPU. + PREVENT_PKGC6_VPU_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by IPU. + PREVENT_PKGC6_IPU_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8060 + 64 + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by DE. + PREVENT_PKGC6_DE_1 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by IPU. + PREVENT_PKGC10_IPU_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8068 + 64 + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by CLUSTER0 + PREVENT_PKGC10_CLUSTER0 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by CLUSTER1. + PREVENT_PKGC10_CLUSTER1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8070 + 64 + + reserved + PREVENT_PKGC10_RSVD_8070 + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by DE. + PREVENT_PKGC10_DE_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8078 + 64 + + Sample, not counter.PKGC can be disabled using several methods e.g DFX, fuses, BIOS.Pcode will update this register with resolved disabled PKGC mask.Encoding: bit 0 set: disable C6. bit 1 set: disable C6. bit 2 is set: disable C10. bit 3 is set: disable C10. bit 4 is set: disable C10Lower 5 bits are being used, rest are reserved.More details in https://docs.intel.com/documents/pm_doc/src/lnl/HAS/PkgC/PkgC.html#resolving + PREVENT_PKGC_DFX_OTHERS + Counter + 32 + 0 + 31 + + + Counts the number of 1ms intervals where PKGCx was prevented by other reasons, incremeting in sum of prevented PKGCx per 1ms. + PREVENT_PKGC_OTHER_REASONS + Counter + 32 + 32 + 63 + + + + Groupname 0x8080 + 64 + + Measures the residency in Cluster0 C0. Units are XTAL clocks. + CLUSTER0_C0_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8088 + 64 + + Measures the residency in Cluster1 C0. Units are XTAL clocks. + CLUSTER1_C0_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8090 + 64 + + Measures the residency in Cluster0 C2. Units are XTAL clocks. + CLUSTER0_C2_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x8098 + 64 + + Measures the residency in Cluster1 C2. Units are XTAL clocks. + CLUSTER1_C2_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80a0 + 64 + + Measures the residency in Cluster0 C3. Units are XTAL clocks. + CLUSTER0_C3_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80a8 + 64 + + Measures the residency in Cluster1 C3. Units are XTAL clocks. + CLUSTER1_C3_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80b0 + 64 + + Measures the residency in Cluster0 C6 (LLC flushed). Units are XTAL clocks. Exposed in MSR 0x0ce in TSC units + CLUSTER0_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80b8 + 64 + + Measures the residency in Cluster1 C6. Units are XTAL clocks. + CLUSTER1_C6_RESIDENCY + Counter + 64 + 0 + 63 + + + + Groupname 0x80c0 + 64 + + Measures the residency in Package C-state C2. Units are XTAL clocks. Exposed in MSR 0x60d in TSC units + PACKAGE_CSTATE_RESIDENCY_1 + Counter + 64 + 0 + 63 + + + + Groupname 0x80c8 + 64 + + Measures the residency in Package C-state C6. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_2 + Counter + 64 + 0 + 63 + + + + Groupname 0x80d0 + 64 + + Measures the residency in Package C-state C6. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_3 + Counter + 64 + 0 + 63 + + + + Groupname 0x80d8 + 64 + + Measures the residency in Package C-state C10. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_4 + Counter + 64 + 0 + 63 + + + + Groupname 0x80e0 + 64 + + Measures the residency in Package C-state C10. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_5 + Counter + 64 + 0 + 63 + + + + Groupname 0x80e8 + 64 + + Measures the residency in Package C-state C10. Units are XTAL clocks. + PACKAGE_CSTATE_RESIDENCY_6 + Counter + 64 + 0 + 63 + + + + Groupname 0x80f0 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 0 + WAKE_REASON_HW_0 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: HW 1 + WAKE_REASON_HW_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x80f8 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 2 + WAKE_REASON_HW_2 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: HW 3 + WAKE_REASON_HW_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8100 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 4 + WAKE_REASON_HW_4 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: PECI + WAKE_REASON_HW_PECI + Counter + 32 + 32 + 63 + + + + Groupname 0x8108 + 64 + + Count the number of times exited from PkgC state due to the reason: Display 1 + WAKE_REASON_DISPLAY_1 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: Display 2 + WAKE_REASON_DISPLAY_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8110 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 8 + WAKE_REASON_HW_8 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: JTAG + WAKE_REASON_JTAG + Counter + 32 + 32 + 63 + + + + Groupname 0x8118 + 64 + + Count the number of times exited from PkgC state due to the reason: VPU + WAKE_REASON_VPU + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: IPU + WAKE_REASON_IPU + Counter + 32 + 32 + 63 + + + + Groupname 0x8120 + 64 + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_12 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_13 + Counter + 32 + 32 + 63 + + + + Groupname 0x8128 + 64 + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_14 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_15 + Counter + 32 + 32 + 63 + + + + Groupname 0x8130 + 64 + + Count the number of times exited from PkgC state - internal + WAKE_REASON_HW_16 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: According to target + WAKE_REASON_HW_17 + Counter + 32 + 32 + 63 + + + + Groupname 0x8138 + 64 + + Count the number of times exited from PkgC state due to the reason: Chipset 1 + WAKE_REASON_CHIPSET_1 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: Chipset 2 + WAKE_REASON_CHIPSET_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8140 + 64 + + Count the number of times exited from PkgC state due to the reason: HW 20 + WAKE_REASON_HW_20 + Counter + 32 + 0 + 31 + + + Count the number of times exited from PkgC state due to the reason: HW 21 + WAKE_REASON_HW_21 + Counter + 32 + 32 + 63 + + + + Groupname 0x8148 + 64 + + Measures the number of transitions to Cluster0 C0 + CLUSTER0_C0_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C0 + CLUSTER1_C0_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8150 + 64 + + Measures the number of transitions to Cluster0 C2 + CLUSTER0_C2_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C2 + CLUSTER1_C2_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8158 + 64 + + Measures the number of transitions to Cluster0 C3 + CLUSTER0_C3_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C3 + CLUSTER1_C3_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8160 + 64 + + Measures the number of transitions to Cluster0 C6 + CLUSTER0_C6_ENTRANCE_COUNTER + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Cluster1 C6 + CLUSTER1_C6_ENTRANCE_COUNTER + Counter + 32 + 32 + 63 + + + + Groupname 0x8168 + 64 + + Measures the number of transitions to Package C-state C0 + PACKAGE_CSTATE_ENTRANCE_COUNTER_0 + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Package C-state C2 + PACKAGE_CSTATE_ENTRANCE_COUNTER_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x8170 + 64 + + Measures the number of transitions to Package C-state C6 + PACKAGE_CSTATE_ENTRANCE_COUNTER_2 + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Package C-state C6 + PACKAGE_CSTATE_ENTRANCE_COUNTER_3 + Counter + 32 + 32 + 63 + + + + Groupname 0x8178 + 64 + + Measures the number of transitions to Package C-state C10 + PACKAGE_CSTATE_ENTRANCE_COUNTER_4 + Counter + 32 + 0 + 31 + + + Measures the number of transitions to Package C-state C10 + PACKAGE_CSTATE_ENTRANCE_COUNTER_5 + Counter + 32 + 32 + 63 + + + + Groupname 0x8180 + 64 + + Measures the number of transitions to Package C-state C10 + PACKAGE_CSTATE_ENTRANCE_COUNTER_6 + Counter + 32 + 0 + 31 + + + reserved + PACKAGE_CSTATE_RSVD_8184 + Counter + 32 + 32 + 63 + + + + Groupname 0x8188 + 64 + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC6_LTR_0 + Counter + 32 + 0 + 31 + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC6_NDE_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8190 + 64 + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC6_TNTE_0 + Counter + 32 + 0 + 31 + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC6_DEMOTION_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8198 + 64 + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC6_IRT_0 + Counter + 32 + 0 + 31 + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC6_LTR_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81a0 + 64 + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC6_NDE_1 + Counter + 32 + 0 + 31 + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC6_TNTE_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81a8 + 64 + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC6_DEMOTION_1 + Counter + 32 + 0 + 31 + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC6_IRT_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81b0 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC10_LTR_0 + Counter + 32 + 0 + 31 + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC10_NDE_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x81b8 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC10_TNTE_0 + Counter + 32 + 0 + 31 + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC10_DEMOTION_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x81c0 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC10_IRT_0 + Counter + 32 + 0 + 31 + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC10_LTR_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81c8 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC10_NDE_1 + Counter + 32 + 0 + 31 + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC10_TNTE_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81d0 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC10_DEMOTION_1 + Counter + 32 + 0 + 31 + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC10_IRT_1 + Counter + 32 + 32 + 63 + + + + Groupname 0x81d8 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + PREVENT_PKGC10_LTR_2 + Counter + 32 + 0 + 31 + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + PREVENT_PKGC10_NDE_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x81e0 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + PREVENT_PKGC10_TNTE_2 + Counter + 32 + 0 + 31 + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + PREVENT_PKGC10_DEMOTION_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x81e8 + 64 + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + PREVENT_PKGC10_IRT_2 + Counter + 32 + 0 + 31 + + + reserved + PREVENT_RSVD_81EC + Counter + 32 + 32 + 63 + + + + Groupname 0x81f0 + 64 + + Current display latency tolerance + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_DISPLAY + Counter + 32 + 0 + 31 + + + Current IPU latency tolerance + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_IPU + Counter + 32 + 32 + 63 + + + + Groupname 0x81f8 + 64 + + Current PCH latency tolerance + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_PCH + Counter + 32 + 0 + 31 + + + Worst-case LTR Threshold for PKGC6 + PKGC6_LTR_THRESHOLDS_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8200 + 64 + + Worst-case LTR Threshold for PKGC6 + PKGC6_LTR_THRESHOLDS_1 + Counter + 32 + 0 + 31 + + + Worst-case LTR Threshold for PKGC6 + PKGC10_LTR_THRESHOLDS_0 + Counter + 32 + 32 + 63 + + + + Groupname 0x8208 + 64 + + Worst-case LTR Threshold for PKGC10 + PKGC10_LTR_THRESHOLDS_1 + Counter + 32 + 0 + 31 + + + Worst-case LTR Threshold for PKGC10 + PKGC10_LTR_THRESHOLDS_2 + Counter + 32 + 32 + 63 + + + + Groupname 0x8210 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8218 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8220 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8228 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8230 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8238 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8240 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8248 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8250 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8258 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8260 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8268 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8270 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8278 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8280 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8288 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8290 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x8298 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82a0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82a8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82b0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82b8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82c0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82c8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82d0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82d8 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + + Groupname 0x82e0 + 64 + + reserved + FIXED_CNTR_RESERVED_1_to_27 + Counter + 64 + 0 + 63 + + + \ No newline at end of file diff --git a/xml/LNL/1/lnla0_1r5_aggregator_interface.xml b/xml/LNL/1/lnla0_1r5_aggregator_interface.xml new file mode 100644 index 0000000..69e11fc --- /dev/null +++ b/xml/LNL/1/lnla0_1r5_aggregator_interface.xml @@ -0,0 +1,1956 @@ + + + + + + + + + float + + parameter_0 + + $parameter_0 / ( 38.4 * 1e6 ) + + + float + + parameter_0 + parameter_1 + + $parameter_0 / $parameter_1 * 100 + + + float + + parameter_0 + parameter_1 + + $parameter_0 / $parameter_1 * 100 + + + float + + parameter_0 + + $parameter_0 * 0.0025 + + + float + + parameter_0 + + $parameter_0 * 64 / 1e6 + + + float + + parameter_0 + + $parameter_0 / 1e6 + + + float + + parameter_0 + + $parameter_0 * 32 / 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + ( ( ( $parameter_0 | ( ~ $parameter_0 + 1 ) ) >> 7 ) & 0x1 ) * ( 49 + $parameter_0 ) * 0.005 + + + integer + + parameter_0 + + ( ( ( 1 - ( ( $parameter_0 >> 7 ) & 0x1 ) ) * ( $parameter_0 & 0xff ) ) - ( ( ( $parameter_0 >> 7 ) & 0x1 ) * ( ( ( $parameter_0 & 0x7f ) ^ 0x7f ) + 1 ) ) ) + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + ( $parameter_0 & 0xff ) / ( 2**7 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x3ff ) / ( 2**3 ) + + + float + + parameter_0 + + $parameter_0 * 0.1 + + + float + + parameter_0 + + $parameter_0 * 0.01667 + + + float + + parameter_0 + + $parameter_0 * 0.025 + + + float + + parameter_0 + + $parameter_0 * 0.033 + + + float + + parameter_0 + + $parameter_0 * 0.05 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**8 ) + + + float + + parameter_0 + + ( $parameter_0 & 0x1ff ) / ( 2**8 ) + + + float + + parameter_0 + + $parameter_0 * 100 / 128 + + + float + + parameter_0 + + ( $parameter_0 & 0xffff ) / ( 2**15 ) + + + float + + parameter_0 + + $parameter_0 * 0.002 + + + float + + parameter_0 + + ( $parameter_0 & 0x7ff ) / ( 2**2 ) + + + float + + parameter_0 + + ( $parameter_0 & 0xffffffff ) / ( 2**14 ) + + + float + + parameter_0 + + $parameter_0 / 16384 + + + float + + parameter_0 + + $parameter_0 * 64 + + + float + + parameter_0 + + $parameter_0 * 0.025 * 33.33 + + + float + + parameter_0 + + $parameter_0 / 400 * 1e6 + + + float + + parameter_0 + + $parameter_0 + + + float + + parameter_0 + + $parameter_0 * 1000 + + + float + + parameter_0 + + $parameter_0 / 32 + + + float + + parameter_0 + + $parameter_0 * 1024 / 1e6 + + + float + + parameter_0 + + $parameter_0 / ( 19.2 * 1e6 ) + + + integer + + parameter_0 + + $parameter_0 + + + + LNL + LNL M/P PMT Telemetry aggregator 1 samples definition and transformation rules + 0x03072105 + Public + 10 + 2024-09-18 + + + Crystal clock count. Used as a reference count in converting many of the counters presented in this telemetry space. + Counter + + + Container_0 + XTAL + + + passthru + + + Reference count for block cause counters. Counts the number of 1ms intervals during which PkgC entry was blocked at least once by any reason. To calculate percent blocked by a specific reason, divide corresponding block reason counter by this counter value. Sums all prevent cause to PKGC + Counter + + + Container_1 + PACKAGE_CSTATE_BLOCK_REFCNT + + + event_counter + + + Candidate for removal. Reference count for wake cause counters. To calculate percent for each wake reason, divide by this number. Sums all wake cause from PKGC + Counter + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + event_counter + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 0. + Counter + + + Container_2 + PREVENT_PKGC6_INTERNAL_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by VPU. + Counter + + + Container_2 + PREVENT_PKGC6_VPU_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Reserved 0. + Counter + + + Container_3 + PREVENT_PKGC_RESERVED_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 0. + Counter + + + Container_3 + PREVENT_PKGC6_CHIPSET_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 1. + Counter + + + Container_4 + PREVENT_PKGC6_CHIPSET_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Media 0. + Counter + + + Container_4 + PREVENT_PKGC6_MEDIA_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Media 1. + Counter + + + Container_5 + PREVENT_PKGC6_MEDIA_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by GT_PB. + Counter + + + Container_5 + PREVENT_PKGC6_GT + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 1. + Counter + + + Container_6 + PREVENT_PKGC6_INTERNAL_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 2. + Counter + + + Container_6 + PREVENT_PKGC6_CHIPSET_2 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Chipset 3. + Counter + + + Container_7 + PREVENT_PKGC6_CHIPSET_3 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by IPU. + Counter + + + Container_7 + PREVENT_PKGC6_IPU_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 2. + Counter + + + Container_8 + PREVENT_PKGC6_INTERNAL_2 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by Internal 3. + Counter + + + Container_8 + PREVENT_PKGC6_INTERNAL_3 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by DE. + Counter + + + Container_9 + PREVENT_PKGC6_DE_0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by CLUSTER0. + Counter + + + Container_9 + PREVENT_PKGC6_CLUSTER0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by CLUSTER1. + Counter + + + Container_10 + PREVENT_PKGC6_CLUSTER1 + + + slowloop + + + reserved + Counter + + + Container_10 + PREVENT_PKGC6_RSVD_8054 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by VPU. + Counter + + + Container_11 + PREVENT_PKGC6_VPU_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by IPU. + Counter + + + Container_11 + PREVENT_PKGC6_IPU_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC6 entry was blocked by DE. + Counter + + + Container_12 + PREVENT_PKGC6_DE_1 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by IPU. + Counter + + + Container_12 + PREVENT_PKGC10_IPU_2 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by CLUSTER0 + Counter + + + Container_13 + PREVENT_PKGC10_CLUSTER0 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by CLUSTER1. + Counter + + + Container_13 + PREVENT_PKGC10_CLUSTER1 + + + slowloop + + + reserved + Counter + + + Container_14 + PREVENT_PKGC10_RSVD_8070 + + + slowloop + + + Counts the number of 1ms intervals during which PkgC10 entry was blocked by DE. + Counter + + + Container_14 + PREVENT_PKGC10_DE_2 + + + slowloop + + + Sample, not counter.PKGC can be disabled using several methods e.g DFX, fuses, BIOS.Pcode will update this register with resolved disabled PKGC mask.Encoding: bit 0 set: disable C6. bit 1 set: disable C6. bit 2 is set: disable C10. bit 3 is set: disable C10. bit 4 is set: disable C10Lower 5 bits are being used, rest are reserved.More details in https://docs.intel.com/documents/pm_doc/src/lnl/HAS/PkgC/PkgC.html#resolving + Counter + + + Container_15 + PREVENT_PKGC_DFX_OTHERS + + + slowloop + + + Counts the number of 1ms intervals where PKGCx was prevented by other reasons, incremeting in sum of prevented PKGCx per 1ms. + Counter + + + Container_15 + PREVENT_PKGC_OTHER_REASONS + + + slowloop + + + Measures the residency in Cluster0 C0. Units are XTAL clocks. + Counter + + + Container_16 + CLUSTER0_C0_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C0. Units are XTAL clocks. + Counter + + + Container_17 + CLUSTER1_C0_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster0 C2. Units are XTAL clocks. + Counter + + + Container_18 + CLUSTER0_C2_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C2. Units are XTAL clocks. + Counter + + + Container_19 + CLUSTER1_C2_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster0 C3. Units are XTAL clocks. + Counter + + + Container_20 + CLUSTER0_C3_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C3. Units are XTAL clocks. + Counter + + + Container_21 + CLUSTER1_C3_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster0 C6 (LLC flushed). Units are XTAL clocks. Exposed in MSR 0x0ce in TSC units + Counter + + + Container_22 + CLUSTER0_C6_RESIDENCY + + + xtal_time + + + Measures the residency in Cluster1 C6. Units are XTAL clocks. + Counter + + + Container_23 + CLUSTER1_C6_RESIDENCY + + + xtal_time + + + Measures the residency in Package C-state C2. Units are XTAL clocks. Exposed in MSR 0x60d in TSC units + Counter + + + Container_24 + PACKAGE_CSTATE_RESIDENCY_1 + + + xtal_time + + + Measures the residency in Package C-state C6. Units are XTAL clocks. + Counter + + + Container_25 + PACKAGE_CSTATE_RESIDENCY_2 + + + xtal_time + + + Measures the residency in Package C-state C6. Units are XTAL clocks. + Counter + + + Container_26 + PACKAGE_CSTATE_RESIDENCY_3 + + + xtal_time + + + Measures the residency in Package C-state C10. Units are XTAL clocks. + Counter + + + Container_27 + PACKAGE_CSTATE_RESIDENCY_4 + + + xtal_time + + + Measures the residency in Package C-state C10. Units are XTAL clocks. + Counter + + + Container_28 + PACKAGE_CSTATE_RESIDENCY_5 + + + xtal_time + + + Measures the residency in Package C-state C10. Units are XTAL clocks. + Counter + + + Container_29 + PACKAGE_CSTATE_RESIDENCY_6 + + + xtal_time + + + Count the number of times exited from PkgC state due to the reason: HW 0 + Counter + + + Container_30 + WAKE_REASON_HW_0 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 1 + Counter + + + Container_30 + WAKE_REASON_HW_1 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 2 + Counter + + + Container_31 + WAKE_REASON_HW_2 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 3 + Counter + + + Container_31 + WAKE_REASON_HW_3 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 4 + Counter + + + Container_32 + WAKE_REASON_HW_4 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: PECI + Counter + + + Container_32 + WAKE_REASON_HW_PECI + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Display 1 + Counter + + + Container_33 + WAKE_REASON_DISPLAY_1 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Display 2 + Counter + + + Container_33 + WAKE_REASON_DISPLAY_2 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 8 + Counter + + + Container_34 + WAKE_REASON_HW_8 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: JTAG + Counter + + + Container_34 + WAKE_REASON_JTAG + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: VPU + Counter + + + Container_35 + WAKE_REASON_VPU + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: IPU + Counter + + + Container_35 + WAKE_REASON_IPU + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_36 + WAKE_REASON_HW_12 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_36 + WAKE_REASON_HW_13 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_37 + WAKE_REASON_HW_14 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_37 + WAKE_REASON_HW_15 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state - internal + Counter + + + Container_38 + WAKE_REASON_HW_16 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: According to target + Counter + + + Container_38 + WAKE_REASON_HW_17 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Chipset 1 + Counter + + + Container_39 + WAKE_REASON_CHIPSET_1 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: Chipset 2 + Counter + + + Container_39 + WAKE_REASON_CHIPSET_2 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 20 + Counter + + + Container_40 + WAKE_REASON_HW_20 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Count the number of times exited from PkgC state due to the reason: HW 21 + Counter + + + Container_40 + WAKE_REASON_HW_21 + + + Container_1 + PACKAGE_CSTATE_WAKE_REFCNT + + + pkgc_wake_cause + + + Measures the number of transitions to Cluster0 C0 + Counter + + + Container_41 + CLUSTER0_C0_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C0 + Counter + + + Container_41 + CLUSTER1_C0_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster0 C2 + Counter + + + Container_42 + CLUSTER0_C2_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C2 + Counter + + + Container_42 + CLUSTER1_C2_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster0 C3 + Counter + + + Container_43 + CLUSTER0_C3_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C3 + Counter + + + Container_43 + CLUSTER1_C3_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster0 C6 + Counter + + + Container_44 + CLUSTER0_C6_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Cluster1 C6 + Counter + + + Container_44 + CLUSTER1_C6_ENTRANCE_COUNTER + + + event_counter + + + Measures the number of transitions to Package C-state C0 + Counter + + + Container_45 + PACKAGE_CSTATE_ENTRANCE_COUNTER_0 + + + event_counter + + + Measures the number of transitions to Package C-state C2 + Counter + + + Container_45 + PACKAGE_CSTATE_ENTRANCE_COUNTER_1 + + + event_counter + + + Measures the number of transitions to Package C-state C6 + Counter + + + Container_46 + PACKAGE_CSTATE_ENTRANCE_COUNTER_2 + + + event_counter + + + Measures the number of transitions to Package C-state C6 + Counter + + + Container_46 + PACKAGE_CSTATE_ENTRANCE_COUNTER_3 + + + event_counter + + + Measures the number of transitions to Package C-state C10 + Counter + + + Container_47 + PACKAGE_CSTATE_ENTRANCE_COUNTER_4 + + + event_counter + + + Measures the number of transitions to Package C-state C10 + Counter + + + Container_47 + PACKAGE_CSTATE_ENTRANCE_COUNTER_5 + + + event_counter + + + Measures the number of transitions to Package C-state C10 + Counter + + + Container_48 + PACKAGE_CSTATE_ENTRANCE_COUNTER_6 + + + event_counter + + + reserved + Counter + + + Container_48 + PACKAGE_CSTATE_RSVD_8184 + + + passthru + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_49 + PREVENT_PKGC6_LTR_0 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_49 + PREVENT_PKGC6_NDE_0 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_50 + PREVENT_PKGC6_TNTE_0 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_50 + PREVENT_PKGC6_DEMOTION_0 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_51 + PREVENT_PKGC6_IRT_0 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_51 + PREVENT_PKGC6_LTR_1 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_52 + PREVENT_PKGC6_NDE_1 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_52 + PREVENT_PKGC6_TNTE_1 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_53 + PREVENT_PKGC6_DEMOTION_1 + + + slowloop + + + PKGC6 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_53 + PREVENT_PKGC6_IRT_1 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_54 + PREVENT_PKGC10_LTR_0 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_54 + PREVENT_PKGC10_NDE_0 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_55 + PREVENT_PKGC10_TNTE_0 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_55 + PREVENT_PKGC10_DEMOTION_0 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_56 + PREVENT_PKGC10_IRT_0 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_56 + PREVENT_PKGC10_LTR_1 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_57 + PREVENT_PKGC10_NDE_1 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_57 + PREVENT_PKGC10_TNTE_1 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_58 + PREVENT_PKGC10_DEMOTION_1 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_58 + PREVENT_PKGC10_IRT_1 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: LTR + Counter + + + Container_59 + PREVENT_PKGC10_LTR_2 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: NDE + Counter + + + Container_59 + PREVENT_PKGC10_NDE_2 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: TNTE + Counter + + + Container_60 + PREVENT_PKGC10_TNTE_2 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: DEMOTION + Counter + + + Container_60 + PREVENT_PKGC10_DEMOTION_2 + + + slowloop + + + PKGC10 WAKE - Count the number of 1ms intervals exited from PkgC state due to the reason: IRT + Counter + + + Container_61 + PREVENT_PKGC10_IRT_2 + + + slowloop + + + reserved + Counter + + + Container_61 + PREVENT_RSVD_81EC + + + passthru + + + Current display latency tolerance + Counter + + + Container_62 + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_DISPLAY + + + ltr + + + Current IPU latency tolerance + Counter + + + Container_62 + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_IPU + + + ltr + + + Current PCH latency tolerance + Counter + + + Container_63 + PACKAGE_CSTATE_LTR_LAST_KNOWN_VALUE_PCH + + + ltr + + + Worst-case LTR Threshold for PKGC6 + Counter + + + Container_63 + PKGC6_LTR_THRESHOLDS_0 + + + ltr + + + Worst-case LTR Threshold for PKGC6 + Counter + + + Container_64 + PKGC6_LTR_THRESHOLDS_1 + + + ltr + + + Worst-case LTR Threshold for PKGC6 + Counter + + + Container_64 + PKGC10_LTR_THRESHOLDS_0 + + + ltr + + + Worst-case LTR Threshold for PKGC10 + Counter + + + Container_65 + PKGC10_LTR_THRESHOLDS_1 + + + ltr + + + Worst-case LTR Threshold for PKGC10 + Counter + + + Container_65 + PKGC10_LTR_THRESHOLDS_2 + + + ltr + + + reserved + Counter + + + Container_66 + FIXED_CNTR_RESERVED_1_to_27 + + + passthru + + + reserved + Counter + + + Container_67 + FIXED_CNTR_RESERVED_1_to_27_1 + + + passthru + + + reserved + Counter + + + Container_68 + FIXED_CNTR_RESERVED_1_to_27_2 + + + passthru + + + reserved + Counter + + + Container_69 + FIXED_CNTR_RESERVED_1_to_27_3 + + + passthru + + + reserved + Counter + + + Container_70 + FIXED_CNTR_RESERVED_1_to_27_4 + + + passthru + + + reserved + Counter + + + Container_71 + FIXED_CNTR_RESERVED_1_to_27_5 + + + passthru + + + reserved + Counter + + + Container_72 + FIXED_CNTR_RESERVED_1_to_27_6 + + + passthru + + + reserved + Counter + + + Container_73 + FIXED_CNTR_RESERVED_1_to_27_7 + + + passthru + + + reserved + Counter + + + Container_74 + FIXED_CNTR_RESERVED_1_to_27_8 + + + passthru + + + reserved + Counter + + + Container_75 + FIXED_CNTR_RESERVED_1_to_27_9 + + + passthru + + + reserved + Counter + + + Container_76 + FIXED_CNTR_RESERVED_1_to_27_10 + + + passthru + + + reserved + Counter + + + Container_77 + FIXED_CNTR_RESERVED_1_to_27_11 + + + passthru + + + reserved + Counter + + + Container_78 + FIXED_CNTR_RESERVED_1_to_27_12 + + + passthru + + + reserved + Counter + + + Container_79 + FIXED_CNTR_RESERVED_1_to_27_13 + + + passthru + + + reserved + Counter + + + Container_80 + FIXED_CNTR_RESERVED_1_to_27_14 + + + passthru + + + reserved + Counter + + + Container_81 + FIXED_CNTR_RESERVED_1_to_27_15 + + + passthru + + + reserved + Counter + + + Container_82 + FIXED_CNTR_RESERVED_1_to_27_16 + + + passthru + + + reserved + Counter + + + Container_83 + FIXED_CNTR_RESERVED_1_to_27_17 + + + passthru + + + reserved + Counter + + + Container_84 + FIXED_CNTR_RESERVED_1_to_27_18 + + + passthru + + + reserved + Counter + + + Container_85 + FIXED_CNTR_RESERVED_1_to_27_19 + + + passthru + + + reserved + Counter + + + Container_86 + FIXED_CNTR_RESERVED_1_to_27_20 + + + passthru + + + reserved + Counter + + + Container_87 + FIXED_CNTR_RESERVED_1_to_27_21 + + + passthru + + + reserved + Counter + + + Container_88 + FIXED_CNTR_RESERVED_1_to_27_22 + + + passthru + + + reserved + Counter + + + Container_89 + FIXED_CNTR_RESERVED_1_to_27_23 + + + passthru + + + reserved + Counter + + + Container_90 + FIXED_CNTR_RESERVED_1_to_27_24 + + + passthru + + + reserved + Counter + + + Container_91 + FIXED_CNTR_RESERVED_1_to_27_25 + + + passthru + + + reserved + Counter + + + Container_92 + FIXED_CNTR_RESERVED_1_to_27_26 + + + passthru + + + \ No newline at end of file diff --git a/xml/LNL/1/lnla0_1r5_common.xml b/xml/LNL/1/lnla0_1r5_common.xml new file mode 100644 index 0000000..f626a82 --- /dev/null +++ b/xml/LNL/1/lnla0_1r5_common.xml @@ -0,0 +1,268 @@ + + + + + counter + + s + + ANY + + + counter + + % + + ANY + + + counter + + % + + ANY + + + status + + V + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + counter + + MB + + ANY + + + status + + us + + ANY + + + status + + MHz + + ANY + + + counter + + J + + ANY + + + status + + V + + ANY + + + status + + C + + S8.7.0 + + + counter + + + + ANY + + + status + + V + + U8.1.7 + + + status + + A + + U10.7.3 + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + GHz + + ANY + + + status + + A + + U16.8.8 + + + status + + + + U9.1.8 + + + status + + % + + ANY + + + status + + + + U16.1.15 + + + status + + V + + ANY + + + status + + A + + U11.9.2 + + + counter + + J + + U32.18.14 + + + counter + + J + + ANY + + + counter + + cycles + + ANY + + + counter + + + counter + + cycles + + ANY + + + counter + + s + + ANY + + + counter + + cycles + + ANY + + + status + + + counter + + s + + ANY + + + status + + C + + ANY + + + counter + + MB + + ANY + + + counter + + s + + ANY + + + string + + \ No newline at end of file diff --git a/xml/pmt.xml b/xml/pmt.xml index 8696ca1..d4b57ed 100644 --- a/xml/pmt.xml +++ b/xml/pmt.xml @@ -1,5 +1,5 @@ - 2024-09-11 + 2024-09-18 2022-09-08 @@ -181,5 +181,29 @@ spr_aggregator_interface.xml + + 2024-09-18 + production + LNL M/P PMT Telemetry aggregator 0 samples definition and transformation rules + + LNL/0 + lnla0_0r5 + lnla0_0r5_common.xml + lnla0_0r5_aggregator.xml + lnla0_0r5_aggregator_interface.xml + + + + 2024-09-18 + production + LNL M/P PMT Telemetry aggregator 1 samples definition and transformation rules + + LNL/1 + lnla0_1r5 + lnla0_1r5_common.xml + lnla0_1r5_aggregator.xml + lnla0_1r5_aggregator_interface.xml + +