From a8ea37c256be6cf5f16f95a8191411655234f7f7 Mon Sep 17 00:00:00 2001
From: 0xd4d <de4dot@gmail.com>
Date: Tue, 26 May 2020 19:25:32 +0200
Subject: [PATCH] Use new PrefetchReserved[3-7] instead of reserved-nop

---
 src/UnitTests/Intel/Decoder/DecoderTest16.txt | 20 ++++++--
 src/UnitTests/Intel/Decoder/DecoderTest32.txt | 20 ++++++--
 src/UnitTests/Intel/Decoder/DecoderTest64.txt | 25 ++++++++--
 src/UnitTests/Intel/Encoder/OpCodeInfos.txt   |  5 ++
 .../Formatter/Gas/Test64_ForceSuffix.txt      |  5 ++
 .../Intel/Formatter/Gas/Test64_NoSuffix.txt   |  5 ++
 .../Intel/Formatter/InstructionInfos64.txt    |  5 ++
 .../Formatter/Intel/Test64_MemAlways.txt      |  5 ++
 .../Formatter/Intel/Test64_MemDefault.txt     |  5 ++
 .../Formatter/Intel/Test64_MemMinimum.txt     |  5 ++
 .../Intel/Formatter/Masm/Test64_MemAlways.txt |  5 ++
 .../Formatter/Masm/Test64_MemDefault.txt      |  5 ++
 .../Formatter/Masm/Test64_MemMinimum.txt      |  5 ++
 .../Intel/Formatter/Nasm/Test64_MemAlways.txt |  5 ++
 .../Formatter/Nasm/Test64_MemDefault.txt      |  5 ++
 .../Formatter/Nasm/Test64_MemMinimum.txt      |  5 ++
 .../InstructionInfoTest_32.txt                | 10 ++++
 .../InstructionInfoTest_64.txt                | 14 +++++-
 .../Assembler/AssemblerSyntaxGenerator.cs     |  6 +++
 .../Generator/Decoder/DecoderTable_Legacy.cs  | 10 ++--
 src/csharp/Intel/Generator/Enums/Code.cs      |  5 ++
 .../Generator/Formatters/Gas/CtorInfosData.cs |  5 ++
 .../Formatters/Intel/CtorInfosData.cs         |  5 ++
 .../Formatters/Masm/CtorInfosData.cs          |  5 ++
 .../Formatters/Nasm/CtorInfosData.cs          |  5 ++
 .../Generator/Tables/InstructionDefsData.cs   | 15 ++++++
 .../Intel/ToEnumConverter.Code.cs             |  7 ++-
 src/csharp/Intel/Iced/Intel/Code.g.cs         | 40 ++++++++++++++++
 .../OpCodeHandlersTables_Legacy.g.cs          | 22 +++++++--
 .../EncoderInternal/OpCodeHandlers.Data.g.cs  |  7 ++-
 .../FormatterStringsTable.g.cs                |  3 +-
 .../GasFormatterInternal/InstrInfos.g.cs      | 17 +++++++
 .../Intel/Iced/Intel/IcedConstants.g.cs       |  2 +-
 .../InstrInfoTable.g.cs                       |  7 ++-
 .../Iced/Intel/InstructionMemorySizes.g.cs    | 10 ++++
 .../Intel/Iced/Intel/InstructionOpCounts.g.cs |  5 ++
 .../IntelFormatterInternal/InstrInfos.g.cs    | 17 +++++++
 .../MasmFormatterInternal/InstrInfos.g.cs     | 17 +++++++
 .../Intel/Iced/Intel/MnemonicUtilsData.g.cs   |  5 ++
 .../NasmFormatterInternal/InstrInfos.g.cs     | 19 ++++++++
 src/rust/iced-x86-js/src/code.rs              |  5 ++
 src/rust/iced-x86/src/code.rs                 | 47 ++++++++++++++++++-
 .../src/decoder/table_de/data_legacy.rs       | 22 +++++++--
 src/rust/iced-x86/src/encoder/op_code_data.rs |  7 ++-
 .../iced-x86/src/formatter/gas/fmt_data.rs    | 17 +++++++
 .../iced-x86/src/formatter/intel/fmt_data.rs  | 17 +++++++
 .../iced-x86/src/formatter/masm/fmt_data.rs   | 17 +++++++
 .../iced-x86/src/formatter/nasm/fmt_data.rs   | 19 ++++++++
 .../iced-x86/src/formatter/strings_data.rs    |  5 +-
 src/rust/iced-x86/src/iced_constants.rs       |  2 +-
 src/rust/iced-x86/src/info/info_table.rs      |  7 ++-
 .../iced-x86/src/instruction_memory_sizes.rs  | 10 ++++
 .../iced-x86/src/instruction_op_counts.rs     |  5 ++
 src/rust/iced-x86/src/mnemonics.rs            |  5 ++
 .../test_utils/from_str_conv/code_table.rs    |  7 ++-
 55 files changed, 538 insertions(+), 42 deletions(-)

diff --git a/src/UnitTests/Intel/Decoder/DecoderTest16.txt b/src/UnitTests/Intel/Decoder/DecoderTest16.txt
index dd0f49810..3a29831cd 100644
--- a/src/UnitTests/Intel/Decoder/DecoderTest16.txt
+++ b/src/UnitTests/Intel/Decoder/DecoderTest16.txt
@@ -2738,11 +2738,11 @@ F3 0F09, Wbnoinvd, Wbnoinvd, 0,
 
 0F0D CE, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=r;si op1=r;cx resnop
 0F0D 18, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx resnop
-0F0D 18, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx
-0F0D 20, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;sp
-0F0D 28, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bp
-0F0D 30, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;si
-0F0D 38, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;di
+0F0D 18, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx resnop
+0F0D 20, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;sp resnop
+0F0D 28, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bp resnop
+0F0D 30, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;si resnop
+0F0D 38, ReservedNop_rm16_r16_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;di resnop
 
 66 0F0D CE, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esi op1=r;ecx resnop
 66 0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;bx;si;1;0;0;UInt32 op1=r;ebx resnop
@@ -2753,6 +2753,16 @@ F3 0F09, Wbnoinvd, Wbnoinvd, 0,
 
 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;bx;si;1;0;0;UInt8
 
+0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
+0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;bx;si;1;0;0;UInt8
+
 0F0E, Femms, Femms, 0,
 
 0F10 CE, Umov_rm8_r8, Umov, 2, op0=r;dh op1=r;cl umov
diff --git a/src/UnitTests/Intel/Decoder/DecoderTest32.txt b/src/UnitTests/Intel/Decoder/DecoderTest32.txt
index e2d3767a1..69492a800 100644
--- a/src/UnitTests/Intel/Decoder/DecoderTest32.txt
+++ b/src/UnitTests/Intel/Decoder/DecoderTest32.txt
@@ -2741,11 +2741,11 @@ F3 0F09, Wbnoinvd, Wbnoinvd, 0,
 
 0F0D CE, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esi op1=r;ecx resnop
 0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx resnop
-0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx
-0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esp
-0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebp
-0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esi
-0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;edi
+0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx resnop
+0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esp resnop
+0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebp resnop
+0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;esi resnop
+0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;edi resnop
 
 0F0D 00, Prefetch_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
 
@@ -2753,6 +2753,16 @@ F3 0F09, Wbnoinvd, Wbnoinvd, 0,
 
 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;eax;;1;0;0;UInt8
 
+0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
+0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;eax;;1;0;0;UInt8
+
 0F0E, Femms, Femms, 0,
 
 0F10 CE, Umov_rm8_r8, Umov, 2, op0=r;dh op1=r;cl umov
diff --git a/src/UnitTests/Intel/Decoder/DecoderTest64.txt b/src/UnitTests/Intel/Decoder/DecoderTest64.txt
index 5352d6874..b0866578a 100644
--- a/src/UnitTests/Intel/Decoder/DecoderTest64.txt
+++ b/src/UnitTests/Intel/Decoder/DecoderTest64.txt
@@ -5336,11 +5336,11 @@ F3 4F 0F09, Wbnoinvd, Wbnoinvd, 0, enc=F30F09
 41 0F0D D9, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;r9d op1=r;ebx resnop
 44 0F0D EC, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esp op1=r;r13d resnop
 0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebx resnop
-0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebx
-0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esp
-0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebp
-0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esi
-0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;edi
+0F0D 18, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebx resnop
+0F0D 20, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esp resnop
+0F0D 28, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;ebp resnop
+0F0D 30, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;esi resnop
+0F0D 38, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=m;ds;rax;;1;0;0;UInt32 op1=r;edi resnop
 42 0F0D CE, ReservedNop_rm32_r32_0F0D, ReservedNop, 2, op0=r;esi op1=r;ecx resnop enc=0F0DCE
 
 48 0F0D CE, ReservedNop_rm64_r64_0F0D, ReservedNop, 2, op0=r;rsi op1=r;rcx resnop
@@ -5361,6 +5361,21 @@ F3 4F 0F09, Wbnoinvd, Wbnoinvd, 0, enc=F30F09
 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;rax;;1;0;0;UInt8
 44 0F0D 10, Prefetchwt1_m8, Prefetchwt1, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D10
 
+0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 18, PrefetchReserved3_m8, Prefetchw, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D18
+
+0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 20, PrefetchReserved4_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D20
+
+0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 28, PrefetchReserved5_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D28
+
+0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 30, PrefetchReserved6_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D30
+
+0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8
+44 0F0D 38, PrefetchReserved7_m8, Prefetch, 1, op0=m;ds;rax;;1;0;0;UInt8 enc=0F0D38
+
 0F0E, Femms, Femms, 0,
 4F 0F0E, Femms, Femms, 0, enc=0F0E
 
diff --git a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt
index eda7fb78c..097a6687b 100644
--- a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt
+++ b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt
@@ -907,6 +907,11 @@ ReservedNop_rm64_r64_0F0D, legacy, , 0F, 0D, REX.W 0F 0D /r, RESERVEDNOP r/m64|
 Prefetch_m8, legacy, , 0F, 0D, 0F 0D /0, PREFETCH m8, g=0 16b 32b 64b op=mem
 Prefetchw_m8, legacy, , 0F, 0D, 0F 0D /1, PREFETCHW m8, g=1 16b 32b 64b op=mem
 Prefetchwt1_m8, legacy, , 0F, 0D, 0F 0D /2, PREFETCHWT1 m8, g=2 16b 32b 64b op=mem
+PrefetchReserved3_m8, legacy, , 0F, 0D, 0F 0D /3, PREFETCHW m8, g=3 16b 32b 64b op=mem
+PrefetchReserved4_m8, legacy, , 0F, 0D, 0F 0D /4, PREFETCH m8, g=4 16b 32b 64b op=mem
+PrefetchReserved5_m8, legacy, , 0F, 0D, 0F 0D /5, PREFETCH m8, g=5 16b 32b 64b op=mem
+PrefetchReserved6_m8, legacy, , 0F, 0D, 0F 0D /6, PREFETCH m8, g=6 16b 32b 64b op=mem
+PrefetchReserved7_m8, legacy, , 0F, 0D, 0F 0D /7, PREFETCH m8, g=7 16b 32b 64b op=mem
 Femms, legacy, , 0F, 0E, 0F 0E, FEMMS, 16b 32b 64b
 Umov_rm8_r8, legacy, , 0F, 10, 0F 10 /r, UMOV r/m8| r8, 16b 32b op=r8_or_mem;r8_reg
 Umov_rm16_r16, legacy, , 0F, 11, o16 0F 11 /r, UMOV r/m16| r16, 16b 32b o16 op=r16_or_mem;r16_reg
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
index da43c7a9e..f002919bf 100644
--- a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
+++ b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 addr32 invlpgb
 invlpgb
 tlbsync
+prefetchw (rax)
+prefetch (rax)
+prefetch (rax)
+prefetch (rax)
+prefetch (rax)
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
index c0bbc90c7..0eb843552 100644
--- a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
+++ b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 addr32 invlpgb
 invlpgb
 tlbsync
+prefetchw (%rax)
+prefetch (%rax)
+prefetch (%rax)
+prefetch (%rax)
+prefetch (%rax)
diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos64.txt b/src/UnitTests/Intel/Formatter/InstructionInfos64.txt
index 80ecd0c75..cac068a79 100644
--- a/src/UnitTests/Intel/Formatter/InstructionInfos64.txt
+++ b/src/UnitTests/Intel/Formatter/InstructionInfos64.txt
@@ -8358,3 +8358,8 @@ F2 0F 01 E9, Xresldtrk
 67 0F 01 FE, Invlpgbd
 0F 01 FE, Invlpgbq
 0F 01 FF, Tlbsync
+0F0D 18, PrefetchReserved3_m8
+0F0D 20, PrefetchReserved4_m8
+0F0D 28, PrefetchReserved5_m8
+0F0D 30, PrefetchReserved6_m8
+0F0D 38, PrefetchReserved7_m8
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt
index 12a32f44b..4fe161681 100644
--- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt
+++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb eax
 invlpgb rax
 tlbsync
+prefetchw byte ptr [rax]
+prefetch_reserved byte ptr [rax]
+prefetch_reserved byte ptr [rax]
+prefetch_reserved byte ptr [rax]
+prefetch_reserved byte ptr [rax]
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt
index cf5495882..d0026a8ed 100644
--- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt
+++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb eax
 invlpgb rax
 tlbsync
+prefetchw [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt
index c170116fc..9078f43c9 100644
--- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt
+++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb eax
 invlpgb rax
 tlbsync
+prefetchw [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
+prefetch_reserved [rax]
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt
index 7a754252d..b7830f2ed 100644
--- a/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt
+++ b/src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb
 invlpgb
 tlbsync
+prefetchw byte ptr [rax]
+prefetch byte ptr [rax]
+prefetch byte ptr [rax]
+prefetch byte ptr [rax]
+prefetch byte ptr [rax]
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt
index 942630238..cbd7b7936 100644
--- a/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt
+++ b/src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt
index 0fa1238c4..2138125e8 100644
--- a/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt
+++ b/src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt
index cce2913e3..215844c16 100644
--- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt
+++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 a32 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt
index 31e300c1f..d37420c9f 100644
--- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt
+++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 a32 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt
index 713f846f4..f3bd5fb8b 100644
--- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt
+++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt
@@ -8358,3 +8358,8 @@ xresldtrk
 a32 invlpgb
 invlpgb
 tlbsync
+prefetchw [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
+prefetch [rax]
diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt
index 0f6c753e2..5981dbe62 100644
--- a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt
+++ b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt
@@ -1555,6 +1555,16 @@ C5ED FB CA, VEX_Vpsubq_ymm_ymm_ymmm256, VEX, AVX2, pm op0=w op1=n op2=n w=vmm1
 0F0D 08, Prefetchw_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
 # prefetchwt1 [eax]
 0F0D 10, Prefetchwt1_m8, Legacy, PREFETCHWT1, op0=nma r=eax;ds
+# prefetchw [eax]
+0F0D 18, PrefetchReserved3_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 20, PrefetchReserved4_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 28, PrefetchReserved5_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 30, PrefetchReserved6_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
+# prefetch [eax]
+0F0D 38, PrefetchReserved7_m8, Legacy, PREFETCHW, op0=nma r=eax;ds
 # prefetchnta [eax]
 0F18 00, Prefetchnta_m8, Legacy, SSE, op0=nma r=eax;ds
 # prefetcht0 [eax]
diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
index 35bd4e2a3..83bb33a14 100644
--- a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
+++ b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
@@ -2945,10 +2945,22 @@ FF 30, Push_rm64, Legacy, X64, op0=r rw=xsp r=rax rm=ds:rax;UInt64 wm=ss:xsp+0xF
 0F09, Wbinvd, Legacy, INTEL486, priv
 # ud2
 0F0B, Ud2, Legacy, INTEL286, flow=Exception
+# prefetch [rax]
+0F0D 00, Prefetch_m8, Legacy, PREFETCHW, op0=nma r=rax
 # prefetchw [rax]
 0F0D 08, Prefetchw_m8, Legacy, PREFETCHW, op0=nma r=rax
 # prefetchwt1 [rax]
 0F0D 10, Prefetchwt1_m8, Legacy, PREFETCHWT1, op0=nma r=rax
+# prefetchw [rax]
+0F0D 18, PrefetchReserved3_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 20, PrefetchReserved4_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 28, PrefetchReserved5_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 30, PrefetchReserved6_m8, Legacy, PREFETCHW, op0=nma r=rax
+# prefetch [rax]
+0F0D 38, PrefetchReserved7_m8, Legacy, PREFETCHW, op0=nma r=rax
 # movups xmm1,xmm5
 0F10 CD, Movups_xmm_xmmm128, Legacy, SSE, op0=w op1=r w=xmm1 r=xmm5
 # movups xmm1,[rax]
@@ -16485,8 +16497,6 @@ F3 0F01 FA, Mcommit, Legacy, MCOMMIT, fw=c fc=aopsz
 0F01 FC, Clzeroq, Legacy, CLZERO, r=rax
 # rdpru
 0F01 FD, Rdpru, Legacy, RDPRU, fw=c fc=aopsz r=ecx w=rax;rdx
-# prefetch [rax]
-0F0D 00, Prefetch_m8, Legacy, PREFETCHW, op0=nma r=rax
 # femms
 0F0E, Femms, Legacy, D3NOW,
 # movntss dword ptr [rax],xmm1
diff --git a/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs b/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs
index d06e94273..38341deae 100644
--- a/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs
+++ b/src/csharp/Intel/Generator/Assembler/AssemblerSyntaxGenerator.cs
@@ -151,6 +151,12 @@ protected AssemblerSyntaxGenerator(GenTypes genTypes) {
 
 				Code.Popw_CS,
 
+				Code.PrefetchReserved3_m8,
+				Code.PrefetchReserved4_m8,
+				Code.PrefetchReserved5_m8,
+				Code.PrefetchReserved6_m8,
+				Code.PrefetchReserved7_m8,
+
 				// The following are implemented manually
 				Code.Call_ptr1616,
 				Code.Call_ptr1632,
diff --git a/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs b/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs
index dc03a4370..d7ee98d29 100644
--- a/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs
+++ b/src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs
@@ -1864,11 +1864,11 @@ public static (string name, object?[] handlers)[] CreateHandlers(GenTypes genTyp
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.Prefetch_m8)] },
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.Prefetchw_m8)] },
 					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.Prefetchwt1_m8)] },
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
-					"reservedNop_0F0D",
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved3_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved4_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved5_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved6_m8)] },
+					new object[] { legacyEnum[nameof(OpCodeHandlerKind.M_1)], codeEnum[nameof(Code.PrefetchReserved7_m8)] },
 				}),
 				("grp0F0D", new object[] { legacyEnum[nameof(OpCodeHandlerKind.RM)],
 					"reservedNop_0F0D",
diff --git a/src/csharp/Intel/Generator/Enums/Code.cs b/src/csharp/Intel/Generator/Enums/Code.cs
index 3ddbb8b07..8e4dde24f 100644
--- a/src/csharp/Intel/Generator/Enums/Code.cs
+++ b/src/csharp/Intel/Generator/Enums/Code.cs
@@ -4247,6 +4247,11 @@ enum Code {
 		Invlpgbd,
 		Invlpgbq,
 		Tlbsync,
+		PrefetchReserved3_m8,
+		PrefetchReserved4_m8,
+		PrefetchReserved5_m8,
+		PrefetchReserved6_m8,
+		PrefetchReserved7_m8,
 	}
 
 	[TypeGen(TypeGenOrders.CreatedInstructions)]
diff --git a/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs
index f485535d6..075a9364b 100644
--- a/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs
+++ b/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs
@@ -4252,6 +4252,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbd)], "invlpgb", 32 },
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbq)], "invlpgb", 64 },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch" },
 			});
 		}
 	}
diff --git a/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs
index d4092ffb1..d030897d4 100644
--- a/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs
+++ b/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs
@@ -4252,6 +4252,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.reg)], code[nameof(Code.Invlpgbd)], "invlpgb", register[nameof(Register.EAX)] },
 				new object[] { ctorKind[nameof(CtorKind.reg)], code[nameof(Code.Invlpgbq)], "invlpgb", register[nameof(Register.RAX)] },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch_reserved" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch_reserved" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch_reserved" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch_reserved" },
 			});
 		}
 	}
diff --git a/src/csharp/Intel/Generator/Formatters/Masm/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Masm/CtorInfosData.cs
index b5ff2397f..c333e6d9c 100644
--- a/src/csharp/Intel/Generator/Formatters/Masm/CtorInfosData.cs
+++ b/src/csharp/Intel/Generator/Formatters/Masm/CtorInfosData.cs
@@ -4252,6 +4252,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Invlpgbd)], "invlpgb" },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Invlpgbq)], "invlpgb" },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch" },
 			});
 		}
 	}
diff --git a/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs
index e5492a729..b8ff37a8a 100644
--- a/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs
+++ b/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs
@@ -4254,6 +4254,11 @@ public static object[][] GetData(GenTypes genTypes) {
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbd)], "invlpgb", 32 },
 				new object[] { ctorKind[nameof(CtorKind.asz)], code[nameof(Code.Invlpgbq)], "invlpgb", 64 },
 				new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Tlbsync)], "tlbsync" },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved3_m8)], "prefetchw", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved4_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved5_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved6_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
+				new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.PrefetchReserved7_m8)], "prefetch", instrOpInfoFlags[nameof(InstrOpInfoFlags.MemSize_Nothing)] },
 			});
 		}
 	}
diff --git a/src/csharp/Intel/Generator/Tables/InstructionDefsData.cs b/src/csharp/Intel/Generator/Tables/InstructionDefsData.cs
index 30c7f56c1..1dd1438df 100644
--- a/src/csharp/Intel/Generator/Tables/InstructionDefsData.cs
+++ b/src/csharp/Intel/Generator/Tables/InstructionDefsData.cs
@@ -12687,6 +12687,21 @@ public static InstructionDef[] CreateTable(GenTypes genTypes) {
 				(0, mnemonic[nameof(Mnemonic.Tlbsync)], memSize[nameof(MemorySize.Unknown)], memSize[nameof(MemorySize.Unknown)],
 				new LegacyOpCodeInfo(code[nameof(Code.Tlbsync)], MandatoryPrefix.PNP, OpCodeTableKind.T0F, 0x01FF, -1, OperandSize.None, AddressSize.None, OpCodeFlags.Mode16 | OpCodeFlags.Mode32 | OpCodeFlags.Mode64, Array.Empty<LegacyOpKind>()),
 				new InstrInfo(code[nameof(Code.Tlbsync)], CodeInfo.None, encoding[nameof(EncodingKind.Legacy)], flowControl[nameof(FlowControl.Next)], RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, new[] { cpuid[nameof(CpuidFeature.INVLPGB)] }, Array.Empty<OpInfo>(), InstrInfoFlags.ProtectedMode | InstrInfoFlags.Privileged)),
+				(1, mnemonic[nameof(Mnemonic.Prefetchw)], memSize[nameof(MemorySize.UInt8)], memSize[nameof(MemorySize.Unknown)],
+				new LegacyOpCodeInfo(code[nameof(Code.PrefetchReserved3_m8)], MandatoryPrefix.None, OpCodeTableKind.T0F, 0x0D, 3, OperandSize.None, AddressSize.None, OpCodeFlags.Mode16 | OpCodeFlags.Mode32 | OpCodeFlags.Mode64, new[] { LegacyOpKind.Mb }),
+				new InstrInfo(code[nameof(Code.PrefetchReserved3_m8)], CodeInfo.None, encoding[nameof(EncodingKind.Legacy)], flowControl[nameof(FlowControl.Next)], RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, new[] { cpuid[nameof(CpuidFeature.PREFETCHW)] }, new[] { OpInfo.NoMemAccess }, InstrInfoFlags.None)),
+				(1, mnemonic[nameof(Mnemonic.Prefetch)], memSize[nameof(MemorySize.UInt8)], memSize[nameof(MemorySize.Unknown)],
+				new LegacyOpCodeInfo(code[nameof(Code.PrefetchReserved4_m8)], MandatoryPrefix.None, OpCodeTableKind.T0F, 0x0D, 4, OperandSize.None, AddressSize.None, OpCodeFlags.Mode16 | OpCodeFlags.Mode32 | OpCodeFlags.Mode64, new[] { LegacyOpKind.Mb }),
+				new InstrInfo(code[nameof(Code.PrefetchReserved4_m8)], CodeInfo.None, encoding[nameof(EncodingKind.Legacy)], flowControl[nameof(FlowControl.Next)], RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, new[] { cpuid[nameof(CpuidFeature.PREFETCHW)] }, new[] { OpInfo.NoMemAccess }, InstrInfoFlags.None)),
+				(1, mnemonic[nameof(Mnemonic.Prefetch)], memSize[nameof(MemorySize.UInt8)], memSize[nameof(MemorySize.Unknown)],
+				new LegacyOpCodeInfo(code[nameof(Code.PrefetchReserved5_m8)], MandatoryPrefix.None, OpCodeTableKind.T0F, 0x0D, 5, OperandSize.None, AddressSize.None, OpCodeFlags.Mode16 | OpCodeFlags.Mode32 | OpCodeFlags.Mode64, new[] { LegacyOpKind.Mb }),
+				new InstrInfo(code[nameof(Code.PrefetchReserved5_m8)], CodeInfo.None, encoding[nameof(EncodingKind.Legacy)], flowControl[nameof(FlowControl.Next)], RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, new[] { cpuid[nameof(CpuidFeature.PREFETCHW)] }, new[] { OpInfo.NoMemAccess }, InstrInfoFlags.None)),
+				(1, mnemonic[nameof(Mnemonic.Prefetch)], memSize[nameof(MemorySize.UInt8)], memSize[nameof(MemorySize.Unknown)],
+				new LegacyOpCodeInfo(code[nameof(Code.PrefetchReserved6_m8)], MandatoryPrefix.None, OpCodeTableKind.T0F, 0x0D, 6, OperandSize.None, AddressSize.None, OpCodeFlags.Mode16 | OpCodeFlags.Mode32 | OpCodeFlags.Mode64, new[] { LegacyOpKind.Mb }),
+				new InstrInfo(code[nameof(Code.PrefetchReserved6_m8)], CodeInfo.None, encoding[nameof(EncodingKind.Legacy)], flowControl[nameof(FlowControl.Next)], RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, new[] { cpuid[nameof(CpuidFeature.PREFETCHW)] }, new[] { OpInfo.NoMemAccess }, InstrInfoFlags.None)),
+				(1, mnemonic[nameof(Mnemonic.Prefetch)], memSize[nameof(MemorySize.UInt8)], memSize[nameof(MemorySize.Unknown)],
+				new LegacyOpCodeInfo(code[nameof(Code.PrefetchReserved7_m8)], MandatoryPrefix.None, OpCodeTableKind.T0F, 0x0D, 7, OperandSize.None, AddressSize.None, OpCodeFlags.Mode16 | OpCodeFlags.Mode32 | OpCodeFlags.Mode64, new[] { LegacyOpKind.Mb }),
+				new InstrInfo(code[nameof(Code.PrefetchReserved7_m8)], CodeInfo.None, encoding[nameof(EncodingKind.Legacy)], flowControl[nameof(FlowControl.Next)], RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, RflagsBits.None, new[] { cpuid[nameof(CpuidFeature.PREFETCHW)] }, new[] { OpInfo.NoMemAccess }, InstrInfoFlags.None)),
 			};
 
 			if (result.Length != code.Values.Length)
diff --git a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs
index 5ed5df9b7..29cddb759 100644
--- a/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs
+++ b/src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs
@@ -35,7 +35,7 @@ static partial class ToEnumConverter {
 		static readonly Dictionary<string, Code> codeDict =
 			// GENERATOR-BEGIN: CodeHash
 			// ⚠️This was generated by GENERATOR!🦹‍♂️
-			new Dictionary<string, Code>(4216, StringComparer.Ordinal) {
+			new Dictionary<string, Code>(4221, StringComparer.Ordinal) {
 				{ "INVALID", Code.INVALID },
 				{ "DeclareByte", Code.DeclareByte },
 				{ "DeclareWord", Code.DeclareWord },
@@ -4252,6 +4252,11 @@ static partial class ToEnumConverter {
 				{ "Invlpgbd", Code.Invlpgbd },
 				{ "Invlpgbq", Code.Invlpgbq },
 				{ "Tlbsync", Code.Tlbsync },
+				{ "PrefetchReserved3_m8", Code.PrefetchReserved3_m8 },
+				{ "PrefetchReserved4_m8", Code.PrefetchReserved4_m8 },
+				{ "PrefetchReserved5_m8", Code.PrefetchReserved5_m8 },
+				{ "PrefetchReserved6_m8", Code.PrefetchReserved6_m8 },
+				{ "PrefetchReserved7_m8", Code.PrefetchReserved7_m8 },
 			};
 			// GENERATOR-END: CodeHash
 	}
diff --git a/src/csharp/Intel/Iced/Intel/Code.g.cs b/src/csharp/Intel/Iced/Intel/Code.g.cs
index a534dca6c..28f824e6f 100644
--- a/src/csharp/Intel/Iced/Intel/Code.g.cs
+++ b/src/csharp/Intel/Iced/Intel/Code.g.cs
@@ -33726,5 +33726,45 @@ public enum Code {
 		/// <br/>
 		/// <c>16/32/64-bit</c></summary>
 		Tlbsync = 4215,
+		/// <summary><c>PREFETCHW m8</c><br/>
+		/// <br/>
+		/// <c>0F 0D /3</c><br/>
+		/// <br/>
+		/// <c>PREFETCHW</c><br/>
+		/// <br/>
+		/// <c>16/32/64-bit</c></summary>
+		PrefetchReserved3_m8 = 4216,
+		/// <summary><c>PREFETCH m8</c><br/>
+		/// <br/>
+		/// <c>0F 0D /4</c><br/>
+		/// <br/>
+		/// <c>PREFETCHW</c><br/>
+		/// <br/>
+		/// <c>16/32/64-bit</c></summary>
+		PrefetchReserved4_m8 = 4217,
+		/// <summary><c>PREFETCH m8</c><br/>
+		/// <br/>
+		/// <c>0F 0D /5</c><br/>
+		/// <br/>
+		/// <c>PREFETCHW</c><br/>
+		/// <br/>
+		/// <c>16/32/64-bit</c></summary>
+		PrefetchReserved5_m8 = 4218,
+		/// <summary><c>PREFETCH m8</c><br/>
+		/// <br/>
+		/// <c>0F 0D /6</c><br/>
+		/// <br/>
+		/// <c>PREFETCHW</c><br/>
+		/// <br/>
+		/// <c>16/32/64-bit</c></summary>
+		PrefetchReserved6_m8 = 4219,
+		/// <summary><c>PREFETCH m8</c><br/>
+		/// <br/>
+		/// <c>0F 0D /7</c><br/>
+		/// <br/>
+		/// <c>PREFETCHW</c><br/>
+		/// <br/>
+		/// <c>16/32/64-bit</c></summary>
+		PrefetchReserved7_m8 = 4220,
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs
index ee2d065c8..3807c2f0f 100644
--- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs
+++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs
@@ -2553,10 +2553,24 @@ static byte[] GetSerializedTables() =>
 					0xF5, 0x06,// Prefetchwt1_m8
 
 				// 3 = 0x03
-				0x05,// Dup
-					0x05,// 5
-					0x07,// HandlerReference
-						0x31,// 0x31 = reservedNop_0F0D
+				0x6E,// M_1
+					0xF8, 0x20,// PrefetchReserved3_m8
+
+				// 4 = 0x04
+				0x6E,// M_1
+					0xF9, 0x20,// PrefetchReserved4_m8
+
+				// 5 = 0x05
+				0x6E,// M_1
+					0xFA, 0x20,// PrefetchReserved5_m8
+
+				// 6 = 0x06
+				0x6E,// M_1
+					0xFB, 0x20,// PrefetchReserved6_m8
+
+				// 7 = 0x07
+				0x6E,// M_1
+					0xFC, 0x20,// PrefetchReserved7_m8
 
 				// grp0F0D
 				0x00,// HandlerReference
diff --git a/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeHandlers.Data.g.cs b/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeHandlers.Data.g.cs
index a1a79b923..c912ffc12 100644
--- a/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeHandlers.Data.g.cs
+++ b/src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeHandlers.Data.g.cs
@@ -29,7 +29,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 namespace Iced.Intel.EncoderInternal {
 	static partial class OpCodeHandlers {
 		public static uint[] GetData() =>
-			new uint[4216 * 3] {
+			new uint[4221 * 3] {
 				0x00000000, 0x00000000, 0x00000000,// INVALID
 				0x00000000, 0x00000000, 0x00000000,// DeclareByte
 				0x00000000, 0x00000000, 0x00000000,// DeclareWord
@@ -4246,6 +4246,11 @@ public static uint[] GetData() =>
 				0x01FE0000, 0x00088004, 0x00000000,// Invlpgbd
 				0x01FE0000, 0x00008024, 0x00000000,// Invlpgbq
 				0x01FF0000, 0x00008004, 0x00000000,// Tlbsync
+				0x000D0000, 0x000001C4, 0x00000012,// PrefetchReserved3_m8
+				0x000D0000, 0x00000244, 0x00000012,// PrefetchReserved4_m8
+				0x000D0000, 0x000002C4, 0x00000012,// PrefetchReserved5_m8
+				0x000D0000, 0x00000344, 0x00000012,// PrefetchReserved6_m8
+				0x000D0000, 0x000003C4, 0x00000012,// PrefetchReserved7_m8
 			};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs b/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs
index d875f9124..4418629ec 100644
--- a/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs
+++ b/src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs
@@ -29,7 +29,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 namespace Iced.Intel.FormatterInternal {
 	static partial class FormatterStringsTable {
 		const int MaxStringLength = 18;
-		const int StringsCount = 1409;
+		const int StringsCount = 1410;
 #if HAS_SPAN
 		static System.ReadOnlySpan<byte> GetSerializedStrings() =>
 #else
@@ -1445,6 +1445,7 @@ static byte[] GetSerializedStrings() =>
 				0x09, 0x78, 0x72, 0x65, 0x73, 0x6C, 0x64, 0x74, 0x72, 0x6B,// xresldtrk
 				0x07, 0x69, 0x6E, 0x76, 0x6C, 0x70, 0x67, 0x62,// invlpgb
 				0x07, 0x74, 0x6C, 0x62, 0x73, 0x79, 0x6E, 0x63,// tlbsync
+				0x11, 0x70, 0x72, 0x65, 0x66, 0x65, 0x74, 0x63, 0x68, 0x5F, 0x72, 0x65, 0x73, 0x65, 0x72, 0x76, 0x65, 0x64,// prefetch_reserved
 			};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs
index 5449d2663..3d59a91b4 100644
--- a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs
+++ b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs
@@ -17521,6 +17521,23 @@ static byte[] GetSerializedInstrInfos() =>
 				// Tlbsync
 				0x01,// Normal_1
 				0x80, 0x0B,// 1408 = "tlbsync"
+
+				// PrefetchReserved3_m8
+				0x01,// Normal_1
+				0xBD, 0x03,// 445 = "prefetchw"
+
+				// PrefetchReserved4_m8
+				0x01,// Normal_1
+				0xBB, 0x03,// 443 = "prefetch"
+
+				// PrefetchReserved5_m8
+				0x00,// Previous
+
+				// PrefetchReserved6_m8
+				0x00,// Previous
+
+				// PrefetchReserved7_m8
+				0x00,// Previous
 			};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs b/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs
index 942d6b4dd..a60b9f28e 100644
--- a/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs
+++ b/src/csharp/Intel/Iced/Intel/IcedConstants.g.cs
@@ -30,7 +30,7 @@ static class IcedConstants {
 		internal const int MaxOpCount = 5;
 		internal const int MaxInstructionLength = 15;
 		internal const int RegisterBits = 8;
-		internal const int NumberOfCodeValues = 4216;
+		internal const int NumberOfCodeValues = 4221;
 		internal const int NumberOfRegisters = 241;
 		internal const int NumberOfMemorySizes = 136;
 		internal const int NumberOfEncodingKinds = 5;
diff --git a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs
index 9de811a4d..0353f5b0b 100644
--- a/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs
+++ b/src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs
@@ -28,7 +28,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #if INSTR_INFO
 namespace Iced.Intel.InstructionInfoInternal {
 	static class InstrInfoTable {
-		internal static readonly uint[] Data = new uint[8432] {
+		internal static readonly uint[] Data = new uint[8442] {
 			0x00000000, 0x00900000,// INVALID
 			0x00000000, 0x00900000,// DeclareByte
 			0x00000000, 0x00900000,// DeclareWord
@@ -4245,6 +4245,11 @@ static class InstrInfoTable {
 			0x66500000, 0x98000000,// Invlpgbd
 			0x66500000, 0x98000000,// Invlpgbq
 			0x60000000, 0x98000000,// Tlbsync
+			0x00000003, 0x6B000000,// PrefetchReserved3_m8
+			0x00000003, 0x6B000000,// PrefetchReserved4_m8
+			0x00000003, 0x6B000000,// PrefetchReserved5_m8
+			0x00000003, 0x6B000000,// PrefetchReserved6_m8
+			0x00000003, 0x6B000000,// PrefetchReserved7_m8
 		};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs b/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs
index 2932e6288..0319a8bb1 100644
--- a/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs
+++ b/src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs
@@ -4250,6 +4250,11 @@ static class InstructionMemorySizes {
 			0,// Invlpgbd
 			0,// Invlpgbq
 			0,// Tlbsync
+			(byte)MemorySize.UInt8,// PrefetchReserved3_m8
+			(byte)MemorySize.UInt8,// PrefetchReserved4_m8
+			(byte)MemorySize.UInt8,// PrefetchReserved5_m8
+			(byte)MemorySize.UInt8,// PrefetchReserved6_m8
+			(byte)MemorySize.UInt8,// PrefetchReserved7_m8
 			0,// INVALID
 			0,// DeclareByte
 			0,// DeclareWord
@@ -8466,6 +8471,11 @@ static class InstructionMemorySizes {
 			0,// Invlpgbd
 			0,// Invlpgbq
 			0,// Tlbsync
+			0,// PrefetchReserved3_m8
+			0,// PrefetchReserved4_m8
+			0,// PrefetchReserved5_m8
+			0,// PrefetchReserved6_m8
+			0,// PrefetchReserved7_m8
 		};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs b/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs
index 02058abdf..77b7971e6 100644
--- a/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs
+++ b/src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs
@@ -4248,6 +4248,11 @@ static class InstructionOpCounts {
 			0,// Invlpgbd
 			0,// Invlpgbq
 			0,// Tlbsync
+			1,// PrefetchReserved3_m8
+			1,// PrefetchReserved4_m8
+			1,// PrefetchReserved5_m8
+			1,// PrefetchReserved6_m8
+			1,// PrefetchReserved7_m8
 		};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs
index 6ee175f7b..e26d6e9c8 100644
--- a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs
+++ b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs
@@ -15670,6 +15670,23 @@ static byte[] GetSerializedInstrInfos() =>
 				// Tlbsync
 				0x01,// Normal_1
 				0x80, 0x0B,// 1408 = "tlbsync"
+
+				// PrefetchReserved3_m8
+				0x01,// Normal_1
+				0xBD, 0x03,// 445 = "prefetchw"
+
+				// PrefetchReserved4_m8
+				0x01,// Normal_1
+				0x81, 0x0B,// 1409 = "prefetch_reserved"
+
+				// PrefetchReserved5_m8
+				0x00,// Previous
+
+				// PrefetchReserved6_m8
+				0x00,// Previous
+
+				// PrefetchReserved7_m8
+				0x00,// Previous
 			};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs
index 0b0647464..c58235ec6 100644
--- a/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs
+++ b/src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs
@@ -15717,6 +15717,23 @@ static byte[] GetSerializedInstrInfos() =>
 				// Tlbsync
 				0x01,// Normal_1
 				0x80, 0x0B,// 1408 = "tlbsync"
+
+				// PrefetchReserved3_m8
+				0x01,// Normal_1
+				0xBD, 0x03,// 445 = "prefetchw"
+
+				// PrefetchReserved4_m8
+				0x01,// Normal_1
+				0xBB, 0x03,// 443 = "prefetch"
+
+				// PrefetchReserved5_m8
+				0x00,// Previous
+
+				// PrefetchReserved6_m8
+				0x00,// Previous
+
+				// PrefetchReserved7_m8
+				0x00,// Previous
 			};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs b/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs
index 83c22ae57..dd80cc361 100644
--- a/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs
+++ b/src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs
@@ -4244,6 +4244,11 @@ static class MnemonicUtilsData {
 			(ushort)Mnemonic.Invlpgb,// Invlpgbd
 			(ushort)Mnemonic.Invlpgb,// Invlpgbq
 			(ushort)Mnemonic.Tlbsync,// Tlbsync
+			(ushort)Mnemonic.Prefetchw,// PrefetchReserved3_m8
+			(ushort)Mnemonic.Prefetch,// PrefetchReserved4_m8
+			(ushort)Mnemonic.Prefetch,// PrefetchReserved5_m8
+			(ushort)Mnemonic.Prefetch,// PrefetchReserved6_m8
+			(ushort)Mnemonic.Prefetch,// PrefetchReserved7_m8
 		};
 	}
 }
diff --git a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs
index 3ca0e454b..0dde7f504 100644
--- a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs
+++ b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs
@@ -16369,6 +16369,25 @@ static byte[] GetSerializedInstrInfos() =>
 				// Tlbsync
 				0x01,// Normal_1
 				0x80, 0x0B,// 1408 = "tlbsync"
+
+				// PrefetchReserved3_m8
+				0x02,// Normal_2
+				0xBD, 0x03,// 445 = "prefetchw"
+				0x01,// 0x1 = MemSize_Nothing
+
+				// PrefetchReserved4_m8
+				0x02,// Normal_2
+				0xBB, 0x03,// 443 = "prefetch"
+				0x01,// 0x1 = MemSize_Nothing
+
+				// PrefetchReserved5_m8
+				0x00,// Previous
+
+				// PrefetchReserved6_m8
+				0x00,// Previous
+
+				// PrefetchReserved7_m8
+				0x00,// Previous
 			};
 	}
 }
diff --git a/src/rust/iced-x86-js/src/code.rs b/src/rust/iced-x86-js/src/code.rs
index 04d1da6f7..adf16733f 100644
--- a/src/rust/iced-x86-js/src/code.rs
+++ b/src/rust/iced-x86-js/src/code.rs
@@ -4247,6 +4247,11 @@ pub enum Code {
 	Invlpgbd = 4213,
 	Invlpgbq = 4214,
 	Tlbsync = 4215,
+	PrefetchReserved3_m8 = 4216,
+	PrefetchReserved4_m8 = 4217,
+	PrefetchReserved5_m8 = 4218,
+	PrefetchReserved6_m8 = 4219,
+	PrefetchReserved7_m8 = 4220,
 }
 // GENERATOR-END: Enum
 
diff --git a/src/rust/iced-x86/src/code.rs b/src/rust/iced-x86/src/code.rs
index 4e4f738ba..1214e40e7 100644
--- a/src/rust/iced-x86/src/code.rs
+++ b/src/rust/iced-x86/src/code.rs
@@ -33734,9 +33734,49 @@ pub enum Code {
 	///
 	/// `16/32/64-bit`
 	Tlbsync = 4215,
+	/// `PREFETCHW m8`
+	///
+	/// `0F 0D /3`
+	///
+	/// `PREFETCHW`
+	///
+	/// `16/32/64-bit`
+	PrefetchReserved3_m8 = 4216,
+	/// `PREFETCH m8`
+	///
+	/// `0F 0D /4`
+	///
+	/// `PREFETCHW`
+	///
+	/// `16/32/64-bit`
+	PrefetchReserved4_m8 = 4217,
+	/// `PREFETCH m8`
+	///
+	/// `0F 0D /5`
+	///
+	/// `PREFETCHW`
+	///
+	/// `16/32/64-bit`
+	PrefetchReserved5_m8 = 4218,
+	/// `PREFETCH m8`
+	///
+	/// `0F 0D /6`
+	///
+	/// `PREFETCHW`
+	///
+	/// `16/32/64-bit`
+	PrefetchReserved6_m8 = 4219,
+	/// `PREFETCH m8`
+	///
+	/// `0F 0D /7`
+	///
+	/// `PREFETCHW`
+	///
+	/// `16/32/64-bit`
+	PrefetchReserved7_m8 = 4220,
 }
 #[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
-static GEN_DEBUG_CODE: [&str; 4216] = [
+static GEN_DEBUG_CODE: [&str; 4221] = [
 	"INVALID",
 	"DeclareByte",
 	"DeclareWord",
@@ -37953,6 +37993,11 @@ static GEN_DEBUG_CODE: [&str; 4216] = [
 	"Invlpgbd",
 	"Invlpgbq",
 	"Tlbsync",
+	"PrefetchReserved3_m8",
+	"PrefetchReserved4_m8",
+	"PrefetchReserved5_m8",
+	"PrefetchReserved6_m8",
+	"PrefetchReserved7_m8",
 ];
 impl fmt::Debug for Code {
 	#[inline]
diff --git a/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs b/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs
index 43f92f01c..799784e90 100644
--- a/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs
+++ b/src/rust/iced-x86/src/decoder/table_de/data_legacy.rs
@@ -2544,10 +2544,24 @@ pub(super) static TBL_DATA: &[u8] = &[
 		0xF5, 0x06,// Prefetchwt1_m8
 
 	// 3 = 0x03
-	0x05,// Dup
-		0x05,// 5
-		0x07,// HandlerReference
-			0x31,// 0x31 = reservedNop_0F0D
+	0x6E,// M_1
+		0xF8, 0x20,// PrefetchReserved3_m8
+
+	// 4 = 0x04
+	0x6E,// M_1
+		0xF9, 0x20,// PrefetchReserved4_m8
+
+	// 5 = 0x05
+	0x6E,// M_1
+		0xFA, 0x20,// PrefetchReserved5_m8
+
+	// 6 = 0x06
+	0x6E,// M_1
+		0xFB, 0x20,// PrefetchReserved6_m8
+
+	// 7 = 0x07
+	0x6E,// M_1
+		0xFC, 0x20,// PrefetchReserved7_m8
 
 	// grp0F0D
 	0x00,// HandlerReference
diff --git a/src/rust/iced-x86/src/encoder/op_code_data.rs b/src/rust/iced-x86/src/encoder/op_code_data.rs
index af54e82ad..ba248d8ce 100644
--- a/src/rust/iced-x86/src/encoder/op_code_data.rs
+++ b/src/rust/iced-x86/src/encoder/op_code_data.rs
@@ -24,7 +24,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 // ⚠️This file was generated by GENERATOR!🦹‍♂️
 
 #[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
-pub(super) static OP_CODE_DATA: [u32; 4216 * 3] = [
+pub(super) static OP_CODE_DATA: [u32; 4221 * 3] = [
 	0x0000_0000, 0x0000_0000, 0x0000_0000,// INVALID
 	0x0000_0000, 0x0000_0000, 0x0000_0000,// DeclareByte
 	0x0000_0000, 0x0000_0000, 0x0000_0000,// DeclareWord
@@ -4241,4 +4241,9 @@ pub(super) static OP_CODE_DATA: [u32; 4216 * 3] = [
 	0x01FE_0000, 0x0008_8004, 0x0000_0000,// Invlpgbd
 	0x01FE_0000, 0x0000_8024, 0x0000_0000,// Invlpgbq
 	0x01FF_0000, 0x0000_8004, 0x0000_0000,// Tlbsync
+	0x000D_0000, 0x0000_01C4, 0x0000_0012,// PrefetchReserved3_m8
+	0x000D_0000, 0x0000_0244, 0x0000_0012,// PrefetchReserved4_m8
+	0x000D_0000, 0x0000_02C4, 0x0000_0012,// PrefetchReserved5_m8
+	0x000D_0000, 0x0000_0344, 0x0000_0012,// PrefetchReserved6_m8
+	0x000D_0000, 0x0000_03C4, 0x0000_0012,// PrefetchReserved7_m8
 ];
diff --git a/src/rust/iced-x86/src/formatter/gas/fmt_data.rs b/src/rust/iced-x86/src/formatter/gas/fmt_data.rs
index 52a04b6ff..d13827a1c 100644
--- a/src/rust/iced-x86/src/formatter/gas/fmt_data.rs
+++ b/src/rust/iced-x86/src/formatter/gas/fmt_data.rs
@@ -17512,4 +17512,21 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
 	// Tlbsync
 	0x01,// Normal_1
 	0x80, 0x0B,// 1408 = "tlbsync"
+
+	// PrefetchReserved3_m8
+	0x01,// Normal_1
+	0xBD, 0x03,// 445 = "prefetchw"
+
+	// PrefetchReserved4_m8
+	0x01,// Normal_1
+	0xBB, 0x03,// 443 = "prefetch"
+
+	// PrefetchReserved5_m8
+	0x00,// Previous
+
+	// PrefetchReserved6_m8
+	0x00,// Previous
+
+	// PrefetchReserved7_m8
+	0x00,// Previous
 ];
diff --git a/src/rust/iced-x86/src/formatter/intel/fmt_data.rs b/src/rust/iced-x86/src/formatter/intel/fmt_data.rs
index d15456560..8ee819bd5 100644
--- a/src/rust/iced-x86/src/formatter/intel/fmt_data.rs
+++ b/src/rust/iced-x86/src/formatter/intel/fmt_data.rs
@@ -15661,4 +15661,21 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
 	// Tlbsync
 	0x01,// Normal_1
 	0x80, 0x0B,// 1408 = "tlbsync"
+
+	// PrefetchReserved3_m8
+	0x01,// Normal_1
+	0xBD, 0x03,// 445 = "prefetchw"
+
+	// PrefetchReserved4_m8
+	0x01,// Normal_1
+	0x81, 0x0B,// 1409 = "prefetch_reserved"
+
+	// PrefetchReserved5_m8
+	0x00,// Previous
+
+	// PrefetchReserved6_m8
+	0x00,// Previous
+
+	// PrefetchReserved7_m8
+	0x00,// Previous
 ];
diff --git a/src/rust/iced-x86/src/formatter/masm/fmt_data.rs b/src/rust/iced-x86/src/formatter/masm/fmt_data.rs
index 53902847f..b0b6dcaee 100644
--- a/src/rust/iced-x86/src/formatter/masm/fmt_data.rs
+++ b/src/rust/iced-x86/src/formatter/masm/fmt_data.rs
@@ -15708,4 +15708,21 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
 	// Tlbsync
 	0x01,// Normal_1
 	0x80, 0x0B,// 1408 = "tlbsync"
+
+	// PrefetchReserved3_m8
+	0x01,// Normal_1
+	0xBD, 0x03,// 445 = "prefetchw"
+
+	// PrefetchReserved4_m8
+	0x01,// Normal_1
+	0xBB, 0x03,// 443 = "prefetch"
+
+	// PrefetchReserved5_m8
+	0x00,// Previous
+
+	// PrefetchReserved6_m8
+	0x00,// Previous
+
+	// PrefetchReserved7_m8
+	0x00,// Previous
 ];
diff --git a/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs b/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs
index 3e1496e70..18a267ba0 100644
--- a/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs
+++ b/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs
@@ -16360,4 +16360,23 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
 	// Tlbsync
 	0x01,// Normal_1
 	0x80, 0x0B,// 1408 = "tlbsync"
+
+	// PrefetchReserved3_m8
+	0x02,// Normal_2
+	0xBD, 0x03,// 445 = "prefetchw"
+	0x01,// 0x1 = MemSize_Nothing
+
+	// PrefetchReserved4_m8
+	0x02,// Normal_2
+	0xBB, 0x03,// 443 = "prefetch"
+	0x01,// 0x1 = MemSize_Nothing
+
+	// PrefetchReserved5_m8
+	0x00,// Previous
+
+	// PrefetchReserved6_m8
+	0x00,// Previous
+
+	// PrefetchReserved7_m8
+	0x00,// Previous
 ];
diff --git a/src/rust/iced-x86/src/formatter/strings_data.rs b/src/rust/iced-x86/src/formatter/strings_data.rs
index 30c0eb648..88acce778 100644
--- a/src/rust/iced-x86/src/formatter/strings_data.rs
+++ b/src/rust/iced-x86/src/formatter/strings_data.rs
@@ -23,10 +23,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 // ⚠️This file was generated by GENERATOR!🦹‍♂️
 
-pub(super) const STRINGS_COUNT: usize = 1409;
+pub(super) const STRINGS_COUNT: usize = 1410;
 
 #[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
-pub(super) static STRINGS_TBL_DATA: [u8; 10790] = [
+pub(super) static STRINGS_TBL_DATA: [u8; 10808] = [
 	0x03, 0x6D, 0x6F, 0x76,// mov
 	0x0C, 0x72, 0x65, 0x73, 0x65, 0x72, 0x76, 0x65, 0x64, 0x2D, 0x6E, 0x6F, 0x70,// reserved-nop
 	0x04, 0x70, 0x75, 0x73, 0x68,// push
@@ -1436,4 +1436,5 @@ pub(super) static STRINGS_TBL_DATA: [u8; 10790] = [
 	0x09, 0x78, 0x72, 0x65, 0x73, 0x6C, 0x64, 0x74, 0x72, 0x6B,// xresldtrk
 	0x07, 0x69, 0x6E, 0x76, 0x6C, 0x70, 0x67, 0x62,// invlpgb
 	0x07, 0x74, 0x6C, 0x62, 0x73, 0x79, 0x6E, 0x63,// tlbsync
+	0x11, 0x70, 0x72, 0x65, 0x66, 0x65, 0x74, 0x63, 0x68, 0x5F, 0x72, 0x65, 0x73, 0x65, 0x72, 0x76, 0x65, 0x64,// prefetch_reserved
 ];
diff --git a/src/rust/iced-x86/src/iced_constants.rs b/src/rust/iced-x86/src/iced_constants.rs
index 8e2d11602..79367a968 100644
--- a/src/rust/iced-x86/src/iced_constants.rs
+++ b/src/rust/iced-x86/src/iced_constants.rs
@@ -31,7 +31,7 @@ impl IcedConstants {
 	pub(crate) const MAX_OP_COUNT: usize = 5;
 	pub(crate) const MAX_INSTRUCTION_LENGTH: usize = 15;
 	pub(crate) const REGISTER_BITS: u32 = 8;
-	pub(crate) const NUMBER_OF_CODE_VALUES: usize = 4216;
+	pub(crate) const NUMBER_OF_CODE_VALUES: usize = 4221;
 	pub(crate) const NUMBER_OF_REGISTERS: usize = 241;
 	pub(crate) const NUMBER_OF_MEMORY_SIZES: usize = 136;
 	pub(crate) const NUMBER_OF_ENCODING_KINDS: usize = 5;
diff --git a/src/rust/iced-x86/src/info/info_table.rs b/src/rust/iced-x86/src/info/info_table.rs
index 603d34ef3..065121dfe 100644
--- a/src/rust/iced-x86/src/info/info_table.rs
+++ b/src/rust/iced-x86/src/info/info_table.rs
@@ -24,7 +24,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 // ⚠️This file was generated by GENERATOR!🦹‍♂️
 
 #[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
-pub(crate) static TABLE: [u32; 8432] = [
+pub(crate) static TABLE: [u32; 8442] = [
 	0x0000_0000, 0x0090_0000,// INVALID
 	0x0000_0000, 0x0090_0000,// DeclareByte
 	0x0000_0000, 0x0090_0000,// DeclareWord
@@ -4241,4 +4241,9 @@ pub(crate) static TABLE: [u32; 8432] = [
 	0x6650_0000, 0x9800_0000,// Invlpgbd
 	0x6650_0000, 0x9800_0000,// Invlpgbq
 	0x6000_0000, 0x9800_0000,// Tlbsync
+	0x0000_0003, 0x6B00_0000,// PrefetchReserved3_m8
+	0x0000_0003, 0x6B00_0000,// PrefetchReserved4_m8
+	0x0000_0003, 0x6B00_0000,// PrefetchReserved5_m8
+	0x0000_0003, 0x6B00_0000,// PrefetchReserved6_m8
+	0x0000_0003, 0x6B00_0000,// PrefetchReserved7_m8
 ];
diff --git a/src/rust/iced-x86/src/instruction_memory_sizes.rs b/src/rust/iced-x86/src/instruction_memory_sizes.rs
index f4615043e..91dca5b0a 100644
--- a/src/rust/iced-x86/src/instruction_memory_sizes.rs
+++ b/src/rust/iced-x86/src/instruction_memory_sizes.rs
@@ -4246,6 +4246,11 @@ pub(super) static SIZES: [MemorySize; IcedConstants::NUMBER_OF_CODE_VALUES * 2]
 	MemorySize::Unknown,// Invlpgbd
 	MemorySize::Unknown,// Invlpgbq
 	MemorySize::Unknown,// Tlbsync
+	MemorySize::UInt8,// PrefetchReserved3_m8
+	MemorySize::UInt8,// PrefetchReserved4_m8
+	MemorySize::UInt8,// PrefetchReserved5_m8
+	MemorySize::UInt8,// PrefetchReserved6_m8
+	MemorySize::UInt8,// PrefetchReserved7_m8
 	MemorySize::Unknown,// INVALID
 	MemorySize::Unknown,// DeclareByte
 	MemorySize::Unknown,// DeclareWord
@@ -8462,4 +8467,9 @@ pub(super) static SIZES: [MemorySize; IcedConstants::NUMBER_OF_CODE_VALUES * 2]
 	MemorySize::Unknown,// Invlpgbd
 	MemorySize::Unknown,// Invlpgbq
 	MemorySize::Unknown,// Tlbsync
+	MemorySize::Unknown,// PrefetchReserved3_m8
+	MemorySize::Unknown,// PrefetchReserved4_m8
+	MemorySize::Unknown,// PrefetchReserved5_m8
+	MemorySize::Unknown,// PrefetchReserved6_m8
+	MemorySize::Unknown,// PrefetchReserved7_m8
 ];
diff --git a/src/rust/iced-x86/src/instruction_op_counts.rs b/src/rust/iced-x86/src/instruction_op_counts.rs
index 60e6a1304..494d6fa1a 100644
--- a/src/rust/iced-x86/src/instruction_op_counts.rs
+++ b/src/rust/iced-x86/src/instruction_op_counts.rs
@@ -4243,4 +4243,9 @@ pub(super) static OP_COUNT: [u8; IcedConstants::NUMBER_OF_CODE_VALUES] = [
 	0,// Invlpgbd
 	0,// Invlpgbq
 	0,// Tlbsync
+	1,// PrefetchReserved3_m8
+	1,// PrefetchReserved4_m8
+	1,// PrefetchReserved5_m8
+	1,// PrefetchReserved6_m8
+	1,// PrefetchReserved7_m8
 ];
diff --git a/src/rust/iced-x86/src/mnemonics.rs b/src/rust/iced-x86/src/mnemonics.rs
index 5670d283e..86296e8e0 100644
--- a/src/rust/iced-x86/src/mnemonics.rs
+++ b/src/rust/iced-x86/src/mnemonics.rs
@@ -4244,4 +4244,9 @@ pub(super) static TO_MNEMONIC: [Mnemonic; IcedConstants::NUMBER_OF_CODE_VALUES]
 	Mnemonic::Invlpgb,// Invlpgbd
 	Mnemonic::Invlpgb,// Invlpgbq
 	Mnemonic::Tlbsync,// Tlbsync
+	Mnemonic::Prefetchw,// PrefetchReserved3_m8
+	Mnemonic::Prefetch,// PrefetchReserved4_m8
+	Mnemonic::Prefetch,// PrefetchReserved5_m8
+	Mnemonic::Prefetch,// PrefetchReserved6_m8
+	Mnemonic::Prefetch,// PrefetchReserved7_m8
 ];
diff --git a/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs b/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs
index 9380bf02a..be6937082 100644
--- a/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs
+++ b/src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs
@@ -33,7 +33,7 @@ lazy_static! {
 	pub(super) static ref TO_CODE_HASH: HashMap<&'static str, Code> = {
 		// GENERATOR-BEGIN: CodeHash
 		// ⚠️This was generated by GENERATOR!🦹‍♂️
-		let mut h = HashMap::with_capacity(4216);
+		let mut h = HashMap::with_capacity(4221);
 		h.insert("INVALID", Code::INVALID);
 		h.insert("DeclareByte", Code::DeclareByte);
 		h.insert("DeclareWord", Code::DeclareWord);
@@ -4250,6 +4250,11 @@ lazy_static! {
 		h.insert("Invlpgbd", Code::Invlpgbd);
 		h.insert("Invlpgbq", Code::Invlpgbq);
 		h.insert("Tlbsync", Code::Tlbsync);
+		h.insert("PrefetchReserved3_m8", Code::PrefetchReserved3_m8);
+		h.insert("PrefetchReserved4_m8", Code::PrefetchReserved4_m8);
+		h.insert("PrefetchReserved5_m8", Code::PrefetchReserved5_m8);
+		h.insert("PrefetchReserved6_m8", Code::PrefetchReserved6_m8);
+		h.insert("PrefetchReserved7_m8", Code::PrefetchReserved7_m8);
 		// GENERATOR-END: CodeHash
 		h
 	};