From 3553baf2a8d781d72bc2498415b669821beaee32 Mon Sep 17 00:00:00 2001 From: 0xd4d Date: Tue, 26 May 2020 19:24:58 +0200 Subject: [PATCH] Don't print data16/32/64 --- .../Formatter/Gas/Test16_ForceSuffix.txt | 2 +- .../Intel/Formatter/Gas/Test16_NoSuffix.txt | 2 +- .../Formatter/Gas/Test32_ForceSuffix.txt | 2 +- .../Intel/Formatter/Gas/Test32_NoSuffix.txt | 2 +- .../Formatter/Gas/Test64_ForceSuffix.txt | 2 +- .../Intel/Formatter/Gas/Test64_NoSuffix.txt | 2 +- .../Formatter/Intel/Test16_MemAlways.txt | 2 +- .../Formatter/Intel/Test16_MemDefault.txt | 2 +- .../Formatter/Intel/Test16_MemMinimum.txt | 2 +- .../Formatter/Intel/Test32_MemAlways.txt | 2 +- .../Formatter/Intel/Test32_MemDefault.txt | 2 +- .../Formatter/Intel/Test32_MemMinimum.txt | 2 +- .../Formatter/Intel/Test64_MemAlways.txt | 2 +- .../Formatter/Intel/Test64_MemDefault.txt | 2 +- .../Formatter/Intel/Test64_MemMinimum.txt | 2 +- .../Intel/Formatter/Nasm/Test16_MemAlways.txt | 2 +- .../Formatter/Nasm/Test16_MemMinimum.txt | 2 +- .../Intel/Formatter/Nasm/Test32_MemAlways.txt | 2 +- .../Formatter/Nasm/Test32_MemMinimum.txt | 2 +- .../Intel/Formatter/Nasm/Test64_MemAlways.txt | 2 +- .../Formatter/Nasm/Test64_MemDefault.txt | 2 +- .../Formatter/Nasm/Test64_MemMinimum.txt | 2 +- .../Generator/Enums/Formatter/Gas/CtorKind.cs | 1 - .../Enums/Formatter/Intel/CtorKind.cs | 1 - .../Enums/Formatter/Nasm/CtorKind.cs | 1 - .../Generator/Formatters/Gas/CtorInfosData.cs | 4 +- .../Formatters/Intel/CtorInfosData.cs | 4 +- .../Formatters/Nasm/CtorInfosData.cs | 4 +- .../Intel/GasFormatterInternal/CtorKind.g.cs | 1 - .../Intel/GasFormatterInternal/InstrInfo.cs | 29 -------------- .../Intel/GasFormatterInternal/InstrInfos.cs | 5 --- .../GasFormatterInternal/InstrInfos.g.cs | 7 +--- .../IntelFormatterInternal/CtorKind.g.cs | 1 - .../Intel/IntelFormatterInternal/InstrInfo.cs | 32 +-------------- .../IntelFormatterInternal/InstrInfos.cs | 5 --- .../IntelFormatterInternal/InstrInfos.g.cs | 21 +++++----- .../Intel/NasmFormatterInternal/CtorKind.g.cs | 1 - .../Intel/NasmFormatterInternal/InstrInfo.cs | 31 --------------- .../Intel/NasmFormatterInternal/InstrInfos.cs | 5 --- .../NasmFormatterInternal/InstrInfos.g.cs | 39 +++++++++---------- src/rust/iced-x86/src/formatter/gas/enums.rs | 4 +- .../iced-x86/src/formatter/gas/fmt_data.rs | 7 +--- .../iced-x86/src/formatter/gas/fmt_tbl.rs | 5 --- src/rust/iced-x86/src/formatter/gas/info.rs | 33 ---------------- .../iced-x86/src/formatter/intel/enums.rs | 4 +- .../iced-x86/src/formatter/intel/fmt_data.rs | 21 +++++----- .../iced-x86/src/formatter/intel/fmt_tbl.rs | 5 --- src/rust/iced-x86/src/formatter/intel/info.rs | 33 ---------------- src/rust/iced-x86/src/formatter/nasm/enums.rs | 4 +- .../iced-x86/src/formatter/nasm/fmt_data.rs | 39 +++++++++---------- .../iced-x86/src/formatter/nasm/fmt_tbl.rs | 5 --- src/rust/iced-x86/src/formatter/nasm/info.rs | 35 ----------------- 52 files changed, 90 insertions(+), 341 deletions(-) diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt index 8065d4b10..e615f85b4 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt @@ -244,7 +244,7 @@ scasw (di), ax scasl (edi), eax scasl (di), eax xbegin 0x0000254e -data32 xbegin 0x34132551 +xbegin 0x34132551 enterw $-0x5aa6, $-0x5a leavew lretw $-0x5aa6 diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt index 6d3ae5e96..7bcfeffcf 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt @@ -244,7 +244,7 @@ scas (%di),%ax scas (%edi),%eax scas (%di),%eax xbegin 0x0000254e -data32 xbegin 0x34132551 +xbegin 0x34132551 enter $0xa55a,$0xa6 leave lret $0xa55a diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt index 79de3ddb6..798bc85b1 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt @@ -310,7 +310,7 @@ scasw (di), ax scasw (edi), ax scasl (di), eax scasl (edi), eax -data16 xbegin 0x7fffa54f +xbegin 0x7fffa54f xbegin 0xb412a550 enterw $-0x5aa6, $-0x5a leavew diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt index 92840c98a..85e88a745 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt @@ -310,7 +310,7 @@ scas (%di),%ax scas (%edi),%ax scas (%di),%eax scas (%edi),%eax -data16 xbegin 0x7fffa54f +xbegin 0x7fffa54f xbegin 0xb412a550 enterw $0xa55a,$0xa6 leavew diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt index 9d38644cc..da43c7a9e 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt @@ -716,7 +716,7 @@ movl $0x3412a55a, ecx movl $0x3412a55a, (rax) movq $-0x7bed5aa6, rcx movq $-0x7bed5aa6, (rax) -data16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 enterw $-0x5aa6, $-0x5a diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt index 5f0dd0e43..c0bbc90c7 100644 --- a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt +++ b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt @@ -716,7 +716,7 @@ mov $0x3412a55a,%ecx movl $0x3412a55a,(%rax) mov $0xffffffff8412a55a,%rcx movq $0xffffffff8412a55a,(%rax) -data16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 enterw $0xa55a,$0xa6 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt index 2548635f2..578485d12 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test16_MemAlways.txt @@ -244,7 +244,7 @@ scasw word ptr [di] scasd dword ptr [edi] scasd dword ptr [di] xbegin 0x0000254e -data32 xbegin 0x34132551 +xbegin 0x34132551 enter -0x5aa6, -0x5a leave ret far -0x5aa6 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt index cfbad0d40..8a024664b 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test16_MemDefault.txt @@ -244,7 +244,7 @@ scasw [di] scasd [edi] scasd [di] xbegin 0x0000254e -data32 xbegin 0x34132551 +xbegin 0x34132551 enter 0xa55a,0xa6 leave ret far 0xa55a diff --git a/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt index 05caa4d10..7a655e000 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test16_MemMinimum.txt @@ -244,7 +244,7 @@ scasw [di] scasd [edi] scasd [di] xbegin 0x0000254e -data32 xbegin 0x34132551 +xbegin 0x34132551 enter -0x5aa6, -0x5a leave ret far -0x5aa6 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt index 361860890..17ad897e2 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt @@ -310,7 +310,7 @@ scasw word ptr [di] scasw word ptr [edi] scasd dword ptr [di] scasd dword ptr [edi] -data16 xbegin 0x7fffa54f +xbegin 0x7fffa54f xbegin 0xb412a550 data16 enter -0x5aa6, -0x5a data16 leave diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt index bee1f8be1..c89ee0078 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt @@ -310,7 +310,7 @@ scasw [di] scasw [edi] scasd [di] scasd [edi] -data16 xbegin 0x7fffa54f +xbegin 0x7fffa54f xbegin 0xb412a550 data16 enter 0xa55a,0xa6 data16 leave diff --git a/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt index 6518f5cde..139813609 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt @@ -310,7 +310,7 @@ scasw [di] scasw [edi] scasd [di] scasd [edi] -data16 xbegin 0x7fffa54f +xbegin 0x7fffa54f xbegin 0xb412a550 data16 enter -0x5aa6, -0x5a data16 leave diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt index 69a2eb95c..fcb0dc20e 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt @@ -716,7 +716,7 @@ mov ecx, 0x3412a55a mov dword ptr [rax], 0x3412a55a mov rcx, -0x7bed5aa6 mov qword ptr [rax], -0x7bed5aa6 -data16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 data16 enter -0x5aa6, -0x5a diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt index 6d9e4751a..e9996ede6 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt @@ -716,7 +716,7 @@ mov ecx,0x3412a55a mov dword ptr [rax],0x3412a55a mov rcx,0xffffffff8412a55a mov qword ptr [rax],0xffffffff8412a55a -data16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 data16 enter 0xa55a,0xa6 diff --git a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt index 9fa8e6bc8..c170116fc 100644 --- a/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt @@ -716,7 +716,7 @@ mov ecx, 0x3412a55a mov dword ptr [rax], 0x3412a55a mov rcx, -0x7bed5aa6 mov qword ptr [rax], -0x7bed5aa6 -data16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 data16 enter -0x5aa6, -0x5a diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt index eb8458b17..2195fcaef 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemAlways.txt @@ -244,7 +244,7 @@ scasw a32 scasd scasd xbegin 0x0000254e -xbegin dword 0x34132551 +xbegin 0x34132551 enter -0x5aa6, -0x5a leave retf -0x5aa6 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt index a25a91407..e89609f4c 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test16_MemMinimum.txt @@ -244,7 +244,7 @@ scasw a32 scasd scasd xbegin 0x0000254e -xbegin dword 0x34132551 +xbegin 0x34132551 enter -0x5aa6, -0x5a leave retf -0x5aa6 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt index 23106c0ed..506286fd5 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt @@ -310,7 +310,7 @@ a16 scasw scasw a16 scasd scasd -xbegin word 0x7fffa54f +xbegin 0x7fffa54f xbegin 0xb412a550 o16 enter -0x5aa6, -0x5a o16 leave diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt index 11ef06587..63258e971 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt @@ -310,7 +310,7 @@ a16 scasw scasw a16 scasd scasd -xbegin word 0x7fffa54f +xbegin 0x7fffa54f xbegin 0xb412a550 o16 enter -0x5aa6, -0x5a o16 leave diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt index 6d1b626fe..cce2913e3 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt @@ -716,7 +716,7 @@ mov ecx, 0x3412a55a mov dword [rax], 0x3412a55a mov rcx, dword -0x7bed5aa6 mov qword [rax], qword -0x7bed5aa6 -o16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 o16 enter -0x5aa6, -0x5a diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt index daa0193ef..31e300c1f 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt @@ -716,7 +716,7 @@ mov ecx,0x3412a55a mov dword [rax],0x3412a55a mov rcx,dword 0xffffffff8412a55a mov qword [rax],qword 0xffffffff8412a55a -o16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 o16 enter 0xa55a,0xa6 diff --git a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt index 85d947fcc..713f846f4 100644 --- a/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt +++ b/src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt @@ -716,7 +716,7 @@ mov ecx, 0x3412a55a mov dword [rax], 0x3412a55a mov rcx, dword -0x7bed5aa6 mov qword [rax], qword -0x7bed5aa6 -o16 xbegin 0x7fffffffffffa54f +xbegin 0x7fffffffffffa54f xbegin 0x800000003412a550 xbegin 0x800000003412a551 o16 enter -0x5aa6, -0x5a diff --git a/src/csharp/Intel/Generator/Enums/Formatter/Gas/CtorKind.cs b/src/csharp/Intel/Generator/Enums/Formatter/Gas/CtorKind.cs index cc89df6fe..24a8f9ee9 100644 --- a/src/csharp/Intel/Generator/Enums/Formatter/Gas/CtorKind.cs +++ b/src/csharp/Intel/Generator/Enums/Formatter/Gas/CtorKind.cs @@ -73,6 +73,5 @@ enum CtorKind { STi_ST2, STIG_1a, STIG_1b, - xbegin, } } diff --git a/src/csharp/Intel/Generator/Enums/Formatter/Intel/CtorKind.cs b/src/csharp/Intel/Generator/Enums/Formatter/Intel/CtorKind.cs index 69be5f3ad..e0902f77f 100644 --- a/src/csharp/Intel/Generator/Enums/Formatter/Intel/CtorKind.cs +++ b/src/csharp/Intel/Generator/Enums/Formatter/Intel/CtorKind.cs @@ -67,7 +67,6 @@ enum CtorKind { ST1_3, ST2, STi_ST, - xbegin, YA, invlpga, } diff --git a/src/csharp/Intel/Generator/Enums/Formatter/Nasm/CtorKind.cs b/src/csharp/Intel/Generator/Enums/Formatter/Nasm/CtorKind.cs index 34624dbd2..bf906a638 100644 --- a/src/csharp/Intel/Generator/Enums/Formatter/Nasm/CtorKind.cs +++ b/src/csharp/Intel/Generator/Enums/Formatter/Nasm/CtorKind.cs @@ -88,7 +88,6 @@ enum CtorKind { STIG1_2, STIG2_2a, STIG2_2b, - xbegin, XLAT, XY, YA, diff --git a/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs index c4931be46..f485535d6 100644 --- a/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs +++ b/src/csharp/Intel/Generator/Formatters/Gas/CtorInfosData.cs @@ -442,8 +442,8 @@ public static object[][] GetData(GenTypes genTypes) { new object[] { ctorKind[nameof(CtorKind.Normal_3)], code[nameof(Code.Mov_rm16_imm16)], "mov", 'w', instrOpInfoFlags[nameof(InstrOpInfoFlags.MnemonicSuffixIfMem)] }, new object[] { ctorKind[nameof(CtorKind.Normal_3)], code[nameof(Code.Mov_rm32_imm32)], "mov", 'l', instrOpInfoFlags[nameof(InstrOpInfoFlags.MnemonicSuffixIfMem)] }, new object[] { ctorKind[nameof(CtorKind.Normal_3)], code[nameof(Code.Mov_rm64_imm32)], "mov", 'q', instrOpInfoFlags[nameof(InstrOpInfoFlags.MnemonicSuffixIfMem)] }, - new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel16)], "xbegin", 16 }, - new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel32)], "xbegin", 32 | 64 }, + new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel16)], "xbegin" }, + new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel32)], "xbegin" }, new object[] { ctorKind[nameof(CtorKind.os2_4)], code[nameof(Code.Enterw_imm16_imm8)], "enter", 'w', 16, instrOpInfoFlags[nameof(InstrOpInfoFlags.KeepOperandOrder)] }, new object[] { ctorKind[nameof(CtorKind.os2_4)], code[nameof(Code.Enterd_imm16_imm8)], "enter", 'l', 32, instrOpInfoFlags[nameof(InstrOpInfoFlags.KeepOperandOrder)] }, new object[] { ctorKind[nameof(CtorKind.os2_4)], code[nameof(Code.Enterq_imm16_imm8)], "enter", 'q', 64, instrOpInfoFlags[nameof(InstrOpInfoFlags.KeepOperandOrder)] }, diff --git a/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs index 315dbea08..68f9e1a91 100644 --- a/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs +++ b/src/csharp/Intel/Generator/Formatters/Intel/CtorInfosData.cs @@ -442,8 +442,8 @@ public static object[][] GetData(GenTypes genTypes) { new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm16_imm16)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) }, new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm32_imm32)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) }, new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm64_imm32)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) }, - new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel16)], "xbegin", 16 }, - new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel32)], "xbegin", 32 | 64 }, + new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel16)], "xbegin" }, + new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel32)], "xbegin" }, new object[] { ctorKind[nameof(CtorKind.os2)], code[nameof(Code.Enterw_imm16_imm8)], "enter", 16 }, new object[] { ctorKind[nameof(CtorKind.os2)], code[nameof(Code.Enterd_imm16_imm8)], "enter", 32 }, new object[] { ctorKind[nameof(CtorKind.os2)], code[nameof(Code.Enterq_imm16_imm8)], "enter", 64 }, diff --git a/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs b/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs index a663f2fa6..e5492a729 100644 --- a/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs +++ b/src/csharp/Intel/Generator/Formatters/Nasm/CtorInfosData.cs @@ -444,8 +444,8 @@ public static object[][] GetData(GenTypes genTypes) { new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm16_imm16)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) }, new object[] { ctorKind[nameof(CtorKind.Normal_2)], code[nameof(Code.Mov_rm32_imm32)], "mov", new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) }, new object[] { ctorKind[nameof(CtorKind.SEX2_4)], code[nameof(Code.Mov_rm64_imm32)], "mov", signExtendInfo[nameof(SignExtendInfo.Sex4)], signExtendInfo[nameof(SignExtendInfo.Sex4to8)], new OrEnumValue(instrOpInfoFlags, nameof(InstrOpInfoFlags.ShowNoMemSize_ForceSize), nameof(InstrOpInfoFlags.ShowMinMemSize_ForceSize)) }, - new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel16)], "xbegin", 16 }, - new object[] { ctorKind[nameof(CtorKind.xbegin)], code[nameof(Code.Xbegin_rel32)], "xbegin", 32 | 64 }, + new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel16)], "xbegin" }, + new object[] { ctorKind[nameof(CtorKind.Normal_1)], code[nameof(Code.Xbegin_rel32)], "xbegin" }, new object[] { ctorKind[nameof(CtorKind.os_2)], code[nameof(Code.Enterw_imm16_imm8)], "enter", 16 }, new object[] { ctorKind[nameof(CtorKind.os_2)], code[nameof(Code.Enterd_imm16_imm8)], "enter", 32 }, new object[] { ctorKind[nameof(CtorKind.os_2)], code[nameof(Code.Enterq_imm16_imm8)], "enter", 64 }, diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/CtorKind.g.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/CtorKind.g.cs index f22e62f6a..0662baba9 100644 --- a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/CtorKind.g.cs +++ b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/CtorKind.g.cs @@ -77,7 +77,6 @@ enum CtorKind { STi_ST2, STIG_1a, STIG_1b, - xbegin, } } #endif diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfo.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfo.cs index edb36492a..111d9e5ae 100644 --- a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfo.cs +++ b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfo.cs @@ -975,35 +975,6 @@ public override void GetOpInfo(FormatterOptions options, in Instruction instruct } } - sealed class SimpleInstrInfo_xbegin : InstrInfo { - readonly int bitnessFlags; - readonly FormatterString mnemonic; - - public SimpleInstrInfo_xbegin(int bitnessFlags, string mnemonic) { - this.bitnessFlags = bitnessFlags; - this.mnemonic = new FormatterString(mnemonic); - } - - public override void GetOpInfo(FormatterOptions options, in Instruction instruction, out InstrOpInfo info) { - var flags = InstrOpInfoFlags.None; - int instrBitness = GetBitness(instruction.CodeSize); - if (instrBitness == 0) { - // Nothing - } - else if (instrBitness == 64) { - if ((bitnessFlags & 16) != 0) - flags |= InstrOpInfoFlags.OpSize16; - } - else if ((instrBitness & bitnessFlags) == 0) { - if ((bitnessFlags & 16) != 0) - flags |= InstrOpInfoFlags.OpSize16; - else if ((bitnessFlags & 32) != 0) - flags |= InstrOpInfoFlags.OpSize32; - } - info = new InstrOpInfo(mnemonic, instruction, flags); - } - } - sealed class SimpleInstrInfo_movabs : InstrInfo { readonly int memOpNumber; readonly FormatterString mnemonic; diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.cs index 18533b182..f5c9592e7 100644 --- a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.cs +++ b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.cs @@ -363,11 +363,6 @@ static InstrInfo[] ReadInfos() { instrInfo = new SimpleInstrInfo_STIG1(s, v != 0); break; - case CtorKind.xbegin: - v = reader.ReadCompressedUInt32(); - instrInfo = new SimpleInstrInfo_xbegin((int)v, s); - break; - default: throw new InvalidOperationException(); } diff --git a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs index a10a9cc2d..5449d2663 100644 --- a/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs +++ b/src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs @@ -2296,14 +2296,11 @@ static byte[] GetSerializedInstrInfos() => 0x01,// 0x1 = MnemonicSuffixIfMem // Xbegin_rel16 - 0x31,// xbegin + 0x01,// Normal_1 0xE5, 0x01,// 229 = "xbegin" - 0x10,// 0x10 // Xbegin_rel32 - 0x31,// xbegin - 0xE5, 0x01,// 229 = "xbegin" - 0x60,// 0x60 + 0x00,// Previous // Enterw_imm16_imm8 0x24,// os2_4 diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/CtorKind.g.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/CtorKind.g.cs index be63d021c..786374d41 100644 --- a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/CtorKind.g.cs +++ b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/CtorKind.g.cs @@ -71,7 +71,6 @@ enum CtorKind { ST1_3, ST2, STi_ST, - xbegin, YA, invlpga, } diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfo.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfo.cs index 72af51e55..c8e6e23c9 100644 --- a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfo.cs +++ b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfo.cs @@ -712,41 +712,11 @@ public override void GetOpInfo(FormatterOptions options, in Instruction instruct } } - sealed class SimpleInstrInfo_xbegin : InstrInfo { - readonly int bitnessFlags; - readonly FormatterString mnemonic; - - public SimpleInstrInfo_xbegin(int bitnessFlags, string mnemonic) { - this.bitnessFlags = bitnessFlags; - this.mnemonic = new FormatterString(mnemonic); - } - - public override void GetOpInfo(FormatterOptions options, in Instruction instruction, out InstrOpInfo info) { - var flags = InstrOpInfoFlags.None; - int instrBitness = GetBitness(instruction.CodeSize); - if (instrBitness == 0) { - // Nothing - } - else if (instrBitness == 64) { - if ((bitnessFlags & 16) != 0) - flags |= InstrOpInfoFlags.OpSize16; - } - else if ((instrBitness & bitnessFlags) == 0) { - if ((bitnessFlags & 16) != 0) - flags |= InstrOpInfoFlags.OpSize16; - else if ((bitnessFlags & 32) != 0) - flags |= InstrOpInfoFlags.OpSize32; - } - info = new InstrOpInfo(mnemonic, instruction, flags); - } - } - sealed class SimpleInstrInfo_k1 : InstrInfo { readonly FormatterString mnemonic; - public SimpleInstrInfo_k1(string mnemonic) { + public SimpleInstrInfo_k1(string mnemonic) => this.mnemonic = new FormatterString(mnemonic); - } public override void GetOpInfo(FormatterOptions options, in Instruction instruction, out InstrOpInfo info) { info = new InstrOpInfo(mnemonic, instruction, InstrOpInfoFlags.None); diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.cs index 4a8771232..9abefbbb1 100644 --- a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.cs +++ b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.cs @@ -287,11 +287,6 @@ static InstrInfo[] ReadInfos() { instrInfo = new SimpleInstrInfo_STi_ST(s); break; - case CtorKind.xbegin: - v = reader.ReadCompressedUInt32(); - instrInfo = new SimpleInstrInfo_xbegin((int)v, s); - break; - case CtorKind.YA: instrInfo = new SimpleInstrInfo_YA(s); break; diff --git a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs index 481487125..8dd6f6f36 100644 --- a/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs +++ b/src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs @@ -1505,19 +1505,19 @@ static byte[] GetSerializedInstrInfos() => 0x00,// Previous // Stosb_m8_AL - 0x2C,// YA + 0x2B,// YA 0xCF, 0x01,// 207 = "stosb" // Stosw_m16_AX - 0x2C,// YA + 0x2B,// YA 0xD0, 0x01,// 208 = "stosw" // Stosd_m32_EAX - 0x2C,// YA + 0x2B,// YA 0xD1, 0x01,// 209 = "stosd" // Stosq_m64_RAX - 0x2C,// YA + 0x2B,// YA 0xD2, 0x01,// 210 = "stosq" // Lodsb_AL_m8 @@ -1756,14 +1756,11 @@ static byte[] GetSerializedInstrInfos() => 0x00,// Previous // Xbegin_rel16 - 0x2B,// xbegin + 0x01,// Normal_1 0xE5, 0x01,// 229 = "xbegin" - 0x10,// 0x10 // Xbegin_rel32 - 0x2B,// xbegin - 0xE5, 0x01,// 229 = "xbegin" - 0x60,// 0x60 + 0x00,// Previous // Enterw_imm16_imm8 0x13,// os2 @@ -3668,17 +3665,17 @@ static byte[] GetSerializedInstrInfos() => 0x25,// EAX // Invlpgaw - 0x2D,// invlpga + 0x2C,// invlpga 0xA1, 0x03,// 417 = "invlpga" 0x10,// 0x10 // Invlpgad - 0x2D,// invlpga + 0x2C,// invlpga 0xA1, 0x03,// 417 = "invlpga" 0x20,// 0x20 // Invlpgaq - 0x2D,// invlpga + 0x2C,// invlpga 0xA1, 0x03,// 417 = "invlpga" 0x40,// 0x40 diff --git a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/CtorKind.g.cs b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/CtorKind.g.cs index 660f872f5..77d354789 100644 --- a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/CtorKind.g.cs +++ b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/CtorKind.g.cs @@ -92,7 +92,6 @@ enum CtorKind { STIG1_2, STIG2_2a, STIG2_2b, - xbegin, XLAT, XY, YA, diff --git a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfo.cs b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfo.cs index f2619e008..ba8d0835c 100644 --- a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfo.cs +++ b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfo.cs @@ -1277,37 +1277,6 @@ public override void GetOpInfo(FormatterOptions options, in Instruction instruct } } - sealed class SimpleInstrInfo_xbegin : InstrInfo { - readonly int bitnessFlags; - readonly FormatterString mnemonic; - - public SimpleInstrInfo_xbegin(int bitnessFlags, string mnemonic) { - this.bitnessFlags = bitnessFlags; - this.mnemonic = new FormatterString(mnemonic); - } - - public override void GetOpInfo(FormatterOptions options, in Instruction instruction, out InstrOpInfo info) { - var flags = InstrOpInfoFlags.None; - var branchInfo = BranchSizeInfo.None; - int instrBitness = GetBitness(instruction.CodeSize); - if (instrBitness == 0) { - // Nothing - } - else if (instrBitness == 64) { - if ((bitnessFlags & 16) != 0) - flags |= InstrOpInfoFlags.OpSize16; - } - else if ((instrBitness & bitnessFlags) == 0) { - if ((bitnessFlags & 16) != 0) - branchInfo = BranchSizeInfo.Word; - else if ((bitnessFlags & 32) != 0) - branchInfo = BranchSizeInfo.Dword; - } - flags |= (InstrOpInfoFlags)((int)branchInfo << (int)InstrOpInfoFlags.BranchSizeInfoShift); - info = new InstrOpInfo(mnemonic, instruction, flags); - } - } - sealed class SimpleInstrInfo_movabs : InstrInfo { readonly int memOpNumber; readonly FormatterString mnemonic; diff --git a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.cs b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.cs index ab0e12605..c3a927217 100644 --- a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.cs +++ b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.cs @@ -421,11 +421,6 @@ static InstrInfo[] ReadInfos() { instrInfo = new SimpleInstrInfo_STIG2(s, (InstrOpInfoFlags)v); break; - case CtorKind.xbegin: - v = reader.ReadCompressedUInt32(); - instrInfo = new SimpleInstrInfo_xbegin((int)v, s); - break; - case CtorKind.XLAT: instrInfo = new SimpleInstrInfo_XLAT(s); break; diff --git a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs index bb39500db..3ca0e454b 100644 --- a/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs +++ b/src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs @@ -603,15 +603,15 @@ static byte[] GetSerializedInstrInfos() => 0x03,// Sex1to8 // Insb_m8_DX - 0x44,// YD + 0x43,// YD 0x96, 0x01,// 150 = "insb" // Insw_m16_DX - 0x44,// YD + 0x43,// YD 0x97, 0x01,// 151 = "insw" // Insd_m32_DX - 0x44,// YD + 0x43,// YD 0x98, 0x01,// 152 = "insd" // Outsb_DX_m8 @@ -1579,35 +1579,35 @@ static byte[] GetSerializedInstrInfos() => 0x00,// Previous // Movsb_m8_m8 - 0x45,// YX + 0x44,// YX 0xC7, 0x01,// 199 = "movsb" // Movsw_m16_m16 - 0x45,// YX + 0x44,// YX 0xC8, 0x01,// 200 = "movsw" // Movsd_m32_m32 - 0x45,// YX + 0x44,// YX 0x25,// 37 = "movsd" // Movsq_m64_m64 - 0x45,// YX + 0x44,// YX 0xC9, 0x01,// 201 = "movsq" // Cmpsb_m8_m8 - 0x42,// XY + 0x41,// XY 0xCB, 0x01,// 203 = "cmpsb" // Cmpsw_m16_m16 - 0x42,// XY + 0x41,// XY 0xCC, 0x01,// 204 = "cmpsw" // Cmpsd_m32_m32 - 0x42,// XY + 0x41,// XY 0x94, 0x06,// 788 = "cmpsd" // Cmpsq_m64_m64 - 0x42,// XY + 0x41,// XY 0xCD, 0x01,// 205 = "cmpsq" // Test_AL_imm8 @@ -1626,19 +1626,19 @@ static byte[] GetSerializedInstrInfos() => 0x00,// None // Stosb_m8_AL - 0x43,// YA + 0x42,// YA 0xCF, 0x01,// 207 = "stosb" // Stosw_m16_AX - 0x43,// YA + 0x42,// YA 0xD0, 0x01,// 208 = "stosw" // Stosd_m32_EAX - 0x43,// YA + 0x42,// YA 0xD1, 0x01,// 209 = "stosd" // Stosq_m64_RAX - 0x43,// YA + 0x42,// YA 0xD2, 0x01,// 210 = "stosq" // Lodsb_AL_m8 @@ -1891,14 +1891,11 @@ static byte[] GetSerializedInstrInfos() => 0x06,// 0x6 = ShowNoMemSize_ForceSize, ShowMinMemSize_ForceSize // Xbegin_rel16 - 0x40,// xbegin + 0x01,// Normal_1 0xE5, 0x01,// 229 = "xbegin" - 0x10,// 0x10 // Xbegin_rel32 - 0x40,// xbegin - 0xE5, 0x01,// 229 = "xbegin" - 0x60,// 0x60 + 0x00,// Previous // Enterw_imm16_imm8 0x1B,// os_2 @@ -2265,7 +2262,7 @@ static byte[] GetSerializedInstrInfos() => 0xF5, 0x01,// 245 = "salc" // Xlat_m8 - 0x41,// XLAT + 0x40,// XLAT 0xF7, 0x01,// 247 = "xlatb" // Fadd_m32fp diff --git a/src/rust/iced-x86/src/formatter/gas/enums.rs b/src/rust/iced-x86/src/formatter/gas/enums.rs index 02599dd2f..a43c3d456 100644 --- a/src/rust/iced-x86/src/formatter/gas/enums.rs +++ b/src/rust/iced-x86/src/formatter/gas/enums.rs @@ -78,10 +78,9 @@ pub(crate) enum CtorKind { STi_ST2, STIG_1a, STIG_1b, - xbegin, } #[cfg_attr(feature = "cargo-fmt", rustfmt::skip)] -static GEN_DEBUG_CTOR_KIND: [&str; 50] = [ +static GEN_DEBUG_CTOR_KIND: [&str; 49] = [ "Previous", "Normal_1", "Normal_2a", @@ -131,7 +130,6 @@ static GEN_DEBUG_CTOR_KIND: [&str; 50] = [ "STi_ST2", "STIG_1a", "STIG_1b", - "xbegin", ]; impl fmt::Debug for CtorKind { #[inline] diff --git a/src/rust/iced-x86/src/formatter/gas/fmt_data.rs b/src/rust/iced-x86/src/formatter/gas/fmt_data.rs index bfe8cf4e2..52a04b6ff 100644 --- a/src/rust/iced-x86/src/formatter/gas/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/gas/fmt_data.rs @@ -2287,14 +2287,11 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x01,// 0x1 = MnemonicSuffixIfMem // Xbegin_rel16 - 0x31,// xbegin + 0x01,// Normal_1 0xE5, 0x01,// 229 = "xbegin" - 0x10,// 0x10 // Xbegin_rel32 - 0x31,// xbegin - 0xE5, 0x01,// 229 = "xbegin" - 0x60,// 0x60 + 0x00,// Previous // Enterw_imm16_imm8 0x24,// os2_4 diff --git a/src/rust/iced-x86/src/formatter/gas/fmt_tbl.rs b/src/rust/iced-x86/src/formatter/gas/fmt_tbl.rs index 3ef6e2592..6d0007724 100644 --- a/src/rust/iced-x86/src/formatter/gas/fmt_tbl.rs +++ b/src/rust/iced-x86/src/formatter/gas/fmt_tbl.rs @@ -362,11 +362,6 @@ fn read() -> Vec> { } Box::new(SimpleInstrInfo_STIG1::new(s, v != 0)) } - - CtorKind::xbegin => { - v = reader.read_compressed_u32(); - Box::new(SimpleInstrInfo_xbegin::new(v, s)) - } }; infos.push(info); diff --git a/src/rust/iced-x86/src/formatter/gas/info.rs b/src/rust/iced-x86/src/formatter/gas/info.rs index 3ffbf0d9b..193dc0ad0 100644 --- a/src/rust/iced-x86/src/formatter/gas/info.rs +++ b/src/rust/iced-x86/src/formatter/gas/info.rs @@ -1118,39 +1118,6 @@ impl InstrInfo for SimpleInstrInfo_os_jcc { } } -#[allow(non_camel_case_types)] -pub(super) struct SimpleInstrInfo_xbegin { - mnemonic: FormatterString, - bitness_flags: u32, -} - -impl SimpleInstrInfo_xbegin { - pub(super) fn new(bitness_flags: u32, mnemonic: String) -> Self { - Self { mnemonic: FormatterString::new(mnemonic), bitness_flags } - } -} - -impl InstrInfo for SimpleInstrInfo_xbegin { - fn op_info<'a>(&'a self, _options: &FormatterOptions, instruction: &Instruction) -> InstrOpInfo<'a> { - let mut flags = InstrOpInfoFlags::NONE; - let instr_bitness = get_bitness(instruction.code_size()); - if instr_bitness == 0 { - // Nothing - } else if instr_bitness == 64 { - if (self.bitness_flags & 16) != 0 { - flags |= InstrOpInfoFlags::OP_SIZE16; - } - } else if (instr_bitness & self.bitness_flags) == 0 { - if (self.bitness_flags & 16) != 0 { - flags |= InstrOpInfoFlags::OP_SIZE16; - } else if (self.bitness_flags & 32) != 0 { - flags |= InstrOpInfoFlags::OP_SIZE32; - } - } - InstrOpInfo::new(&self.mnemonic, instruction, flags) - } -} - #[allow(non_camel_case_types)] pub(super) struct SimpleInstrInfo_movabs { mnemonic: FormatterString, diff --git a/src/rust/iced-x86/src/formatter/intel/enums.rs b/src/rust/iced-x86/src/formatter/intel/enums.rs index 02943f08a..3deb06e1f 100644 --- a/src/rust/iced-x86/src/formatter/intel/enums.rs +++ b/src/rust/iced-x86/src/formatter/intel/enums.rs @@ -72,12 +72,11 @@ pub(crate) enum CtorKind { ST1_3, ST2, STi_ST, - xbegin, YA, invlpga, } #[cfg_attr(feature = "cargo-fmt", rustfmt::skip)] -static GEN_DEBUG_CTOR_KIND: [&str; 46] = [ +static GEN_DEBUG_CTOR_KIND: [&str; 45] = [ "Previous", "Normal_1", "Normal_2", @@ -121,7 +120,6 @@ static GEN_DEBUG_CTOR_KIND: [&str; 46] = [ "ST1_3", "ST2", "STi_ST", - "xbegin", "YA", "invlpga", ]; diff --git a/src/rust/iced-x86/src/formatter/intel/fmt_data.rs b/src/rust/iced-x86/src/formatter/intel/fmt_data.rs index ad79e0b5e..e8ee8a591 100644 --- a/src/rust/iced-x86/src/formatter/intel/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/intel/fmt_data.rs @@ -1496,19 +1496,19 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x00,// Previous // Stosb_m8_AL - 0x2C,// YA + 0x2B,// YA 0xCF, 0x01,// 207 = "stosb" // Stosw_m16_AX - 0x2C,// YA + 0x2B,// YA 0xD0, 0x01,// 208 = "stosw" // Stosd_m32_EAX - 0x2C,// YA + 0x2B,// YA 0xD1, 0x01,// 209 = "stosd" // Stosq_m64_RAX - 0x2C,// YA + 0x2B,// YA 0xD2, 0x01,// 210 = "stosq" // Lodsb_AL_m8 @@ -1747,14 +1747,11 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x00,// Previous // Xbegin_rel16 - 0x2B,// xbegin + 0x01,// Normal_1 0xE5, 0x01,// 229 = "xbegin" - 0x10,// 0x10 // Xbegin_rel32 - 0x2B,// xbegin - 0xE5, 0x01,// 229 = "xbegin" - 0x60,// 0x60 + 0x00,// Previous // Enterw_imm16_imm8 0x13,// os2 @@ -3659,17 +3656,17 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x25,// EAX // Invlpgaw - 0x2D,// invlpga + 0x2C,// invlpga 0xA1, 0x03,// 417 = "invlpga" 0x10,// 0x10 // Invlpgad - 0x2D,// invlpga + 0x2C,// invlpga 0xA1, 0x03,// 417 = "invlpga" 0x20,// 0x20 // Invlpgaq - 0x2D,// invlpga + 0x2C,// invlpga 0xA1, 0x03,// 417 = "invlpga" 0x40,// 0x40 diff --git a/src/rust/iced-x86/src/formatter/intel/fmt_tbl.rs b/src/rust/iced-x86/src/formatter/intel/fmt_tbl.rs index 0cd972b91..ac4f3f571 100644 --- a/src/rust/iced-x86/src/formatter/intel/fmt_tbl.rs +++ b/src/rust/iced-x86/src/formatter/intel/fmt_tbl.rs @@ -268,11 +268,6 @@ fn read() -> Vec> { CtorKind::STi_ST => Box::new(SimpleInstrInfo_STi_ST::new(s)), - CtorKind::xbegin => { - v = reader.read_compressed_u32(); - Box::new(SimpleInstrInfo_xbegin::new(v, s)) - } - CtorKind::YA => Box::new(SimpleInstrInfo_YA::new(s)), CtorKind::invlpga => { diff --git a/src/rust/iced-x86/src/formatter/intel/info.rs b/src/rust/iced-x86/src/formatter/intel/info.rs index 9c2d6a1fa..45f2a7dbe 100644 --- a/src/rust/iced-x86/src/formatter/intel/info.rs +++ b/src/rust/iced-x86/src/formatter/intel/info.rs @@ -827,39 +827,6 @@ impl InstrInfo for SimpleInstrInfo_movabs { } } -#[allow(non_camel_case_types)] -pub(super) struct SimpleInstrInfo_xbegin { - mnemonic: FormatterString, - bitness_flags: u32, -} - -impl SimpleInstrInfo_xbegin { - pub(super) fn new(bitness_flags: u32, mnemonic: String) -> Self { - Self { mnemonic: FormatterString::new(mnemonic), bitness_flags } - } -} - -impl InstrInfo for SimpleInstrInfo_xbegin { - fn op_info<'a>(&'a self, _options: &FormatterOptions, instruction: &Instruction) -> InstrOpInfo<'a> { - let mut flags = InstrOpInfoFlags::NONE; - let instr_bitness = get_bitness(instruction.code_size()); - if instr_bitness == 0 { - // Nothing - } else if instr_bitness == 64 { - if (self.bitness_flags & 16) != 0 { - flags |= InstrOpInfoFlags::OP_SIZE16; - } - } else if (instr_bitness & self.bitness_flags) == 0 { - if (self.bitness_flags & 16) != 0 { - flags |= InstrOpInfoFlags::OP_SIZE16; - } else if (self.bitness_flags & 32) != 0 { - flags |= InstrOpInfoFlags::OP_SIZE32; - } - } - InstrOpInfo::new(&self.mnemonic, instruction, flags) - } -} - #[allow(non_camel_case_types)] pub(super) struct SimpleInstrInfo_k1 { mnemonic: FormatterString, diff --git a/src/rust/iced-x86/src/formatter/nasm/enums.rs b/src/rust/iced-x86/src/formatter/nasm/enums.rs index cdc76aece..49d2e36e2 100644 --- a/src/rust/iced-x86/src/formatter/nasm/enums.rs +++ b/src/rust/iced-x86/src/formatter/nasm/enums.rs @@ -93,7 +93,6 @@ pub(crate) enum CtorKind { STIG1_2, STIG2_2a, STIG2_2b, - xbegin, XLAT, XY, YA, @@ -101,7 +100,7 @@ pub(crate) enum CtorKind { YX, } #[cfg_attr(feature = "cargo-fmt", rustfmt::skip)] -static GEN_DEBUG_CTOR_KIND: [&str; 70] = [ +static GEN_DEBUG_CTOR_KIND: [&str; 69] = [ "Previous", "Normal_1", "Normal_2", @@ -166,7 +165,6 @@ static GEN_DEBUG_CTOR_KIND: [&str; 70] = [ "STIG1_2", "STIG2_2a", "STIG2_2b", - "xbegin", "XLAT", "XY", "YA", diff --git a/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs b/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs index bed88f8ee..3e1496e70 100644 --- a/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs +++ b/src/rust/iced-x86/src/formatter/nasm/fmt_data.rs @@ -594,15 +594,15 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x03,// Sex1to8 // Insb_m8_DX - 0x44,// YD + 0x43,// YD 0x96, 0x01,// 150 = "insb" // Insw_m16_DX - 0x44,// YD + 0x43,// YD 0x97, 0x01,// 151 = "insw" // Insd_m32_DX - 0x44,// YD + 0x43,// YD 0x98, 0x01,// 152 = "insd" // Outsb_DX_m8 @@ -1570,35 +1570,35 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x00,// Previous // Movsb_m8_m8 - 0x45,// YX + 0x44,// YX 0xC7, 0x01,// 199 = "movsb" // Movsw_m16_m16 - 0x45,// YX + 0x44,// YX 0xC8, 0x01,// 200 = "movsw" // Movsd_m32_m32 - 0x45,// YX + 0x44,// YX 0x25,// 37 = "movsd" // Movsq_m64_m64 - 0x45,// YX + 0x44,// YX 0xC9, 0x01,// 201 = "movsq" // Cmpsb_m8_m8 - 0x42,// XY + 0x41,// XY 0xCB, 0x01,// 203 = "cmpsb" // Cmpsw_m16_m16 - 0x42,// XY + 0x41,// XY 0xCC, 0x01,// 204 = "cmpsw" // Cmpsd_m32_m32 - 0x42,// XY + 0x41,// XY 0x94, 0x06,// 788 = "cmpsd" // Cmpsq_m64_m64 - 0x42,// XY + 0x41,// XY 0xCD, 0x01,// 205 = "cmpsq" // Test_AL_imm8 @@ -1617,19 +1617,19 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x00,// None // Stosb_m8_AL - 0x43,// YA + 0x42,// YA 0xCF, 0x01,// 207 = "stosb" // Stosw_m16_AX - 0x43,// YA + 0x42,// YA 0xD0, 0x01,// 208 = "stosw" // Stosd_m32_EAX - 0x43,// YA + 0x42,// YA 0xD1, 0x01,// 209 = "stosd" // Stosq_m64_RAX - 0x43,// YA + 0x42,// YA 0xD2, 0x01,// 210 = "stosq" // Lodsb_AL_m8 @@ -1882,14 +1882,11 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0x06,// 0x6 = ShowNoMemSize_ForceSize, ShowMinMemSize_ForceSize // Xbegin_rel16 - 0x40,// xbegin + 0x01,// Normal_1 0xE5, 0x01,// 229 = "xbegin" - 0x10,// 0x10 // Xbegin_rel32 - 0x40,// xbegin - 0xE5, 0x01,// 229 = "xbegin" - 0x60,// 0x60 + 0x00,// Previous // Enterw_imm16_imm8 0x1B,// os_2 @@ -2256,7 +2253,7 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[ 0xF5, 0x01,// 245 = "salc" // Xlat_m8 - 0x41,// XLAT + 0x40,// XLAT 0xF7, 0x01,// 247 = "xlatb" // Fadd_m32fp diff --git a/src/rust/iced-x86/src/formatter/nasm/fmt_tbl.rs b/src/rust/iced-x86/src/formatter/nasm/fmt_tbl.rs index 199cddb22..0701b5bb7 100644 --- a/src/rust/iced-x86/src/formatter/nasm/fmt_tbl.rs +++ b/src/rust/iced-x86/src/formatter/nasm/fmt_tbl.rs @@ -412,11 +412,6 @@ fn read() -> Vec> { Box::new(SimpleInstrInfo_STIG2::with_flags(s, v)) } - CtorKind::xbegin => { - v = reader.read_compressed_u32(); - Box::new(SimpleInstrInfo_xbegin::new(v, s)) - } - CtorKind::XLAT => Box::new(SimpleInstrInfo_XLAT::new(s)), CtorKind::XY => Box::new(SimpleInstrInfo_XY::new(s)), CtorKind::YA => Box::new(SimpleInstrInfo_YA::new(s)), diff --git a/src/rust/iced-x86/src/formatter/nasm/info.rs b/src/rust/iced-x86/src/formatter/nasm/info.rs index b1fa08607..94c810906 100644 --- a/src/rust/iced-x86/src/formatter/nasm/info.rs +++ b/src/rust/iced-x86/src/formatter/nasm/info.rs @@ -1430,41 +1430,6 @@ impl InstrInfo for SimpleInstrInfo_far_mem { } } -#[allow(non_camel_case_types)] -pub(super) struct SimpleInstrInfo_xbegin { - mnemonic: FormatterString, - bitness_flags: u32, -} - -impl SimpleInstrInfo_xbegin { - pub(super) fn new(bitness_flags: u32, mnemonic: String) -> Self { - Self { mnemonic: FormatterString::new(mnemonic), bitness_flags } - } -} - -impl InstrInfo for SimpleInstrInfo_xbegin { - fn op_info<'a>(&'a self, _options: &FormatterOptions, instruction: &Instruction) -> InstrOpInfo<'a> { - let mut flags = InstrOpInfoFlags::NONE; - let mut branch_info = BranchSizeInfo::None; - let instr_bitness = get_bitness(instruction.code_size()); - if instr_bitness == 0 { - // Nothing - } else if instr_bitness == 64 { - if (self.bitness_flags & 16) != 0 { - flags |= InstrOpInfoFlags::OP_SIZE16; - } - } else if (instr_bitness & self.bitness_flags) == 0 { - if (self.bitness_flags & 16) != 0 { - branch_info = BranchSizeInfo::Word; - } else if (self.bitness_flags & 32) != 0 { - branch_info = BranchSizeInfo::Dword; - } - } - flags |= (branch_info as u32) << InstrOpInfoFlags::BRANCH_SIZE_INFO_SHIFT; - InstrOpInfo::new(&self.mnemonic, instruction, flags) - } -} - #[allow(non_camel_case_types)] pub(super) struct SimpleInstrInfo_movabs { mnemonic: FormatterString,