cells.json

{"nand3": {"description": "3-input NAND.", "file_prefix": "sky130_fd_sc_hd__nand3", "library": "sky130_fd_sc_hd", "name": "nand3", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand3"}, "o31ai": {"description": "3-input OR into 2-input NAND.", "equation": "Y = !((A1 | A2 | A3) & B1)", "file_prefix": "sky130_fd_sc_hd__o31ai", "library": "sky130_fd_sc_hd", "name": "o31ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o31ai"}, "or4bb": {"description": "4-input OR, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__or4bb", "library": "sky130_fd_sc_hd", "name": "or4bb", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or4bb"}, "tap": {"description": "Tap cell with no tap connections (no contacts on metal1).", "file_prefix": "sky130_fd_sc_hd__tap", "library": "sky130_fd_sc_hd", "name": "tap", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__tap"}, "or4": {"description": "4-input OR.", "file_prefix": "sky130_fd_sc_hd__or4", "library": "sky130_fd_sc_hd", "name": "or4", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or4"}, "sdfxtp": {"description": "Scan delay flop, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfxtp", "library": "sky130_fd_sc_hd", "name": "sdfxtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfxtp"}, "and4bb": {"description": "4-input AND, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__and4bb", "library": "sky130_fd_sc_hd", "name": "and4bb", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B_N", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and4bb"}, "macro_sparecell": {"description": "Macro cell for metal-mask-only revisioning, containing inverter, 2-input NOR, 2-input NAND, and constant cell.", "file_prefix": "sky130_fd_sc_hd__macro_sparecell", "library": "sky130_fd_sc_hd", "name": "macro_sparecell", "parameters": [], "ports": [["signal", "LO", "output", ""], ["power", "VGND", "input", "supply0"], ["power", "VNB", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VPWR", "input", "supply1"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__macro_sparecell"}, "dlymetal6s4s": {"description": "6-inverter delay with output from 4th inverter on horizontal route.", "file_prefix": "sky130_fd_sc_hd__dlymetal6s4s", "library": "sky130_fd_sc_hd", "name": "dlymetal6s4s", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlymetal6s4s"}, "nor4b": {"description": "4-input NOR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nor4b", "library": "sky130_fd_sc_hd", "name": "nor4b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor4b"}, "sdfbbp": {"description": "Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sdfbbp", "library": "sky130_fd_sc_hd", "name": "sdfbbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "CLK", "input", ""], ["signal", "SET_B", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfbbp"}, "fahcon": {"description": "Full adder, inverted carry in, inverted carry out.", "file_prefix": "sky130_fd_sc_hd__fahcon", "library": "sky130_fd_sc_hd", "name": "fahcon", "parameters": [], "ports": [["signal", "COUT_N", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CI", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fahcon"}, "or3b": {"description": "3-input OR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__or3b", "library": "sky130_fd_sc_hd", "name": "or3b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or3b"}, "dlygate4sd3": {"description": "Delay Buffer 4-stage 0.50um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__dlygate4sd3", "library": "sky130_fd_sc_hd", "name": "dlygate4sd3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlygate4sd3"}, "dlxtn": {"description": "Delay latch, inverted enable, single output.", "file_prefix": "sky130_fd_sc_hd__dlxtn", "library": "sky130_fd_sc_hd", "name": "dlxtn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "D", "input", ""], ["signal", "GATE_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlxtn"}, "a221o": {"description": "2-input AND into first two inputs of 3-input OR.", "equation": "X = ((A1 & A2) | (B1 & B2) | C1)", "file_prefix": "sky130_fd_sc_hd__a221o", "library": "sky130_fd_sc_hd", "name": "a221o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a221o"}, "dfbbn": {"description": "Delay flop, inverted set, inverted reset, inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfbbn", "library": "sky130_fd_sc_hd", "name": "dfbbn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "CLK_N", "input", ""], ["signal", "SET_B", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfbbn"}, "ebufn": {"description": "Tri-state buffer, negative enable.", "file_prefix": "sky130_fd_sc_hd__ebufn", "library": "sky130_fd_sc_hd", "name": "ebufn", "parameters": [], "ports": [["signal", "Z", "output", ""], ["signal", "A", "input", ""], ["signal", "TE_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__ebufn"}, "bufbuf": {"description": "Double buffer.", "file_prefix": "sky130_fd_sc_hd__bufbuf", "library": "sky130_fd_sc_hd", "name": "bufbuf", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__bufbuf"}, "a2111oi": {"description": "2-input AND into first input of 4-input NOR.", "equation": "Y = !((A1 & A2) | B1 | C1 | D1)", "file_prefix": "sky130_fd_sc_hd__a2111oi", "library": "sky130_fd_sc_hd", "name": "a2111oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a2111oi"}, "a21bo": {"description": "2-input AND into first input of 2-input OR, 2nd input inverted.", "equation": "X = ((A1 & A2) | (!B1_N))", "file_prefix": "sky130_fd_sc_hd__a21bo", "library": "sky130_fd_sc_hd", "name": "a21bo", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a21bo"}, "o31a": {"description": "3-input OR into 2-input AND.", "equation": "X = ((A1 | A2 | A3) & B1)", "file_prefix": "sky130_fd_sc_hd__o31a", "library": "sky130_fd_sc_hd", "name": "o31a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o31a"}, "dlrbp": {"description": "Delay latch, inverted reset, non-inverted enable, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dlrbp", "library": "sky130_fd_sc_hd", "name": "dlrbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "RESET_B", "input", ""], ["signal", "D", "input", ""], ["signal", "GATE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlrbp"}, "o221a": {"description": "2-input OR into first two inputs of 3-input AND.", "equation": "X = ((A1 | A2) & (B1 | B2) & C1)", "file_prefix": "sky130_fd_sc_hd__o221a", "library": "sky130_fd_sc_hd", "name": "o221a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o221a"}, "o32ai": {"description": "3-input OR and 2-input OR into 2-input NAND.", "equation": "Y = !((A1 | A2 | A3) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o32ai", "library": "sky130_fd_sc_hd", "name": "o32ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o32ai"}, "a21oi": {"description": "2-input AND into first input of 2-input NOR.", "equation": "Y = !((A1 & A2) | B1)", "file_prefix": "sky130_fd_sc_hd__a21oi", "library": "sky130_fd_sc_hd", "name": "a21oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a21oi"}, "tapvgnd": {"description": "Tap cell with tap to ground, isolated power connection 1 row down.", "file_prefix": "sky130_fd_sc_hd__tapvgnd", "library": "sky130_fd_sc_hd", "name": "tapvgnd", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__tapvgnd"}, "sedfxtp": {"description": "Scan delay flop, data enable, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sedfxtp", "library": "sky130_fd_sc_hd", "name": "sedfxtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sedfxtp"}, "lpflow_clkinvkapwr": {"description": "Clock tree inverter on keep-alive rail.", "file_prefix": "sky130_fd_sc_hd__lpflow_clkinvkapwr", "library": "sky130_fd_sc_hd", "name": "lpflow_clkinvkapwr", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "KAPWR", "input", "supply1"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_clkinvkapwr"}, "ha": {"description": "Half adder.", "file_prefix": "sky130_fd_sc_hd__ha", "library": "sky130_fd_sc_hd", "name": "ha", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__ha"}, "a21boi": {"description": "2-input AND into first input of 2-input NOR, 2nd input inverted.", "equation": "Y = !((A1 & A2) | (!B1_N))", "file_prefix": "sky130_fd_sc_hd__a21boi", "library": "sky130_fd_sc_hd", "name": "a21boi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a21boi"}, "a311oi": {"description": "3-input AND into first input of 3-input NOR.", "equation": "Y = !((A1 & A2 & A3) | B1 | C1)", "file_prefix": "sky130_fd_sc_hd__a311oi", "library": "sky130_fd_sc_hd", "name": "a311oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a311oi"}, "lpflow_inputiso0p": {"description": "Input isolator with non-inverted enable.", "equation": "X = (A & !SLEEP_B)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso0p", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso0p", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso0p"}, "a32o": {"description": "3-input AND into first input, and 2-input AND into 2nd input of 2-input OR.", "equation": "X = ((A1 & A2 & A3) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a32o", "library": "sky130_fd_sc_hd", "name": "a32o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a32o"}, "lpflow_clkbufkapwr": {"description": "Clock tree buffer on keep-alive power rail.", "file_prefix": "sky130_fd_sc_hd__lpflow_clkbufkapwr", "library": "sky130_fd_sc_hd", "name": "lpflow_clkbufkapwr", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "KAPWR", "input", "supply1"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_clkbufkapwr"}, "mux2": {"description": "2-input multiplexer.", "file_prefix": "sky130_fd_sc_hd__mux2", "library": "sky130_fd_sc_hd", "name": "mux2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A0", "input", ""], ["signal", "A1", "input", ""], ["signal", "S", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__mux2"}, "a22o": {"description": "2-input AND into both inputs of 2-input OR.", "equation": "X = ((A1 & A2) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a22o", "library": "sky130_fd_sc_hd", "name": "a22o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a22o"}, "dlclkp": {"description": "Clock gate.", "file_prefix": "sky130_fd_sc_hd__dlclkp", "library": "sky130_fd_sc_hd", "name": "dlclkp", "parameters": [], "ports": [["signal", "GCLK", "output", ""], ["signal", "GATE", "input", ""], ["signal", "CLK", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlclkp"}, "fa": {"description": "Full adder.", "file_prefix": "sky130_fd_sc_hd__fa", "library": "sky130_fd_sc_hd", "name": "fa", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CIN", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fa"}, "o2111a": {"description": "2-input OR into first input of 4-input AND.", "equation": "X = ((A1 | A2) & B1 & C1 & D1)", "file_prefix": "sky130_fd_sc_hd__o2111a", "library": "sky130_fd_sc_hd", "name": "o2111a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o2111a"}, "or2": {"description": "2-input OR.", "file_prefix": "sky130_fd_sc_hd__or2", "library": "sky130_fd_sc_hd", "name": "or2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or2"}, "sdfrtp": {"description": "Scan delay flop, inverted reset, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfrtp", "library": "sky130_fd_sc_hd", "name": "sdfrtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfrtp"}, "nand2b": {"description": "2-input NAND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nand2b", "library": "sky130_fd_sc_hd", "name": "nand2b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand2b"}, "lpflow_inputiso0n": {"description": "Input isolator with inverted enable.", "equation": "X = (A & SLEEP_B)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso0n", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso0n", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso0n"}, "nand4b": {"description": "4-input NAND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nand4b", "library": "sky130_fd_sc_hd", "name": "nand4b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand4b"}, "or4b": {"description": "4-input OR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__or4b", "library": "sky130_fd_sc_hd", "name": "or4b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or4b"}, "dfrtp": {"description": "Delay flop, inverted reset, single output.", "file_prefix": "sky130_fd_sc_hd__dfrtp", "library": "sky130_fd_sc_hd", "name": "dfrtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfrtp"}, "o21ba": {"description": "2-input OR into first input of 2-input AND, 2nd input inverted.", "equation": "X = ((A1 | A2) & !B1_N)", "file_prefix": "sky130_fd_sc_hd__o21ba", "library": "sky130_fd_sc_hd", "name": "o21ba", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21ba"}, "a21o": {"description": "2-input AND into first input of 2-input OR.", "equation": "X = ((A1 & A2) | B1)", "file_prefix": "sky130_fd_sc_hd__a21o", "library": "sky130_fd_sc_hd", "name": "a21o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a21o"}, "or2b": {"description": "2-input OR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__or2b", "library": "sky130_fd_sc_hd", "name": "or2b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or2b"}, "dlymetal6s2s": {"description": "6-inverter delay with output from 2nd stage on horizontal route.", "file_prefix": "sky130_fd_sc_hd__dlymetal6s2s", "library": "sky130_fd_sc_hd", "name": "dlymetal6s2s", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlymetal6s2s"}, "xnor3": {"description": "3-input exclusive NOR.", "file_prefix": "sky130_fd_sc_hd__xnor3", "library": "sky130_fd_sc_hd", "name": "xnor3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xnor3"}, "dfbbp": {"description": "Delay flop, inverted set, inverted reset, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfbbp", "library": "sky130_fd_sc_hd", "name": "dfbbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "CLK", "input", ""], ["signal", "SET_B", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfbbp"}, "a211o": {"description": "2-input AND into first input of 3-input OR.", "equation": "X = ((A1 & A2) | B1 | C1)", "file_prefix": "sky130_fd_sc_hd__a211o", "library": "sky130_fd_sc_hd", "name": "a211o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a211o"}, "edfxbp": {"description": "Delay flop with loopback enable, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__edfxbp", "library": "sky130_fd_sc_hd", "name": "edfxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__edfxbp"}, "sdfbbn": {"description": "Scan delay flop, inverted set, inverted reset, inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sdfbbn", "library": "sky130_fd_sc_hd", "name": "sdfbbn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "CLK_N", "input", ""], ["signal", "SET_B", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfbbn"}, "fill": {"description": "Fill cell.", "file_prefix": "sky130_fd_sc_hd__fill", "library": "sky130_fd_sc_hd", "name": "fill", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fill"}, "dlrbn": {"description": "Delay latch, inverted reset, inverted enable, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dlrbn", "library": "sky130_fd_sc_hd", "name": "dlrbn", "parameters": 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"sky130_fd_sc_hd__a221oi", "library": "sky130_fd_sc_hd", "name": "a221oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a221oi"}, "lpflow_lsbuf_lh_isowell_tap": {"description": "Level-shift buffer, low-to-high, isolated well on input buffer, vpb/vnb taps, double-row-height cell.", "file_prefix": "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap", "library": "sky130_fd_sc_hd", "name": "lpflow_lsbuf_lh_isowell_tap", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "LOWLVPWR", "input", "wire"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap"}, "clkinvlp": {"description": "Lower power Clock tree inverter.", "file_prefix": "sky130_fd_sc_hd__clkinvlp", "library": "sky130_fd_sc_hd", "name": "clkinvlp", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkinvlp"}, "and3b": {"description": "3-input AND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__and3b", "library": "sky130_fd_sc_hd", "name": "and3b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and3b"}, "a2bb2o": {"description": "2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input OR.", "equation": "X = ((!A1 & !A2) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a2bb2o", "library": "sky130_fd_sc_hd", "name": "a2bb2o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1_N", "input", ""], ["signal", "A2_N", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a2bb2o"}, "lpflow_lsbuf_lh_hl_isowell_tap": {"description": "Level-shift buffer, low-to-high, isolated well on input buffer, vpb/vnb taps, double-row-height cell.", "file_prefix": "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap", "library": "sky130_fd_sc_hd", "name": "lpflow_lsbuf_lh_hl_isowell_tap", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWRIN", "input", "wire"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap"}, "a31o": {"description": "3-input AND into first input of 2-input OR.", "equation": "X = ((A1 & A2 & A3) | B1)", "file_prefix": "sky130_fd_sc_hd__a31o", "library": "sky130_fd_sc_hd", "name": "a31o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a31o"}, 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"supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfrbp"}, "tapvgnd2": {"description": "Tap cell with tap to ground, isolated power connection 2 rows down.", "file_prefix": "sky130_fd_sc_hd__tapvgnd2", "library": "sky130_fd_sc_hd", "name": "tapvgnd2", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__tapvgnd2"}, "maj3": {"description": "3-input majority vote.", "file_prefix": "sky130_fd_sc_hd__maj3", "library": "sky130_fd_sc_hd", "name": "maj3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__maj3"}, "a2bb2oi": {"description": "2-input AND, both inputs inverted, into first input, and 2-input AND into 2nd input of 2-input NOR.", "equation": "Y = !((!A1 & !A2) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a2bb2oi", "library": "sky130_fd_sc_hd", "name": "a2bb2oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1_N", "input", ""], ["signal", "A2_N", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a2bb2oi"}, "sdfrbp": {"description": "Scan delay flop, inverted reset, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sdfrbp", "library": "sky130_fd_sc_hd", "name": "sdfrbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfrbp"}, "o211a": {"description": "2-input OR into first input of 3-input AND.", "equation": "X = ((A1 | A2) & B1 & C1)", "file_prefix": "sky130_fd_sc_hd__o211a", "library": "sky130_fd_sc_hd", "name": "o211a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o211a"}, "o311a": {"description": "3-input OR into 3-input AND.", "equation": "X = ((A1 | A2 | A3) & B1 & C1)", "file_prefix": "sky130_fd_sc_hd__o311a", "library": "sky130_fd_sc_hd", "name": "o311a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o311a"}, "dfrtn": {"description": "Delay flop, inverted reset, inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfrtn", "library": "sky130_fd_sc_hd", "name": "dfrtn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK_N", "input", ""], ["signal", "D", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfrtn"}, "decap": {"description": "Decoupling capacitance filler.", "file_prefix": "sky130_fd_sc_hd__decap", "library": "sky130_fd_sc_hd", "name": "decap", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__decap"}, "dlygate4sd1": {"description": "Delay Buffer 4-stage 0.15um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__dlygate4sd1", "library": "sky130_fd_sc_hd", "name": "dlygate4sd1", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlygate4sd1"}, "lpflow_decapkapwr": {"description": "Decoupling capacitance filler on keep-alive rail.", "file_prefix": "sky130_fd_sc_hd__lpflow_decapkapwr", "library": "sky130_fd_sc_hd", "name": "lpflow_decapkapwr", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "KAPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_decapkapwr"}, "sdfsbp": {"description": "Scan delay flop, inverted set, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sdfsbp", "library": "sky130_fd_sc_hd", "name": "sdfsbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "SET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfsbp"}, "dfxtp": {"description": "Delay flop, single output.", "file_prefix": "sky130_fd_sc_hd__dfxtp", "library": "sky130_fd_sc_hd", "name": "dfxtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfxtp"}, "o22a": {"description": "2-input OR into both inputs of 2-input AND.", "equation": "X = ((A1 | A2) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o22a", "library": "sky130_fd_sc_hd", "name": "o22a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o22a"}, "or3": {"description": "3-input OR.", "file_prefix": "sky130_fd_sc_hd__or3", "library": "sky130_fd_sc_hd", "name": "or3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or3"}, "conb": {"description": "Constant value, low, high outputs.", "file_prefix": "sky130_fd_sc_hd__conb", "library": "sky130_fd_sc_hd", "name": "conb", "parameters": [], "ports": [["signal", "HI", "output", ""], ["signal", "LO", "output", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__conb"}, "mux4": {"description": "4-input multiplexer.", "file_prefix": "sky130_fd_sc_hd__mux4", "library": "sky130_fd_sc_hd", "name": "mux4", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A0", "input", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "S0", "input", ""], ["signal", "S1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__mux4"}, "sdfxbp": {"description": "Scan delay flop, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sdfxbp", "library": "sky130_fd_sc_hd", "name": "sdfxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfxbp"}, "einvp": {"description": "Tri-state inverter, positive enable.", "file_prefix": "sky130_fd_sc_hd__einvp", "library": "sky130_fd_sc_hd", "name": "einvp", "parameters": [], "ports": [["signal", "Z", "output", ""], ["signal", "A", "input", ""], ["signal", "TE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__einvp"}, "dlxbn": {"description": "Delay latch, inverted enable, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dlxbn", "library": "sky130_fd_sc_hd", "name": "dlxbn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "GATE_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlxbn"}, "o22ai": {"description": "2-input OR into both inputs of 2-input NAND.", "equation": "Y = !((A1 | A2) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o22ai", "library": "sky130_fd_sc_hd", "name": "o22ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o22ai"}, "a2111o": {"description": "2-input AND into first input of 4-input OR.", "equation": "X = ((A1 & A2) | B1 | C1 | D1)", "file_prefix": "sky130_fd_sc_hd__a2111o", "library": "sky130_fd_sc_hd", "name": "a2111o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a2111o"}, "bufinv": {"description": "Buffer followed by inverter.", "file_prefix": "sky130_fd_sc_hd__bufinv", "library": "sky130_fd_sc_hd", "name": "bufinv", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__bufinv"}, "o2bb2a": {"description": "2-input NAND and 2-input OR into 2-input AND.", "equation": "X = (!(A1 & A2) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o2bb2a", "library": "sky130_fd_sc_hd", "name": "o2bb2a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1_N", "input", ""], ["signal", "A2_N", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o2bb2a"}, "nand2": {"description": "2-input NAND.", "file_prefix": "sky130_fd_sc_hd__nand2", "library": "sky130_fd_sc_hd", "name": "nand2", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand2"}, "nand4": {"description": "4-input NAND.", "file_prefix": "sky130_fd_sc_hd__nand4", "library": "sky130_fd_sc_hd", "name": "nand4", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand4"}, "dlxbp": {"description": "Delay latch, non-inverted enable, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dlxbp", "library": "sky130_fd_sc_hd", "name": "dlxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "GATE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlxbp"}, "o2bb2ai": {"description": "2-input NAND and 2-input OR into 2-input NAND.", "equation": "Y = !(!(A1 & A2) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o2bb2ai", "library": "sky130_fd_sc_hd", "name": "o2bb2ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1_N", "input", ""], ["signal", "A2_N", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o2bb2ai"}, "o32a": {"description": "3-input OR and 2-input OR into 2-input AND.", "equation": "X = ((A1 | A2 | A3) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o32a", "library": "sky130_fd_sc_hd", "name": "o32a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o32a"}, "lpflow_inputiso1p": {"description": "Input isolation, noninverted sleep.", "equation": "X = (A & !SLEEP)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso1p", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso1p", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso1p"}, "and2b": {"description": "2-input AND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__and2b", "library": "sky130_fd_sc_hd", "name": "and2b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and2b"}, "clkdlybuf4s15": {"description": "Clock Delay Buffer 4-stage 0.15um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s15", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s15", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s15"}, "o21bai": {"description": "2-input OR into first input of 2-input NAND, 2nd iput inverted.", "equation": "Y = !((A1 | A2) & !B1_N)", "file_prefix": "sky130_fd_sc_hd__o21bai", "library": "sky130_fd_sc_hd", "name": "o21bai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21bai"}, "and4": {"description": "4-input AND.", "file_prefix": "sky130_fd_sc_hd__and4", "library": "sky130_fd_sc_hd", "name": "and4", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and4"}, "o2111ai": {"description": "2-input OR into first input of 4-input NAND.", "equation": "Y = !((A1 | A2) & B1 & C1 & D1)", "file_prefix": "sky130_fd_sc_hd__o2111ai", "library": "sky130_fd_sc_hd", "name": "o2111ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o2111ai"}, "fah": {"description": "Full adder.", "file_prefix": "sky130_fd_sc_hd__fah", "library": "sky130_fd_sc_hd", "name": "fah", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CI", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fah"}, "inv": {"description": "Inverter.", "file_prefix": "sky130_fd_sc_hd__inv", "library": "sky130_fd_sc_hd", "name": "inv", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__inv"}, "xor3": {"description": "3-input exclusive OR.", "equation": "X = A ^ B ^ C", "file_prefix": "sky130_fd_sc_hd__xor3", "library": "sky130_fd_sc_hd", "name": "xor3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xor3"}, "dlrtn": {"description": "Delay latch, inverted reset, inverted enable, single output.", "file_prefix": "sky130_fd_sc_hd__dlrtn", "library": "sky130_fd_sc_hd", "name": "dlrtn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "RESET_B", "input", ""], ["signal", "D", "input", ""], ["signal", "GATE_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlrtn"}, "nor2b": {"description": "2-input NOR, first input inverted.", "equation": "Y = !(A | B | C | !D)", "file_prefix": "sky130_fd_sc_hd__nor2b", "library": "sky130_fd_sc_hd", "name": "nor2b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor2b"}, "o41ai": {"description": "4-input OR into 2-input NAND.", "equation": "Y = !((A1 | A2 | A3 | A4) & B1)", "file_prefix": "sky130_fd_sc_hd__o41ai", "library": "sky130_fd_sc_hd", "name": "o41ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o41ai"}, "and4b": {"description": "4-input AND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__and4b", "library": "sky130_fd_sc_hd", "name": "and4b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and4b"}, "tapvpwrvgnd": {"description": "Substrate and well tap cell.", "file_prefix": "sky130_fd_sc_hd__tapvpwrvgnd", "library": "sky130_fd_sc_hd", "name": "tapvpwrvgnd", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__tapvpwrvgnd"}, "a211oi": {"description": "2-input AND into first input of 3-input NOR.", "equation": "Y = !((A1 & A2) | B1 | C1)", "file_prefix": "sky130_fd_sc_hd__a211oi", "library": "sky130_fd_sc_hd", "name": "a211oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a211oi"}, "sdlclkp": {"description": "Scan gated clock.", "file_prefix": "sky130_fd_sc_hd__sdlclkp", "library": "sky130_fd_sc_hd", "name": "sdlclkp", "parameters": [], "ports": [["signal", "GCLK", "output", ""], ["signal", "SCE", "input", ""], ["signal", "GATE", "input", ""], ["signal", "CLK", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdlclkp"}, "and3": {"description": "3-input AND.", "file_prefix": "sky130_fd_sc_hd__and3", "library": "sky130_fd_sc_hd", "name": "and3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and3"}, "nor3": {"description": "3-input NOR.", "equation": "Y = !(A | B | C | !D)", "file_prefix": "sky130_fd_sc_hd__nor3", "library": "sky130_fd_sc_hd", "name": "nor3", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor3"}, "a31oi": {"description": "3-input AND into first input of 2-input NOR.", "equation": "Y = !((A1 & A2 & A3) | B1)", "file_prefix": "sky130_fd_sc_hd__a31oi", "library": "sky130_fd_sc_hd", "name": "a31oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a31oi"}, "dfstp": {"description": "Delay flop, inverted set, single output.", "file_prefix": "sky130_fd_sc_hd__dfstp", "library": "sky130_fd_sc_hd", "name": "dfstp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfstp"}, "nor2": {"description": "2-input NOR.", "file_prefix": "sky130_fd_sc_hd__nor2", "library": "sky130_fd_sc_hd", "name": "nor2", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor2"}, "edfxtp": {"description": "Delay flop with loopback enable, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__edfxtp", "library": "sky130_fd_sc_hd", "name": "edfxtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__edfxtp"}, "o21ai": {"description": "2-input OR into first input of 2-input NAND.", "equation": "Y = !((A1 | A2) & B1)", "file_prefix": "sky130_fd_sc_hd__o21ai", "library": "sky130_fd_sc_hd", "name": "o21ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21ai"}, "lpflow_isobufsrckapwr": {"description": "Input isolation, noninverted sleep on keep-alive power rail.", "equation": "X = (!A | SLEEP)", "file_prefix": "sky130_fd_sc_hd__lpflow_isobufsrckapwr", "library": "sky130_fd_sc_hd", "name": "lpflow_isobufsrckapwr", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "SLEEP", "input", ""], ["signal", "A", "input", ""], ["power", "KAPWR", "input", "supply1"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_isobufsrckapwr"}, "dlygate4sd2": {"description": "Delay Buffer 4-stage 0.18um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__dlygate4sd2", "library": "sky130_fd_sc_hd", "name": "dlygate4sd2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlygate4sd2"}, "clkbuf": {"description": "Clock tree buffer.", "file_prefix": "sky130_fd_sc_hd__clkbuf", "library": "sky130_fd_sc_hd", "name": "clkbuf", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkbuf"}, "buf": {"description": "Buffer.", "file_prefix": "sky130_fd_sc_hd__buf", "library": "sky130_fd_sc_hd", "name": "buf", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__buf"}, "diode": {"description": "Antenna tie-down diode.", "file_prefix": "sky130_fd_sc_hd__diode", "library": "sky130_fd_sc_hd", "name": "diode", "parameters": [], "ports": [["signal", "DIODE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__diode"}, "lpflow_inputisolatch": {"description": "Latching input isolator with inverted enable.", "file_prefix": "sky130_fd_sc_hd__lpflow_inputisolatch", "library": "sky130_fd_sc_hd", "name": "lpflow_inputisolatch", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "D", "input", ""], ["signal", "SLEEP_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputisolatch"}, "a22oi": {"description": "2-input AND into both inputs of 2-input NOR.", "equation": "Y = !((A1 & A2) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a22oi", "library": "sky130_fd_sc_hd", "name": "a22oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a22oi"}, "nand3b": {"description": "3-input NAND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nand3b", "library": "sky130_fd_sc_hd", "name": "nand3b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand3b"}, "einvn": {"description": "Tri-state inverter, negative enable.", "file_prefix": "sky130_fd_sc_hd__einvn", "library": "sky130_fd_sc_hd", "name": "einvn", "parameters": [], "ports": [["signal", "Z", "output", ""], ["signal", "A", "input", ""], ["signal", "TE_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__einvn"}, "nor4": {"description": "4-input NOR.", "equation": "Y = !(A | B | C | D)", "file_prefix": "sky130_fd_sc_hd__nor4", "library": "sky130_fd_sc_hd", "name": "nor4", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor4"}, "dfsbp": {"description": "Delay flop, inverted set, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfsbp", "library": "sky130_fd_sc_hd", "name": "dfsbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfsbp"}, "a222oi": {"description": "2-input AND into all inputs of 3-input NOR.", "equation": "Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))", "file_prefix": "sky130_fd_sc_hd__a222oi", "library": "sky130_fd_sc_hd", "name": "a222oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["signal", "C2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a222oi"}, "o21a": {"description": "2-input OR into first input of 2-input AND.", "equation": "X = ((A1 | A2) & B1)", "file_prefix": "sky130_fd_sc_hd__o21a", "library": "sky130_fd_sc_hd", "name": "o21a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21a"}, "o211ai": {"description": "2-input OR into first input of 3-input NAND.", "equation": "Y = !((A1 | A2) & B1 & C1)", "file_prefix": "sky130_fd_sc_hd__o211ai", "library": "sky130_fd_sc_hd", "name": "o211ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o211ai"}, "lpflow_isobufsrc": {"description": "Input isolation, noninverted sleep.", "equation": "X = (!A | SLEEP)", "file_prefix": "sky130_fd_sc_hd__lpflow_isobufsrc", "library": "sky130_fd_sc_hd", "name": "lpflow_isobufsrc", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "SLEEP", "input", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_isobufsrc"}, "dfxbp": {"description": "Delay flop, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfxbp", "library": "sky130_fd_sc_hd", "name": "dfxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfxbp"}, "lpflow_inputiso1n": {"description": "Input isolation, inverted sleep.", "equation": "X = (A & SLEEP_B)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso1n", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso1n", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso1n"}, "sdfrtn": {"description": "Scan delay flop, inverted reset, inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfrtn", "library": "sky130_fd_sc_hd", "name": "sdfrtn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK_N", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfrtn"}, "probec_p": {"description": "Virtual current probe point.", "file_prefix": "sky130_fd_sc_hd__probec_p", "library": "sky130_fd_sc_hd", "name": "probec_p", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VGND", "input", "supply0"], ["power", "VNB", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VPWR", "input", "supply1"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__probec_p"}, "fahcin": {"description": "Full adder, inverted carry in.", "file_prefix": "sky130_fd_sc_hd__fahcin", "library": "sky130_fd_sc_hd", "name": "fahcin", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CIN", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fahcin"}, "clkinv": {"description": "Clock tree inverter.", "file_prefix": "sky130_fd_sc_hd__clkinv", "library": "sky130_fd_sc_hd", "name": "clkinv", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkinv"}, "a32oi": {"description": "3-input AND into first input, and 2-input AND into 2nd input of 2-input NOR.", "equation": "Y = !((A1 & A2 & A3) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a32oi", "library": "sky130_fd_sc_hd", "name": "a32oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a32oi"}, "lpflow_lsbuf_lh_isowell": {"description": "Level-shift buffer, low-to-high, isolated well on input buffer, no taps, double-row-height cell.", "file_prefix": "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell", "library": "sky130_fd_sc_hd", "name": "lpflow_lsbuf_lh_isowell", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "LOWLVPWR", "input", "wire"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell"}, "dlymetal6s6s": {"description": "6-inverter delay with output from 6th inverter on horizontal route.", "file_prefix": "sky130_fd_sc_hd__dlymetal6s6s", "library": "sky130_fd_sc_hd", "name": "dlymetal6s6s", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlymetal6s6s"}, "o41a": {"description": "4-input OR into 2-input AND.", "equation": "X = ((A1 | A2 | A3 | A4) & B1)", "file_prefix": "sky130_fd_sc_hd__o41a", "library": "sky130_fd_sc_hd", "name": "o41a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o41a"}, "sdfstp": {"description": "Scan delay flop, inverted set, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfstp", "library": "sky130_fd_sc_hd", "name": "sdfstp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "SET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfstp"}, "dlrtp": {"description": "Delay latch, inverted reset, non-inverted enable, single output.", "file_prefix": "sky130_fd_sc_hd__dlrtp", "library": "sky130_fd_sc_hd", "name": "dlrtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "RESET_B", "input", ""], ["signal", "D", "input", ""], ["signal", "GATE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlrtp"}, "sedfxbp": {"description": "Scan delay flop, data enable, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sedfxbp", "library": "sky130_fd_sc_hd", "name": "sedfxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sedfxbp"}, "lpflow_bleeder": {"description": "Current bleeder (weak pulldown to ground).", "file_prefix": "sky130_fd_sc_hd__lpflow_bleeder", "library": "sky130_fd_sc_hd", "name": "lpflow_bleeder", "parameters": [], "ports": [["signal", "SHORT", "input", ""], ["power", "VPWR", "inout", "wire"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_bleeder"}, "nor4bb": {"description": "4-input NOR, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__nor4bb", "library": "sky130_fd_sc_hd", "name": "nor4bb", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor4bb"}, "clkdlybuf4s18": {"description": "Clock Delay Buffer 4-stage 0.18um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s18", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s18", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s18"}, "xor2": {"description": "2-input exclusive OR.", "equation": "X = A ^ B", "file_prefix": "sky130_fd_sc_hd__xor2", "library": "sky130_fd_sc_hd", "name": "xor2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xor2"}, "and2": {"description": "2-input AND.", "file_prefix": "sky130_fd_sc_hd__and2", "library": "sky130_fd_sc_hd", "name": "and2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and2"}, "clkdlybuf4s25": {"description": "Clock Delay Buffer 4-stage 0.25um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s25", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s25", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s25"}, "a41o": {"description": "4-input AND into first input of 2-input OR.", "equation": "X = ((A1 & A2 & A3 & A4) | B1)", "file_prefix": "sky130_fd_sc_hd__a41o", "library": "sky130_fd_sc_hd", "name": "a41o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a41o"}, "nand4bb": {"description": "4-input NAND, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__nand4bb", "library": "sky130_fd_sc_hd", "name": "nand4bb", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B_N", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand4bb"}, "mux2i": {"description": "2-input multiplexer, output inverted.", "file_prefix": "sky130_fd_sc_hd__mux2i", "library": "sky130_fd_sc_hd", "name": "mux2i", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A0", "input", ""], ["signal", "A1", "input", ""], ["signal", "S", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__mux2i"}, "o221ai": {"description": "2-input OR into first two inputs of 3-input NAND.", "equation": "Y = !((A1 | A2) & (B1 | B2) & C1)", "file_prefix": "sky130_fd_sc_hd__o221ai", "library": "sky130_fd_sc_hd", "name": "o221ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o221ai"}, "xnor2": {"description": "2-input exclusive NOR.", "equation": "Y = !(A ^ B)", "file_prefix": "sky130_fd_sc_hd__xnor2", "library": "sky130_fd_sc_hd", "name": "xnor2", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xnor2"}, "o311ai": {"description": "3-input OR into 3-input NAND.", "equation": "Y = !((A1 | A2 | A3) & B1 & C1)", "file_prefix": "sky130_fd_sc_hd__o311ai", "library": "sky130_fd_sc_hd", "name": "o311ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o311ai"}, "nor3b": {"description": "3-input NOR, first input inverted.", "equation": "Y = (!(A | B)) & !C)", "file_prefix": "sky130_fd_sc_hd__nor3b", "library": "sky130_fd_sc_hd", "name": "nor3b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor3b"}, "a311o": {"description": "3-input AND into first input of 3-input OR.", "equation": "X = ((A1 & A2 & A3) | B1 | C1)", "file_prefix": "sky130_fd_sc_hd__a311o", "library": "sky130_fd_sc_hd", "name": "a311o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a311o"}, "clkdlybuf4s50": {"description": "Clock Delay Buffer 4-stage 0.59um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s50", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s50", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s50"}, "a41oi": {"description": "4-input AND into first input of 2-input NOR.", "equation": "Y = !((A1 & A2 & A3 & A4) | B1)", "file_prefix": "sky130_fd_sc_hd__a41oi", "library": "sky130_fd_sc_hd", "name": "a41oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a41oi"}}