CPLD testbench not adapted to top module

[l-miara]

What type of issue is this?

permanent - occurring repeatedly

What issue are you facing?

When trying to simulate the CPLD top module with the testbench (both in firmware/cpld/sgpio_if), I was faced with an error.
Looking more into it, I noticed that the ports of the component decalred in the testbench do not match the ports of the actual top module (it seems to match the top module of commit 19f2852 and older).
Is there a way to find a testbench that match the current top module ?

What are the steps to reproduce this?

Open the sgpio_if.xise project with ise and try to simulate the top module.

Can you provide any logs? (output, errors, etc.)

ERROR:HDLCompiler:1156 - "/home/vboxuser/Downloads/cpld/sgpio_if/top_tb.vhd" Line 35: Formal port <HOST_DECIM_SEL> does not exist in entity . Please compare the definition of block to its component declaration and its instantion to detect the mismatch.
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit top_tb in library work failed

[martinling]

I think the testbench was not updated when the CPLD code was changed in #381 to remove the decimation feature, and it wouldn't surprise me if you're the first person who's tried to run it since.

I'm marking this as a bug.

I think we're unlikely to find time to work on this, since the current CPLD code is working fine, but if anyone wants to update the testbench, a PR for that would be welcome.