From ace41b22aeb1f5152c4ce3c1e35e618d8fb11309 Mon Sep 17 00:00:00 2001 From: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> Date: Tue, 24 Sep 2024 14:54:05 -0500 Subject: [PATCH] fix(CMSIS): Fix `AFE_ADC_n_CTRL.ref_sel` enum fields and remove deprecated registers (#1069) --- .../Maxim/MAX32675/Include/aes_key_regs.h | 114 ------------------ .../Maxim/MAX32675/Include/afe_adc_one_regs.h | 25 ++-- .../MAX32675/Include/afe_adc_zero_regs.h | 47 ++++---- .../Device/Maxim/MAX32675/Include/crc_regs.h | 4 +- .../Device/Maxim/MAX32675/Include/dma_regs.h | 2 +- .../Maxim/MAX32675/Include/max32675.svd | 8 +- .../Maxim/MAX32680/Include/aes_key_regs.h | 114 ------------------ .../Maxim/MAX32680/Include/afe_adc_one_regs.h | 16 +-- .../MAX32680/Include/afe_adc_zero_regs.h | 18 +-- .../Device/Maxim/MAX32680/Include/crc_regs.h | 4 +- .../Device/Maxim/MAX32680/Include/dma_regs.h | 2 +- .../Maxim/MAX32680/Include/lpcmp_regs.h | 8 +- .../Maxim/MAX32680/Include/max32680.svd | 12 +- .../Source/AFE/afe_adc_one_reva.svd | 21 ++-- .../Source/AFE/afe_adc_zero_reva.svd | 21 ++-- 15 files changed, 98 insertions(+), 318 deletions(-) delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_key_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_key_regs.h diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_key_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_key_regs.h deleted file mode 100644 index ca5707be90..0000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_key_regs.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * @file aes_key_regs.h - * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. - * @note This file is @deprecated. - */ - -/****************************************************************************** - * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_AES_KEY_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_AES_KEY_REGS_H_ - -#warning "DEPRECATED(1-10-2023): aes_key_regs.h - Scheduled for removal. Please use aeskeys_regs.h." - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup aes_key - * @defgroup aes_key_registers AES_KEY_Registers - * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. - * @details AES Key Registers. - */ - -/** - * @ingroup aes_key_registers - * Structure type to access the AES_KEY Registers. - */ -#if defined(__GNUC__) -__attribute__((deprecated("mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023"))) -#else -#warning "mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023" -#endif -typedef struct { - __IO uint32_t aes_key0; /**< \b 0x00: AES_KEY AES_KEY0 Register */ - __IO uint32_t aes_key1; /**< \b 0x04: AES_KEY AES_KEY1 Register */ - __IO uint32_t aes_key2; /**< \b 0x08: AES_KEY AES_KEY2 Register */ - __IO uint32_t aes_key3; /**< \b 0x0C: AES_KEY AES_KEY3 Register */ - __IO uint32_t aes_key4; /**< \b 0x10: AES_KEY AES_KEY4 Register */ - __IO uint32_t aes_key5; /**< \b 0x14: AES_KEY AES_KEY5 Register */ - __IO uint32_t aes_key6; /**< \b 0x18: AES_KEY AES_KEY6 Register */ - __IO uint32_t aes_key7; /**< \b 0x1C: AES_KEY AES_KEY7 Register */ -} mxc_aes_key_regs_t; - -/* Register offsets for module AES_KEY */ -/** - * @ingroup aes_key_registers - * @defgroup AES_KEY_Register_Offsets Register Offsets - * @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address. - * @{ - */ -#define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: 0x0000 */ -#define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: 0x0004 */ -#define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: 0x0008 */ -#define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: 0x000C */ -#define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: 0x0010 */ -#define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: 0x0014 */ -#define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: 0x0018 */ -#define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: 0x001C */ -/**@} end of group aes_key_registers */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_AES_KEY_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h index b7f2b95cf9..27c4e42333 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h @@ -7,9 +7,7 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -352,20 +350,20 @@ extern "C" { */ #define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS 0 /**< CTRL_REF_SEL Position */ #define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */ #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */ #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */ #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AGND Setting */ #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */ #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ #define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS 3 /**< CTRL_REFBUFN_EN Position */ #define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */ @@ -563,7 +561,10 @@ extern "C" { * @{ */ #define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS 0 /**< PART_ID_REV_ID Position */ -#define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID ((uint32_t)(0x7UL << MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ +#define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ + +#define MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS 5 /**< PART_ID_ADC_SEL Position */ +#define MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS)) /**< PART_ID_ADC_SEL Mask */ /**@} end of group AFE_ADC_ONE_PART_ID_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h index 76639b8630..ab92522de2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h @@ -7,9 +7,7 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -93,7 +91,6 @@ extern "C" { #define MXC_R_AFE_ADC_ZERO_PGA ((uint32_t)0x000E0001UL) /**< Offset from AFE_ADC_ZERO Base Address: 0xE0001 */ #define MXC_R_AFE_ADC_ZERO_WAIT_EXT ((uint32_t)0x000F0001UL) /**< Offset from AFE_ADC_ZERO Base Address: 0xF0001 */ #define MXC_R_AFE_ADC_ZERO_WAIT_START ((uint32_t)0x00100001UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x100001 */ -#define MXC_R_AFE_ADC_ZERO_PART_ID ((uint32_t)0x00110003UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x110003 */ #define MXC_R_AFE_ADC_ZERO_SYSC_SEL ((uint32_t)0x00120003UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x120003 */ #define MXC_R_AFE_ADC_ZERO_SYS_OFF_A ((uint32_t)0x00130003UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x130003 */ #define MXC_R_AFE_ADC_ZERO_SYS_OFF_B ((uint32_t)0x00140003UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x140003 */ @@ -194,6 +191,7 @@ extern "C" { #define MXC_R_AFE_ADC_ZERO_ANA_TRIM ((uint32_t)0x00790002UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x790002 */ #define MXC_R_AFE_ADC_ZERO_SYS_CTRL ((uint32_t)0x007A0001UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x7A0001 */ #define MXC_R_AFE_ADC_ZERO_TS_CTRL ((uint32_t)0x007C0001UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x7C0001 */ +#define MXC_R_AFE_ADC_ZERO_PART_ID ((uint32_t)0x00910003UL) /**< Offset from AFE_ADC_ZERO Base Address: 0x910003 */ /**@} end of group afe_adc_zero_registers */ /** @@ -352,20 +350,20 @@ extern "C" { */ #define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS 0 /**< CTRL_REF_SEL Position */ #define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */ #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */ #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */ #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AGND Setting */ #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */ #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ #define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS 3 /**< CTRL_REFBUFN_EN Position */ #define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */ @@ -556,17 +554,6 @@ extern "C" { /**@} end of group AFE_ADC_ZERO_WAIT_EXT_Register */ -/** - * @ingroup afe_adc_zero_registers - * @defgroup AFE_ADC_ZERO_PART_ID AFE_ADC_ZERO_PART_ID - * @brief Silicon Revision ID - * @{ - */ -#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS 0 /**< PART_ID_REV_ID Position */ -#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID ((uint32_t)(0x3FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ - -/**@} end of group AFE_ADC_ZERO_PART_ID_Register */ - /** * @ingroup afe_adc_zero_registers * @defgroup AFE_ADC_ZERO_SYSC_SEL AFE_ADC_ZERO_SYSC_SEL @@ -2041,6 +2028,20 @@ extern "C" { /**@} end of group AFE_ADC_ZERO_TS_CTRL_Register */ +/** + * @ingroup afe_adc_zero_registers + * @defgroup AFE_ADC_ZERO_PART_ID AFE_ADC_ZERO_PART_ID + * @brief Silicon Revision ID + * @{ + */ +#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS 0 /**< PART_ID_REV_ID Position */ +#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ + +#define MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL_POS 5 /**< PART_ID_ADC_SEL Position */ +#define MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL_POS)) /**< PART_ID_ADC_SEL Mask */ + +/**@} end of group AFE_ADC_ZERO_PART_ID_Register */ + #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h index 94dc7c3c72..0ebb5ddb9d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h @@ -77,8 +77,8 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ union { __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h index 955e81b904..38a910b1f6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h @@ -88,7 +88,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd index b59d67db51..a1951f062f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd @@ -361,9 +361,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -379,9 +377,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_key_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_key_regs.h deleted file mode 100644 index effac90f49..0000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_key_regs.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * @file aes_key_regs.h - * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. - * @note This file is @deprecated. - */ - -/****************************************************************************** - * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AES_KEY_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AES_KEY_REGS_H_ - -#warning "DEPRECATED(1-10-2023): aes_key_regs.h - Scheduled for removal. Please use aeskeys_regs.h." - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup aes_key - * @defgroup aes_key_registers AES_KEY_Registers - * @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module. - * @details AES Key Registers. - */ - -/** - * @ingroup aes_key_registers - * Structure type to access the AES_KEY Registers. - */ -#if defined(__GNUC__) -__attribute__((deprecated("mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023"))) -#else -#warning "mxc_aes_key_regs_t struct and aes_key_regs.h no longer supported. Use aeskeys_regs.h and MXC_AESKEYS (mxc_aeskeys_regs_t) for AES Key Access. 1-10-2023" -#endif -typedef struct { - __IO uint32_t aes_key0; /**< \b 0x00: AES_KEY AES_KEY0 Register */ - __IO uint32_t aes_key1; /**< \b 0x04: AES_KEY AES_KEY1 Register */ - __IO uint32_t aes_key2; /**< \b 0x08: AES_KEY AES_KEY2 Register */ - __IO uint32_t aes_key3; /**< \b 0x0C: AES_KEY AES_KEY3 Register */ - __IO uint32_t aes_key4; /**< \b 0x10: AES_KEY AES_KEY4 Register */ - __IO uint32_t aes_key5; /**< \b 0x14: AES_KEY AES_KEY5 Register */ - __IO uint32_t aes_key6; /**< \b 0x18: AES_KEY AES_KEY6 Register */ - __IO uint32_t aes_key7; /**< \b 0x1C: AES_KEY AES_KEY7 Register */ -} mxc_aes_key_regs_t; - -/* Register offsets for module AES_KEY */ -/** - * @ingroup aes_key_registers - * @defgroup AES_KEY_Register_Offsets Register Offsets - * @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address. - * @{ - */ -#define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: 0x0000 */ -#define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: 0x0004 */ -#define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: 0x0008 */ -#define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: 0x000C */ -#define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: 0x0010 */ -#define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: 0x0014 */ -#define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: 0x0018 */ -#define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: 0x001C */ -/**@} end of group aes_key_registers */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AES_KEY_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h index a976811d43..20fc136b9b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_one_regs.h @@ -352,20 +352,20 @@ extern "C" { */ #define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS 0 /**< CTRL_REF_SEL Position */ #define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */ #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */ #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */ #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AGND Setting */ #define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */ #define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ #define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS 3 /**< CTRL_REFBUFN_EN Position */ #define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h index 8dcd5b7870..9b3298a5e7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/afe_adc_zero_regs.h @@ -352,20 +352,20 @@ extern "C" { */ #define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS 0 /**< CTRL_REF_SEL Position */ #define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */ #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */ #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */ #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */ #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AGND Setting */ #define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */ #define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */ -#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */ -#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */ +#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */ +#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */ #define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS 3 /**< CTRL_REFBUFN_EN Position */ #define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */ @@ -563,7 +563,7 @@ extern "C" { * @{ */ #define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS 0 /**< PART_ID_REV_ID Position */ -#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID ((uint32_t)(0x7UL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ +#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID ((uint32_t)(0x3FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ /**@} end of group AFE_ADC_ZERO_PART_ID_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h index 58ead5cb43..adf5ca1c91 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/crc_regs.h @@ -77,8 +77,8 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ union { __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h index b7a6fd02d7..f0f6b9b475 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/dma_regs.h @@ -88,7 +88,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h index e28886a51c..bb3e1696d0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/lpcmp_regs.h @@ -99,14 +99,14 @@ typedef struct { #define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ #define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ -#define MXC_F_LPCMP_CTRL_INT_EN_POS 6 /**< CTRL_INT_EN Position */ -#define MXC_F_LPCMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ +#define MXC_F_LPCMP_CTRL_INTEN_POS 6 /**< CTRL_INTEN Position */ +#define MXC_F_LPCMP_CTRL_INTEN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTEN_POS)) /**< CTRL_INTEN Mask */ #define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ #define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ -#define MXC_F_LPCMP_CTRL_INT_FL_POS 15 /**< CTRL_INT_FL Position */ -#define MXC_F_LPCMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_FL_POS)) /**< CTRL_INT_FL Mask */ +#define MXC_F_LPCMP_CTRL_INTFL_POS 15 /**< CTRL_INTFL Position */ +#define MXC_F_LPCMP_CTRL_INTFL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTFL_POS)) /**< CTRL_INTFL Mask */ /**@} end of group LPCMP_CTRL_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd index 9ee591378c..b375763e25 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd @@ -700,9 +700,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -718,9 +716,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 @@ -6681,7 +6677,7 @@ 1 - INT_EN + INTEN IRQ Enable. 6 1 @@ -6693,7 +6689,7 @@ 1 - INT_FL + INTFL IRQ Flag 15 1 diff --git a/Libraries/PeriphDrivers/Source/AFE/afe_adc_one_reva.svd b/Libraries/PeriphDrivers/Source/AFE/afe_adc_one_reva.svd index e78cee39a1..b15783d5fb 100644 --- a/Libraries/PeriphDrivers/Source/AFE/afe_adc_one_reva.svd +++ b/Libraries/PeriphDrivers/Source/AFE/afe_adc_one_reva.svd @@ -278,7 +278,7 @@ 3 - REF0P_AND_REF0N + AIN0P_AND_AIN1N Description not included 0 @@ -288,7 +288,7 @@ 1 - REF2P_AND_REF2N + REF0P_AND_REF0N Description not included 2 @@ -298,7 +298,7 @@ 3 - REF0P_AND_AGND + AIN0P_AND_AGND Description not included 4 @@ -308,7 +308,7 @@ 5 - REF2P_AND_AGND + REF0P_AND_AGND Description not included 6 @@ -700,9 +700,16 @@ REV_ID - Description not included + Revision ID. 0 - 3 + 5 + read-only + + + ADC_SEL + ADC Selected. + 5 + 1 read-only @@ -2811,4 +2818,4 @@ - + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd b/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd index 287bf658b2..e8d6703cb1 100644 --- a/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd +++ b/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd @@ -278,7 +278,7 @@ 3 - REF0P_AND_REF0N + AIN0P_AND_AIN1N Description not included 0 @@ -288,7 +288,7 @@ 1 - REF2P_AND_REF2N + REF0P_AND_REF0N Description not included 2 @@ -298,7 +298,7 @@ 3 - REF0P_AND_AGND + AIN0P_AND_AGND Description not included 4 @@ -308,7 +308,7 @@ 5 - REF2P_AND_AGND + REF0P_AND_AGND Description not included 6 @@ -696,13 +696,20 @@ PART_ID Silicon Revision ID - 0x00110003 + 0x00910003 REV_ID - Description not included + Revision ID. 0 - 6 + 5 + read-only + + + ADC_SEL + ADC Selected. + 5 + 1 read-only