Negation bar wrong in DTACK_SEL signals

[jotego]

The / bar on top of DTACK_SEL signals is wrong on page 12. At the output of inverter M85, it should be /DTACK_SEL0, and then DTACK_SEL0 at the output of S99. Then the signals at the input of S105 (same page) should have the / swapped too. Otherwise, the comment on top of S105 does not hold true. As it is now, the S105 output is 1-clock delay for DTACK_SEL=3, for instance.

[furrtek]

The values mentioned in that comment were meant to reflect the settings in the registers (bits [3:2]), not the DTACK_SELx signals. If I'm not mistaken, those end up inverted after the NAND-based muxes.

Got to agree that this wasn't clear at all. I double-checked how the S105 cell was connected to confirm, and updated the note on the schematic.