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While simulating your models for this pair of chips, I found that the master chip starts the scaling count on SPR_ZX_ACC before the drawing part starts rendering. So the CARY signal gets a bit ahead of time. Not only that, but the SPR_ZX_ACC loads the next sprite data before the current one is completely rendered, which has the effect of potentially missing some CARY assertions for the last few pixels.
Whether this is the real behavior or just some logic missing between these two parts, I don't know. But I thought it was worth mentioning it, in case you have seen funny behaviour related to the scaling logic.
Thanks for the report Jose.
There shouldn't be any logic missing but hook-up or verilog mistakes are very possible. I've only partially tested vertical scaling in simulation, and TMNT almost never uses scaling at all, so I must have missed the problem.
I'll have access to a real computer to investigate after the 22nd.
While simulating your models for this pair of chips, I found that the master chip starts the scaling count on SPR_ZX_ACC before the drawing part starts rendering. So the CARY signal gets a bit ahead of time. Not only that, but the SPR_ZX_ACC loads the next sprite data before the current one is completely rendered, which has the effect of potentially missing some CARY assertions for the last few pixels.
The whole file with the waveforms is here.
Whether this is the real behavior or just some logic missing between these two parts, I don't know. But I thought it was worth mentioning it, in case you have seen funny behaviour related to the scaling logic.
These are the simulation files:
k051960.zip
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