From da074db5960481849211103b1c86541777bbab33 Mon Sep 17 00:00:00 2001 From: liuzhao Date: Thu, 8 Jun 2023 15:44:02 +0800 Subject: [PATCH] add support for YT8512 phy --- arch/arm/src/imxrt/imxrt_enet.c | 67 ++++++++++++++++++++++++++++++++- drivers/net/Kconfig | 6 +++ include/nuttx/net/mii.h | 53 ++++++++++++++++++++++---- 3 files changed, 117 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index e86960c8d872f..d823fb6dc9c73 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -260,6 +260,15 @@ # define MMD1 1 # define MMD1_PMA_STATUS1 1 # define MMD1_PS1_RECEIVE_LINK_STATUS (1 << 2) +#elif defined(CONFIG_ETH0_PHY_YT8512) +# define BOARD_PHY_NAME "YT8512" +# define BOARD_PHYID1 MII_PHYID1_YT8512 +# define BOARD_PHYID2 MII_PHYID2_YT8512 +# define BOARD_PHY_STATUS MII_YT8512_PHYSTS +# define BOARD_PHY_ADDR (0) +# define BOARD_PHY_10BASET(s) (((s) & MII_YT8512_PHYSTS_SPEED) == 0) +# define BOARD_PHY_100BASET(s) (((s) & MII_YT8512_PHYSTS_SPEED) != 0) +# define BOARD_PHY_ISDUPLEX(s) (((s) & MII_YT8512_PHYSTS_DUPLEX) != 0) #else # error "Unrecognized or missing PHY selection" #endif @@ -1852,11 +1861,12 @@ static int imxrt_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int imxrt_phyintenable(struct imxrt_driver_s *priv) { -#if defined(CONFIG_ETH0_PHY_KSZ8051) || defined(CONFIG_ETH0_PHY_KSZ8061) || \ - defined(CONFIG_ETH0_PHY_KSZ8081) || defined(CONFIG_ETH0_PHY_DP83825I) uint16_t phyval; int ret; +#if defined(CONFIG_ETH0_PHY_KSZ8051) || defined(CONFIG_ETH0_PHY_KSZ8061) || \ + defined(CONFIG_ETH0_PHY_KSZ8081) || defined(CONFIG_ETH0_PHY_DP83825I) + /* Read the interrupt status register in order to clear any pending * interrupts */ @@ -1870,6 +1880,22 @@ static int imxrt_phyintenable(struct imxrt_driver_s *priv) (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN)); } + return ret; +#elif defined(CONFIG_ETH0_YT8512) + + /* Read the interrupt status register in order to clear any pending + * interrupts + */ + + ret = imxrt_readmii(priv, priv->phyaddr, MII_YT8512_ISR, &phyval); + if (ret == OK) + { + /* Enable link up/down interrupts */ + + ret = imxrt_writemii(priv, priv->phyaddr, MII_YT8512_IMR, + (MII_YT8512_IMR_LD_EN | MII_YT8512_IMR_LU_EN)); + } + return ret; #else # error Unrecognized PHY @@ -2404,6 +2430,43 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) MII_ADVERTISE_10BASETXHALF | MII_ADVERTISE_CSMA); +#elif defined (CONFIG_ETH0_PHY_YT8512) + + /* Reset PHY */ + + imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); + + /* Config LEDs */ + + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED0); + + imxrt_readmii(priv, phyaddr, MII_YT8512_DEBUG_DATA, &phydata); + + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED0); + + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_DATA, 0x331); + + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED1); + + imxrt_readmii(priv, phyaddr, MII_YT8512_DEBUG_DATA, &phydata); + + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED1); + + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_DATA, 0x30); + + /* Set negotiation */ + + imxrt_writemii(priv, phyaddr, MII_ADVERTISE, + MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_10BASETXFULL | + MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_CSMA); + #endif #if !defined(CONFIG_ETH0_PHY_TJA1103) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 3924d3913da1a..918e49a54f46f 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -468,6 +468,9 @@ config ETH0_PHY_LAN8742A config ETH0_PHY_DM9161 bool "Davicom DM9161 PHY" +config ETH0_PHY_YT8512 + bool "Motorcomm YT8512 PHY" + endchoice choice @@ -518,6 +521,9 @@ config ETH1_PHY_LAN8720 config ETH1_PHY_DM9161 bool "Davicom DM9161 PHY" +config ETH1_PHY_YT8512 + bool "Motorcomm YT8512 PHY" + endchoice config ARCH_PHY_100BASE_T1 diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h index 59504522c77c4..bae8a1dcd07e3 100644 --- a/include/nuttx/net/mii.h +++ b/include/nuttx/net/mii.h @@ -212,6 +212,20 @@ #define MII_LAN8740_IMR 0x1e /* Interrupt Mask Register */ #define MII_LAN8740_SCSR 0x1f /* PHY Special Control/Status Register */ +/* Motorcomm YT8512C/YT8512H Extended Registers */ + +#define MII_YT8512_PHYSFC 0x10 /* PHY Function conrtol Register */ +#define MII_YT8512_PHYSTS 0x11 /* PHY Status Register */ +#define MII_YT8512_IMR 0x12 /* Interrupt Mask Register */ +#define MII_YT8512_ISR 0x13 /* Interrupt Source Register */ +#define MII_YT8512_SADC 0x14 /* Speed auto downgrade control Register */ +#define MII_YT8512_REC 0x15 /* Rx Error Counter Register */ +#define MII_YT8512_DEBUG_ADDR_OFFSET 0x1E /* Debug Register's Address Offset Register */ +#define MII_YT8512_DEBUG_DATA 0x1F /* Debug Register's Data Register */ + +#define MII_YT8512_LED0 0x40c0 /* LED0 control */ +#define MII_YT8512_LED1 0x40c3 /* LED1 control */ + /* MII register bit settings ************************************************/ /* MII Control register bit definitions */ @@ -847,14 +861,39 @@ /* Atheros AR8031 MII ID1/2 register bits */ -#define MII_PHYID1_AR8031 0x004d /* ID1 value for AR8031 */ -#define MII_PHYID2_AR8031 0xd074 /* ID2 value for AR8031 */ +#define MII_PHYID1_AR8031 0x004d /* ID1 value for AR8031 */ +#define MII_PHYID2_AR8031 0xd074 /* ID2 value for AR8031 */ + +#define MII_AR8031_PSSR_SPEEDMASK (3 << 14) /* Bit 14-15: Speed */ +#define MII_AR8031_PSSR_10MBPS (0 << 14) +#define MII_AR8031_PSSR_100MBPS (1 << 14) +#define MII_AR8031_PSSR_1000MBPS (2 << 14) +#define MII_AR8031_PSSR_DUPLEX (1 << 13) /* Bit 13: Full duplex mode */ + +/* YT8512 register bit settings *********************************************/ + +/* YT8512 MII ID1/2 register bits */ + +#define MII_PHYID1_YT8512 0x0000 /* ID1 value for YT8512 */ +#define MII_PHYID2_YT8512 0x0128 /* ID2 value for YT8512 */ + +/* YT8512 Register 0x10: Specific function control register */ + +/* YT8512 Register 0x11: Specific status */ + +#define MII_YT8512_PHYSTS_SPEED (1 << 14) +#define MII_YT8512_PHYSTS_DUPLEX (1 << 13) +/* YT8512 Register 0x12: Interrupt mask */ +#define MII_YT8512_IMR_SPD_EN (1 << 14) +#define MII_YT8512_IMR_DUP_EN (1 << 13) +#define MII_YT8512_IMR_LD_EN (1 << 11) +#define MII_YT8512_IMR_LU_EN (1 << 10) + +/* YT8512 Register 0x13: Interrupt status */ + +/* YT8512 Register 0x14: Speed auto downgrade control */ -#define MII_AR8031_PSSR_SPEEDMASK (3 << 14) /* Bit 14-15: Speed */ -#define MII_AR8031_PSSR_10MBPS (0 << 14) -#define MII_AR8031_PSSR_100MBPS (1 << 14) -#define MII_AR8031_PSSR_1000MBPS (2 << 14) -#define MII_AR8031_PSSR_DUPLEX (1 << 13) /* Bit 13: Full duplex mode */ +/* YT8512 Register 0x15: Rx error counter */ /**************************************************************************** * Type Definitions