From b7d923e02bdf8359551a7f24a1e6bc64af3940e9 Mon Sep 17 00:00:00 2001
From: Flyinghead <raphael.jean@gmail.com>
Date: Fri, 20 Oct 2023 16:15:42 +0200
Subject: [PATCH] maple: clear mapleDmaOut on reset. Other reset issues

mapleDmaOut wasn't reset, causing crashes or freezes in subsequent runs
Issue #1253

reset YUV state, pvr tile clip, MMU sq_remap, sh4 sq_buffer and more
---
 core/hw/maple/maple_if.cpp  |  1 +
 core/hw/pvr/pvr.cpp         |  4 ++++
 core/hw/pvr/pvr_mem.cpp     | 12 ++++++++++++
 core/hw/pvr/pvr_mem.h       |  1 +
 core/hw/pvr/spg.cpp         |  3 +++
 core/hw/pvr/ta_vtx.cpp      |  1 +
 core/hw/sh4/modules/mmu.cpp |  1 +
 core/hw/sh4/modules/mmu.h   |  1 -
 core/hw/sh4/sh4_mmr.cpp     |  1 +
 9 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/core/hw/maple/maple_if.cpp b/core/hw/maple/maple_if.cpp
index 5ae102840..ab27768cd 100644
--- a/core/hw/maple/maple_if.cpp
+++ b/core/hw/maple/maple_if.cpp
@@ -335,6 +335,7 @@ void maple_Reset(bool hard)
 	SB_MSHTCL = 0;
 	SB_MDAPRO = 0x00007F00;
 	SB_MMSEL  = 1;
+	mapleDmaOut.clear();
 }
 
 void maple_Term()
diff --git a/core/hw/pvr/pvr.cpp b/core/hw/pvr/pvr.cpp
index 0c6141f90..79478de0b 100644
--- a/core/hw/pvr/pvr.cpp
+++ b/core/hw/pvr/pvr.cpp
@@ -47,7 +47,11 @@ void reset(bool hard)
 	tactx_Term();
 	elan::reset(hard);
 	if (hard)
+	{
 		ta_parse_reset();
+		YUV_reset();
+		taRenderPass = 0;
+	}
 }
 
 void init()
diff --git a/core/hw/pvr/pvr_mem.cpp b/core/hw/pvr/pvr_mem.cpp
index 708185961..aafc3c62e 100644
--- a/core/hw/pvr/pvr_mem.cpp
+++ b/core/hw/pvr/pvr_mem.cpp
@@ -196,6 +196,18 @@ void YUV_deserialize(Deserializer& deser)
 		YUV_index = 0;
 }
 
+void YUV_reset()
+{
+	memset(YUV_tempdata, 0, sizeof(YUV_tempdata));
+	YUV_dest = 0;
+	YUV_blockcount = 0;
+	YUV_x_curr = 0;
+	YUV_y_curr = 0;
+	YUV_x_size = 0;
+	YUV_y_size = 0;
+	YUV_index = 0;
+}
+
 //vram 32-64b
 
 //read
diff --git a/core/hw/pvr/pvr_mem.h b/core/hw/pvr/pvr_mem.h
index cf30c523b..531079402 100644
--- a/core/hw/pvr/pvr_mem.h
+++ b/core/hw/pvr/pvr_mem.h
@@ -16,6 +16,7 @@ void DYNACALL TAWriteSQ(u32 address, const SQBuffer *sqb);
 void YUV_init();
 void YUV_serialize(Serializer& ser);
 void YUV_deserialize(Deserializer& deser);
+void YUV_reset();
 
 // 32-bit vram path handlers
 template<typename T> T DYNACALL pvr_read32p(u32 addr);
diff --git a/core/hw/pvr/spg.cpp b/core/hw/pvr/spg.cpp
index 6f307e9f1..ff3b6f320 100755
--- a/core/hw/pvr/spg.cpp
+++ b/core/hw/pvr/spg.cpp
@@ -274,6 +274,9 @@ void spg_Reset(bool hard)
 	cpu_time_idx = 0;
 	cpu_cycles.fill(0);
 	real_times.fill(0.0);
+	maple_int_pending = false;
+	lightgun_line = 0xffff;
+	lightgun_hpos = 0;
 }
 
 void scheduleRenderDone(TA_context *cntx)
diff --git a/core/hw/pvr/ta_vtx.cpp b/core/hw/pvr/ta_vtx.cpp
index 2fb3328e5..b84c28397 100644
--- a/core/hw/pvr/ta_vtx.cpp
+++ b/core/hw/pvr/ta_vtx.cpp
@@ -125,6 +125,7 @@ class BaseTAParser
 
 	static void reset()
 	{
+		tileclip_val = 0;
 		memset(FaceBaseColor, 0xff, sizeof(FaceBaseColor));
 		memset(FaceOffsColor, 0xff, sizeof(FaceOffsColor));
 		memset(FaceBaseColor1, 0xff, sizeof(FaceBaseColor1));
diff --git a/core/hw/sh4/modules/mmu.cpp b/core/hw/sh4/modules/mmu.cpp
index 44e9165b0..5bb1f2fa7 100644
--- a/core/hw/sh4/modules/mmu.cpp
+++ b/core/hw/sh4/modules/mmu.cpp
@@ -492,6 +492,7 @@ void MMU_reset()
 	memset(ITLB, 0, sizeof(ITLB));
 	mmu_set_state();
 	mmu_flush_table();
+	memset(sq_remap, 0, sizeof(sq_remap));
 }
 
 void MMU_term()
diff --git a/core/hw/sh4/modules/mmu.h b/core/hw/sh4/modules/mmu.h
index d568a2032..6e6eea39a 100644
--- a/core/hw/sh4/modules/mmu.h
+++ b/core/hw/sh4/modules/mmu.h
@@ -37,7 +37,6 @@ struct TLB_Entry
 
 extern TLB_Entry UTLB[64];
 extern TLB_Entry ITLB[4];
-extern u32 sq_remap[64];
 extern bool mmuOn;
 
 constexpr u32 fast_reg_lut[8] =
diff --git a/core/hw/sh4/sh4_mmr.cpp b/core/hw/sh4/sh4_mmr.cpp
index c584b24b8..ff408873d 100644
--- a/core/hw/sh4/sh4_mmr.cpp
+++ b/core/hw/sh4/sh4_mmr.cpp
@@ -611,6 +611,7 @@ void sh4_mmr_reset(bool hard)
 	ubc.reset();
 
 	MMU_reset();
+	memset(p_sh4rcb->sq_buffer, 0, sizeof(p_sh4rcb->sq_buffer));
 }
 
 void sh4_mmr_term()