From c741527fa525e88fcddc5b7e1c02eb5c8023ac4f Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Fri, 29 Oct 2021 17:25:23 +0200 Subject: [PATCH] Removed demo programs because they are now hosted at a separate Git repository. Updated version information in preparation for the next release. --- ChangeLog | 6 + .../.gitignore | 5 - .../README.md | 30 - .../STM32F091RC_FLASH.ld | 168 - .../analogfloat.c | 125 - .../analogfloat.h | 43 - .../bin/.gitignore | 4 - demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.c | 131 - demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.h | 45 - .../Device/ST/STM32F0xx/Include/stm32f091xc.h | 11868 ---------------- .../Device/ST/STM32F0xx/Include/stm32f0xx.h | 242 - .../ST/STM32F0xx/Include/system_stm32f0xx.h | 121 - .../lib/CMSIS/Include/arm_common_tables.h | 136 - .../lib/CMSIS/Include/arm_const_structs.h | 79 - .../lib/CMSIS/Include/arm_math.h | 7154 ---------- .../lib/CMSIS/Include/cmsis_armcc.h | 734 - .../lib/CMSIS/Include/cmsis_armcc_V6.h | 1800 --- .../lib/CMSIS/Include/cmsis_gcc.h | 1373 -- .../lib/CMSIS/Include/core_cm0.h | 798 -- .../lib/CMSIS/Include/core_cm0plus.h | 914 -- .../lib/CMSIS/Include/core_cm3.h | 1763 --- .../lib/CMSIS/Include/core_cm4.h | 1937 --- .../lib/CMSIS/Include/core_cm7.h | 2512 ---- .../lib/CMSIS/Include/core_cmFunc.h | 87 - .../lib/CMSIS/Include/core_cmInstr.h | 87 - .../lib/CMSIS/Include/core_cmSimd.h | 96 - .../lib/CMSIS/Include/core_sc000.h | 926 -- .../lib/CMSIS/Include/core_sc300.h | 1745 --- .../lib/Newlib/putchar.c | 113 - .../lib/Newlib/putchar.h | 43 - .../lib/Newlib/syscalls.c | 213 - .../Inc/Legacy/stm32_hal_legacy.h | 3215 ----- .../STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h | 562 - .../Inc/stm32f0xx_hal_adc.h | 982 -- .../Inc/stm32f0xx_hal_adc_ex.h | 315 - .../Inc/stm32f0xx_hal_cortex.h | 149 - .../Inc/stm32f0xx_hal_def.h | 182 - .../Inc/stm32f0xx_hal_dma.h | 579 - .../Inc/stm32f0xx_hal_dma_ex.h | 827 -- .../Inc/stm32f0xx_hal_flash.h | 369 - .../Inc/stm32f0xx_hal_flash_ex.h | 464 - .../Inc/stm32f0xx_hal_gpio.h | 312 - .../Inc/stm32f0xx_hal_gpio_ex.h | 816 -- .../Inc/stm32f0xx_hal_i2c.h | 708 - .../Inc/stm32f0xx_hal_i2c_ex.h | 188 - .../Inc/stm32f0xx_hal_pwr.h | 205 - .../Inc/stm32f0xx_hal_pwr_ex.h | 475 - .../Inc/stm32f0xx_hal_rcc.h | 1702 --- .../Inc/stm32f0xx_hal_rcc_ex.h | 2101 --- .../Inc/stm32f0xx_hal_tim.h | 1830 --- .../Inc/stm32f0xx_hal_tim_ex.h | 325 - .../Inc/stm32f0xx_ll_bus.h | 861 -- .../Inc/stm32f0xx_ll_cortex.h | 336 - .../Inc/stm32f0xx_ll_crs.h | 799 -- .../Inc/stm32f0xx_ll_dma.h | 2224 --- .../Inc/stm32f0xx_ll_exti.h | 1032 -- .../Inc/stm32f0xx_ll_gpio.h | 955 -- .../Inc/stm32f0xx_ll_pwr.h | 568 - .../Inc/stm32f0xx_ll_rcc.h | 2257 --- .../Inc/stm32f0xx_ll_system.h | 1868 --- .../Inc/stm32f0xx_ll_usart.h | 3819 ----- .../Inc/stm32f0xx_ll_utils.h | 287 - .../STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c | 467 - .../Src/stm32f0xx_hal_adc.c | 2186 --- .../Src/stm32f0xx_hal_adc_ex.c | 204 - .../Src/stm32f0xx_hal_cortex.c | 357 - .../Src/stm32f0xx_hal_dma.c | 905 -- .../Src/stm32f0xx_hal_flash.c | 706 - .../Src/stm32f0xx_hal_flash_ex.c | 1000 -- .../Src/stm32f0xx_hal_gpio.c | 543 - .../Src/stm32f0xx_hal_i2c.c | 4868 ------- .../Src/stm32f0xx_hal_i2c_ex.c | 347 - .../Src/stm32f0xx_hal_pwr.c | 470 - .../Src/stm32f0xx_hal_pwr_ex.c | 290 - .../Src/stm32f0xx_hal_rcc.c | 1332 -- .../Src/stm32f0xx_hal_rcc_ex.c | 980 -- .../Src/stm32f0xx_hal_tim.c | 5495 ------- .../Src/stm32f0xx_hal_tim_ex.c | 2012 --- .../Src/stm32f0xx_ll_dma.c | 412 - .../Src/stm32f0xx_ll_exti.c | 238 - .../Src/stm32f0xx_ll_gpio.c | 279 - .../Src/stm32f0xx_ll_rcc.c | 599 - .../Src/stm32f0xx_ll_usart.c | 529 - .../Src/stm32f0xx_ll_utils.c | 620 - .../lib/stm32f0xx_hal_conf.h | 323 - .../lib/system_stm32f0xx.c | 333 - demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/main.c | 237 - .../ARM_CORTEXM_ST_Nucleo_F091RC_GCC/makefile | 174 - .../obj/.gitignore | 4 - .../startup_stm32f091xc.s | 303 - .../tbx_conf.h | 58 - .../ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.c | 84 - .../ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.h | 43 - source/microtbx.h | 2 +- 94 files changed, 7 insertions(+), 93003 deletions(-) delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/.gitignore delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/README.md delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/STM32F091RC_FLASH.ld delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.c delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.h delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/bin/.gitignore delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.c delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.h delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_common_tables.h delete mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_const_structs.h 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mode 100644 demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.h diff --git a/ChangeLog b/ChangeLog index fb3f5f6..706d7b7 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,4 +1,10 @@ ----------------------------------------------------------------------------------------- +2021-10-29 Frank Voorburg + +* Moved demos to a separate git repository. +* Moved tbx_conf.h to the "template" subdirectory. +* Public release of version 0.9.4. +----------------------------------------------------------------------------------------- 2020-04-09 Frank Voorburg * Added linked list module. diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/.gitignore b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/.gitignore deleted file mode 100644 index 904595f..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -/.settings/ -.cproject -.project -*.launch - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/README.md b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/README.md deleted file mode 100644 index 86e53e1..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/README.md +++ /dev/null @@ -1,30 +0,0 @@ -This demo program demonstrates how MicroTBX is integrated and used. It is targeted towards an -ST [Nucleo-F091RC](https://www.st.com/en/evaluation-tools/nucleo-f091rc.html) board and is configured for building with the [GNU ARM Embedded](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm) toolchain. - -# Prerequisites - -It is assumed that the ARM GCC Embedded toolchain in installed on the system. It can be downloaded from [here](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm). Additionally, the GNU tools *make* and *rm* should be installed and available on the path. Windows users can install the [GNU MCU Eclipse Windows Build Tools](https://gnu-mcu-eclipse.github.io/windows-build-tools/) for this. On a Debian/Ubuntu based system, the GNU tools can be installed with the following command: - -``` -sudo apt-get install build-essential -``` - -# Configuration - -The demo program is configured for building with a `makefile`. Before attempting to perform a build, update the location of the toolchain binaries (i.e. `arm-none-eabi-gcc`) in the `makefile`. It is set in variable `TOOL_PATH`: - -``` -TOOL_PATH=/opt/gcc-arm-none-eabi-5_4-2016q3/bin/ -``` - -If the toolchain binaries are available on the path, then the `TOOL_PATH` variable can be left empty. - -# Building - -Using the terminal, set the working directory to the directory that has the `makefile` in it. Next, type the following command to build the demo program: - -``` -make clean all -``` - -This creates the `microtbx_demo.elf` executable in the `./binary` directory. This file can be programmed onto the ST Nucleo-F091RC board, using the on-board ST-Link debugger interface and with the help of the [STM32CubeProgrammer](https://www.st.com/en/development-tools/stm32cubeprog.html) software program. diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/STM32F091RC_FLASH.ld b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/STM32F091RC_FLASH.ld deleted file mode 100644 index 1e4f22f..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/STM32F091RC_FLASH.ld +++ /dev/null @@ -1,168 +0,0 @@ -/* -***************************************************************************** -** - -** File : stm32_flash.ld -** -** Abstract : Linker script for STM32F091RC Device with -** 256KByte FLASH, 32KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. This file may only be built (assembled or compiled and linked) -** using the Atollic TrueSTUDIO(R) product. The use of this file together -** with other tools than Atollic TrueSTUDIO(R) is not permitted. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20008000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.c deleted file mode 100644 index db88b37..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.c +++ /dev/null @@ -1,125 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/analogfloat.c -* \brief Floating analog input driver source file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include /* for standard integer types */ -#include "analogfloat.h" /* floating analog input driver */ -#include "stm32f0xx.h" /* STM32 CPU and HAL header */ - - -/**************************************************************************************** -* Local data declarations -****************************************************************************************/ -/** \brief Handle for accessing the ADC peripheral with the HAL drivers. */ -static ADC_HandleTypeDef adcHandle; - - -/************************************************************************************//** -** \brief Initializes the driver for reading a floating analog input. -** \return none. -** -****************************************************************************************/ -void AnalogFloatInit(void) -{ - GPIO_InitTypeDef GPIO_InitStruct; - ADC_ChannelConfTypeDef ADC_ChannelConfStruct; - - - /* GPIO port and ADC peripheral clock enable. */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_ADC1_CLK_ENABLE(); - - /* Configure PA0 (AN0 on the board) as an analog input. */ - GPIO_InitStruct.Pin = GPIO_PIN_0; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Configure the global features of the ADC such as the clock, resolution, data - * alignment and number of conversions. - */ - adcHandle.Instance = ADC1; - adcHandle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; - adcHandle.Init.Resolution = ADC_RESOLUTION_12B; - adcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - adcHandle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; - adcHandle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - adcHandle.Init.LowPowerAutoWait = DISABLE; - adcHandle.Init.LowPowerAutoPowerOff = DISABLE; - adcHandle.Init.ContinuousConvMode = DISABLE; - adcHandle.Init.DiscontinuousConvMode = DISABLE; - adcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; - adcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - adcHandle.Init.DMAContinuousRequests = DISABLE; - adcHandle.Init.Overrun = ADC_OVR_DATA_PRESERVED; - (void)HAL_ADC_Init(&adcHandle); - - /* Configure the ADC regular channel (PA0 = ADC channel 0) to be converted. */ - ADC_ChannelConfStruct.Channel = ADC_CHANNEL_0; - ADC_ChannelConfStruct.Rank = ADC_RANK_CHANNEL_NUMBER; - ADC_ChannelConfStruct.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; - (void)HAL_ADC_ConfigChannel(&adcHandle, &ADC_ChannelConfStruct); -} /*** end of AnalogFloatInit ***/ - - -/************************************************************************************//** -** \brief Performs an analog to digital conversion of the floating analog input pin. -** \return The result of the analog to digital conversion. -** -****************************************************************************************/ -uint16_t AnalogFloatGet(void) -{ - uint16_t result = 0; - - /* Start a new analog to digital conversion on the configured channel, which is this - * case is pin PA0 which is not connected to anything. Such a floating channel will - * pick up noise, so the conversion results always vary slightly. - */ - if (HAL_ADC_Start(&adcHandle) == HAL_OK) - { - /* Wait for the analog to digital conversion to complete. */ - if (HAL_ADC_PollForConversion(&adcHandle, 10) == HAL_OK) - { - /* Store the conversion results. */ - result = HAL_ADC_GetValue(&adcHandle); - } - } - - /* Give the result back to the caller. */ - return result; -} /*** end of AnalogFloatGet ***/ - - -/*********************************** end of analogfloat.c ******************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.h deleted file mode 100644 index 6f59db8..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/analogfloat.h +++ /dev/null @@ -1,43 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/analogfloat.h -* \brief Floating analog input driver header file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ -#ifndef ANALOGFLOAT_H -#define ANALOGFLOAT_H - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -void AnalogFloatInit(void); -uint16_t AnalogFloatGet(void); - -#endif /* ANALOGFLOAT_H */ -/*********************************** end of analogfloat.h ******************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/bin/.gitignore b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/bin/.gitignore deleted file mode 100644 index 5e7d273..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/bin/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -# Ignore everything in this directory -* -# Except this file -!.gitignore diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.c deleted file mode 100644 index 38521a6..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.c +++ /dev/null @@ -1,131 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/led.c -* \brief LED driver source file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "microtbx.h" /* MicroTBX library */ -#include "led.h" /* LED driver */ -#include "stm32f0xx.h" /* STM32 CPU and HAL header */ - - -/**************************************************************************************** -* Local data declarations -****************************************************************************************/ -/** \brief Current state of the LED. TBX_TRUE for ON, TBX_FALSE for off. */ -static uint8_t ledState; - - -/************************************************************************************//** -** \brief Initializes the LED driver. -** \return none. -** -****************************************************************************************/ -void LedInit(void) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /* Initialize locals. */ - ledState = TBX_FALSE; - - /* GPIO ports clock enable. */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - - /* Configure the LED GPIO pin. */ - GPIO_InitStruct.Pin = GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - /* turn the LED off */ - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); -} /*** end of LedInit ***/ - - -/************************************************************************************//** -** \brief Controls the state of the LED. -** \param on Boolean true to turn the LED on, boolean false for off. -** \return none. -** -****************************************************************************************/ -void LedSet(uint8_t on) -{ - if (on == TBX_TRUE) - { - /* turn the LED on */ - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET); - TbxCriticalSectionEnter(); - ledState = TBX_TRUE; - TbxCriticalSectionExit(); - } - else - { - /* turn the LED off */ - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); - TbxCriticalSectionEnter(); - ledState = TBX_FALSE; - TbxCriticalSectionExit(); - } -} /*** end of LedSet ***/ - - -/************************************************************************************//** -** \brief Obtains the current state of the LED. -** \return Boolean true if the LED is on, boolean false if off. -** -****************************************************************************************/ -uint8_t LedGet(void) -{ - return ledState; -} /*** end of LedGet ***/ - - -/************************************************************************************//** -** \brief Toggles the current state of the LED. -** \return none. -** -****************************************************************************************/ -void LedToggle(void) -{ - uint8_t newState = TBX_TRUE; - - /* Toggle the LED state. */ - if (LedGet() == TBX_TRUE) - { - newState = TBX_FALSE; - } - LedSet(newState); -} /*** end of LedToggle ***/ - - -/*********************************** end of led.c **************************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.h deleted file mode 100644 index 8805df7..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/led.h +++ /dev/null @@ -1,45 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/led.h -* \brief LED driver header file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ -#ifndef LED_H -#define LED_H - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -void LedInit(void); -void LedSet(uint8_t on); -uint8_t LedGet(void); -void LedToggle(void); - -#endif /* LED_H */ -/*********************************** end of led.h **************************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h deleted file mode 100644 index 4f2ae78..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h +++ /dev/null @@ -1,11868 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f091xc.h - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F0xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f091xc - * @{ - */ - -#ifndef __STM32F091xC_H -#define __STM32F091xC_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0 Processor and Core Peripherals - */ -#define __CM0_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ -#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F0xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** STM32F0 specific Interrupt Numbers ******************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */ - RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ - FLASH_IRQn = 3, /*!< FLASH global Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ - TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ - DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */ - DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupt */ - ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ - TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */ - TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ - TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ - TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ - TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ - TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ - USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ - USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupt */ - CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ -#include "system_stm32f0xx.h" /* STM32F0xx System Header */ -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -}CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -}CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -}CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -}CAN_TypeDef; - -/** - * @brief HDMI-CEC - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ - __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ - __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ - __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ - __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ - __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ -}CEC_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/* Legacy defines */ -typedef struct -{ - __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */ -}COMP1_2_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -}CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ - uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */ - __IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! exti[31] Interrupt */ -#define SYSCFG_ITLINE1_SR_VDDIO2_Pos (1U) -#define SYSCFG_ITLINE1_SR_VDDIO2_Msk (0x1U << SYSCFG_ITLINE1_SR_VDDIO2_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE1_SR_VDDIO2 SYSCFG_ITLINE1_SR_VDDIO2_Msk /*!< VDDIO2 -> exti[16] Interrupt */ -#define SYSCFG_ITLINE2_SR_RTC_ALRA_Pos (0U) -#define SYSCFG_ITLINE2_SR_RTC_ALRA_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_ALRA_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE2_SR_RTC_ALRA SYSCFG_ITLINE2_SR_RTC_ALRA_Msk /*!< RTC Alarm -> exti[17] interrupt .... */ -#define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos (1U) -#define SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_TSTAMP_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE2_SR_RTC_TSTAMP SYSCFG_ITLINE2_SR_RTC_TSTAMP_Msk /*!< RTC Time Stamp -> exti[19] interrupt */ -#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (2U) -#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1U << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000004 */ -#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC WAKEUP -> exti[20] Interrupt */ -#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (0U) -#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1U << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< Flash ITF Interrupt */ -#define SYSCFG_ITLINE4_SR_CRS_Pos (0U) -#define SYSCFG_ITLINE4_SR_CRS_Msk (0x1U << SYSCFG_ITLINE4_SR_CRS_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE4_SR_CRS SYSCFG_ITLINE4_SR_CRS_Msk /*!< CRS interrupt */ -#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (1U) -#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1U << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< CLK CTRL interrupt */ -#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) -#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1U << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ -#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) -#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1U << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ -#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) -#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1U << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ -#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) -#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1U << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ -#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) -#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) -#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) -#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ -#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) -#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ -#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) -#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ -#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) -#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ -#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) -#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ -#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) -#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ -#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) -#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ -#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) -#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ -#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) -#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ -#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) -#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1U << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ -#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 to 4 */ -#define SYSCFG_ITLINE8_SR_TSC_EOA_Pos (0U) -#define SYSCFG_ITLINE8_SR_TSC_EOA_Msk (0x1U << SYSCFG_ITLINE8_SR_TSC_EOA_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE8_SR_TSC_EOA SYSCFG_ITLINE8_SR_TSC_EOA_Msk /*!< Touch control EOA Interrupt */ -#define SYSCFG_ITLINE8_SR_TSC_MCE_Pos (1U) -#define SYSCFG_ITLINE8_SR_TSC_MCE_Msk (0x1U << SYSCFG_ITLINE8_SR_TSC_MCE_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE8_SR_TSC_MCE SYSCFG_ITLINE8_SR_TSC_MCE_Msk /*!< Touch control MCE Interrupt */ -#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) -#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1U << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) -#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) -#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA2_CH1_Pos (2U) -#define SYSCFG_ITLINE10_SR_DMA2_CH1_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA2_CH1_Pos) /*!< 0x00000004 */ -#define SYSCFG_ITLINE10_SR_DMA2_CH1 SYSCFG_ITLINE10_SR_DMA2_CH1_Msk /*!< DMA2 Channel 1 Interrupt */ -#define SYSCFG_ITLINE10_SR_DMA2_CH2_Pos (3U) -#define SYSCFG_ITLINE10_SR_DMA2_CH2_Msk (0x1U << SYSCFG_ITLINE10_SR_DMA2_CH2_Pos) /*!< 0x00000008 */ -#define SYSCFG_ITLINE10_SR_DMA2_CH2 SYSCFG_ITLINE10_SR_DMA2_CH2_Msk /*!< DMA2 Channel 2 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (0U) -#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (1U) -#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (2U) -#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000004 */ -#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (3U) -#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000008 */ -#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA2_CH3_Pos (4U) -#define SYSCFG_ITLINE11_SR_DMA2_CH3_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH3_Pos) /*!< 0x00000010 */ -#define SYSCFG_ITLINE11_SR_DMA2_CH3 SYSCFG_ITLINE11_SR_DMA2_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA2_CH4_Pos (5U) -#define SYSCFG_ITLINE11_SR_DMA2_CH4_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH4_Pos) /*!< 0x00000020 */ -#define SYSCFG_ITLINE11_SR_DMA2_CH4 SYSCFG_ITLINE11_SR_DMA2_CH4_Msk /*!< DMA2 Channel 4 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMA2_CH5_Pos (6U) -#define SYSCFG_ITLINE11_SR_DMA2_CH5_Msk (0x1U << SYSCFG_ITLINE11_SR_DMA2_CH5_Pos) /*!< 0x00000040 */ -#define SYSCFG_ITLINE11_SR_DMA2_CH5 SYSCFG_ITLINE11_SR_DMA2_CH5_Msk /*!< DMA2 Channel 5 Interrupt */ -#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) -#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1U << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ -#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U) -#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1U << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[21] */ -#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) -#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1U << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ -#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[22] */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (0U) -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (1U) -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (2U) -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000004 */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (3U) -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1U << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000008 */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) -#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1U << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) -#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1U << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) -#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1U << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC_Pos (0U) -#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1U << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (1U) -#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1U << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) -#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1U << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) -#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1U << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ -#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) -#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1U << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) -#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1U << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) -#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1U << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) -#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1U << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ -#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) -#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1U << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) -#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1U << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) -#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1U << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) -#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1U << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ -#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) -#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1U << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ -#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) -#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt -> exti[28] */ -#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) -#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART5_GLB_Pos (2U) -#define SYSCFG_ITLINE29_SR_USART5_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART5_GLB_Pos) /*!< 0x00000004 */ -#define SYSCFG_ITLINE29_SR_USART5_GLB SYSCFG_ITLINE29_SR_USART5_GLB_Msk /*!< USART5 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART6_GLB_Pos (3U) -#define SYSCFG_ITLINE29_SR_USART6_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART6_GLB_Pos) /*!< 0x00000008 */ -#define SYSCFG_ITLINE29_SR_USART6_GLB SYSCFG_ITLINE29_SR_USART6_GLB_Msk /*!< USART6 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART7_GLB_Pos (4U) -#define SYSCFG_ITLINE29_SR_USART7_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART7_GLB_Pos) /*!< 0x00000010 */ -#define SYSCFG_ITLINE29_SR_USART7_GLB SYSCFG_ITLINE29_SR_USART7_GLB_Msk /*!< USART7 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_USART8_GLB_Pos (5U) -#define SYSCFG_ITLINE29_SR_USART8_GLB_Msk (0x1U << SYSCFG_ITLINE29_SR_USART8_GLB_Pos) /*!< 0x00000020 */ -#define SYSCFG_ITLINE29_SR_USART8_GLB SYSCFG_ITLINE29_SR_USART8_GLB_Msk /*!< USART8 GLB Interrupt */ -#define SYSCFG_ITLINE30_SR_CAN_Pos (0U) -#define SYSCFG_ITLINE30_SR_CAN_Msk (0x1U << SYSCFG_ITLINE30_SR_CAN_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE30_SR_CAN SYSCFG_ITLINE30_SR_CAN_Msk /*!< CAN Interrupt */ -#define SYSCFG_ITLINE30_SR_CEC_Pos (1U) -#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1U << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000002 */ -#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt */ - -/*****************************************************************************/ -/* */ -/* Timers (TIM) */ -/* */ -/*****************************************************************************/ -/******************* Bit definition for TIM_CR1 register *******************/ -#define TIM_CR1_CEN_Pos (0U) -#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ -#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx - * @{ - */ - -#ifndef __STM32F0xx_H -#define __STM32F0xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32F0) -#define STM32F0 -#endif /* STM32F0 */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ - !defined (STM32F031x6) && !defined (STM32F038xx) && \ - !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ - !defined (STM32F051x8) && !defined (STM32F058xx) && \ - !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ - !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) - /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ - /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ - /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */ - /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ - /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ - /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ - /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ - /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ - /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ - /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ - /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ - /* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */ - /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V2.3.3 - */ -#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ - |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ - |(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\ - |(__STM32F0_DEVICE_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32F030x6) - #include "stm32f030x6.h" -#elif defined(STM32F030x8) - #include "stm32f030x8.h" -#elif defined(STM32F031x6) - #include "stm32f031x6.h" -#elif defined(STM32F038xx) - #include "stm32f038xx.h" -#elif defined(STM32F042x6) - #include "stm32f042x6.h" -#elif defined(STM32F048xx) - #include "stm32f048xx.h" -#elif defined(STM32F051x8) - #include "stm32f051x8.h" -#elif defined(STM32F058xx) - #include "stm32f058xx.h" -#elif defined(STM32F070x6) - #include "stm32f070x6.h" -#elif defined(STM32F070xB) - #include "stm32f070xb.h" -#elif defined(STM32F071xB) - #include "stm32f071xb.h" -#elif defined(STM32F072xB) - #include "stm32f072xb.h" -#elif defined(STM32F078xx) - #include "stm32f078xx.h" -#elif defined(STM32F091xC) - #include "stm32f091xc.h" -#elif defined(STM32F098xx) - #include "stm32f098xx.h" -#elif defined(STM32F030xC) - #include "stm32f030xc.h" -#else - #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32f0xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32F0xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h deleted file mode 100644 index 4daf83e..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f0xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F0XX_H -#define __SYSTEM_STM32F0XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F0xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F0xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 3) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) by calling HAL API function HAL_RCC_ClockConfig() - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F0XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_common_tables.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index d5d7241..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_const_structs.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 54595f5..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_math.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_math.h deleted file mode 100644 index 580cbbd..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_armcc.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index f2bb66a..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_armcc_V6.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_armcc_V6.h deleted file mode 100644 index d714e9b..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_gcc.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index d868f2e..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm0.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm0.h deleted file mode 100644 index fdee521..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm0plus.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 7614450..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm3.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm3.h deleted file mode 100644 index 34ed84c..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1763 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm4.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm4.h deleted file mode 100644 index 01cb73b..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1937 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm7.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm7.h deleted file mode 100644 index 20963c1..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmFunc.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index ca319a5..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmInstr.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index a0a5064..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmSimd.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index 4d76bf9..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_sc000.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_sc000.h deleted file mode 100644 index ea16bf3..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,926 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_sc300.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_sc300.h deleted file mode 100644 index 820cef4..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1745 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/putchar.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/putchar.c deleted file mode 100644 index 162e243..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/putchar.c +++ /dev/null @@ -1,113 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/lib/Newlib/putchar.c -* \brief Transmit character source file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include /* for standard integer types */ -#include "putchar.h" /* putchar module */ -#include "stm32f0xx.h" /* STM32 CPU and HAL header */ -#include "stm32f0xx_ll_usart.h" /* STM32 LL USART header */ - - -/************************************************************************************//** -** \brief Initializes the communication interface for sending the character. -** \return none. -** -****************************************************************************************/ -void PutCharInit(void) -{ - GPIO_InitTypeDef GPIO_InitStruct; - LL_USART_InitTypeDef USART_InitStruct; - - /* GPIO ports clock enable. */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - /* UART Peripheral clock enable. */ - __HAL_RCC_USART2_CLK_ENABLE(); - - /* UART TX and RX GPIO pin configuration. */ - GPIO_InitStruct.Pin = GPIO_PIN_2 | GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF1_USART2; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Configure UART peripheral */ - USART_InitStruct.BaudRate = 57600; - USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; - USART_InitStruct.StopBits = LL_USART_STOPBITS_1; - USART_InitStruct.Parity = LL_USART_PARITY_NONE; - USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; - USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; - USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; - /* Initialize the UART peripheral */ - LL_USART_Init(USART2, &USART_InitStruct); - LL_USART_Enable(USART2); -} /*** end of PutCharInit ***/ - - -/************************************************************************************//** -** \brief Transmits the character on the communication interface. -** \param ch The value of the character to transmit. -** \return The value of the transmitted character if successful, -1 otherwise. -** -****************************************************************************************/ -int PutCharTransmit(int ch) -{ - int result = ch; - uint8_t c; - - /* Convert to 8-bit character. */ - c = ch & 0x00FF; - - /* Write byte to transmit holding register */ - LL_USART_TransmitData8(USART2, c); - /* Wait for tx holding register to be empty */ - while (LL_USART_IsActiveFlag_TXE(USART2) == 0) - { - ; - } - - /* Automatically send carriage return with each newline. */ - if (ch == '\n') - { - (void)PutCharTransmit('\r'); - } - - /* Give the result back to the caller. */ - return result; -} /*** end of PutCharTransmit ***/ - - -/*********************************** end of putchar.c **********************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/putchar.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/putchar.h deleted file mode 100644 index ca93779..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/putchar.h +++ /dev/null @@ -1,43 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/lib/Newlib/putchar.h -* \brief Transmit character header file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ -#ifndef PUTCHAR_H -#define PUTCHAR_H - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -void PutCharInit(void); -int PutCharTransmit(int ch); - -#endif /* PUTCHAR_H */ -/*********************************** end of putchar.h **********************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/syscalls.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/syscalls.c deleted file mode 100644 index 8024c64..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/Newlib/syscalls.c +++ /dev/null @@ -1,213 +0,0 @@ -/* -****************************************************************************** -File: syscalls.c -Info: Generated by Atollic TrueSTUDIO(R) 9.0.1 2019-06-16 - -The MIT License (MIT) -Copyright (c) 2018 STMicroelectronics - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - -****************************************************************************** -*/ - -/* Includes */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "putchar.h" - - -/* Variables */ -#undef errno -extern int32_t errno; - -uint8_t *__env[1] = { 0 }; -uint8_t **environ = __env; - - -/* Functions */ -void initialise_monitor_handles() -{ -} - -int _getpid(void) -{ - errno = ENOSYS; - return -1; -} - -int _gettimeofday(struct timeval *ptimeval, void *ptimezone) -{ - errno = ENOSYS; - return -1; -} - -int _kill(int32_t pid, int32_t sig) -{ - errno = ENOSYS; - return -1; -} - -void _exit(int32_t status) -{ - while (1) {} /* Make sure we hang here */ -} - -int _write(int32_t file, uint8_t *ptr, int32_t len) -{ - static uint8_t initialized = 0; - int result = len; - int idx; - - /* make sure the communication interface for transmitting characters is initialized. */ - if (!initialized) - { - PutCharInit(); - initialized = 1; - } - - /* transmit the characters one at a time. */ - for (idx = 0; idx < len; idx++) - { - if (!PutCharTransmit(*ptr)) - { - errno = EIO; - break; - } - ptr++; - } - - /* give the result back to the caller. */ - return result; -} - -void * _sbrk(int32_t incr) -{ - extern char end; /* Set by linker. */ - static char * heap_end; - char * prev_heap_end; - - if (heap_end == 0) { - heap_end = & end; - } - - prev_heap_end = heap_end; - heap_end += incr; - - return (void *) prev_heap_end; -} - -int _close(int32_t file) -{ - errno = ENOSYS; - return -1; -} - - -int _fstat(int32_t file, struct stat *st) -{ - errno = ENOSYS; - return -1; -} - -int _isatty(int32_t file) -{ - errno = ENOSYS; - return 0; -} - -int _lseek(int32_t file, int32_t ptr, int32_t dir) -{ - errno = ENOSYS; - return -1; -} - -int _read(int32_t file, uint8_t *ptr, int32_t len) -{ - errno = ENOSYS; - return -1; -} - -int _readlink(const char *path, char *buf, size_t bufsize) -{ - errno = ENOSYS; - return -1; -} - -int _open(const uint8_t *path, int32_t flags, int32_t mode) -{ - errno = ENOSYS; - return -1; -} - -int _wait(int32_t *status) -{ - errno = ENOSYS; - return -1; -} - -int _unlink(const uint8_t *name) -{ - errno = ENOSYS; - return -1; -} - -int _times(struct tms *buf) -{ - errno = ENOSYS; - return -1; -} - -int _stat(const uint8_t *file, struct stat *st) -{ - errno = ENOSYS; - return -1; -} - -int _symlink(const char *path1, const char *path2) -{ - errno = ENOSYS; - return -1; -} - -int _link(const uint8_t *old, const uint8_t *new) -{ - errno = ENOSYS; - return -1; -} - -int _fork(void) -{ - errno = ENOSYS; - return -1; -} - -int _execve(const uint8_t *name, uint8_t * const *argv, uint8_t * const *env) -{ - errno = ENOSYS; - return -1; -} - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h deleted file mode 100644 index 32a59ff..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,3215 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @version V1.8.1 - * @date 14-April-2017 - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000U) -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) - #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE - #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE - #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET - #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET - #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE - #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE - - #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 - #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - - #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX - #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 - #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 - #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - - #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT - #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING - #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING - #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - - -#endif /* STM32H7 */ - - -/** - * @} - */ - - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) - -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4xx || STM32F7*/ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32WB) -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h deleted file mode 100644 index 8bf0e6c..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h +++ /dev/null @@ -1,562 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_H -#define __STM32F0xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_conf.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup HAL_Private_Macros - * @{ - */ -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F070xB) || defined(STM32F030x6) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#else -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#endif -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ -#if defined(STM32F091xC) || defined(STM32F098xx) -#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ - ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ - ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) -#endif /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -/** @defgroup HAL_Pin_remapping HAL Pin remapping - * @{ - */ -#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). - 0: No remap (pin pair PA9/10 mapped on the pins) - 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ - -/** - * @} - */ -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ - -#if defined(STM32F091xC) || defined(STM32F098xx) -/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection - * @note Applicable on STM32F09x - * @{ - */ -#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ -#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ -#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ - -/** - * @} - */ -#endif /* STM32F091xC || STM32F098xx */ - - -/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO - * @{ - */ - -/** @brief Fast-mode Plus driving capability on a specific GPIO - */ -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F070xB) || defined(STM32F030x6) -#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */ -#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */ -#endif -#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */ -#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */ -#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */ -#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */ - -/** - * @} - */ - - -#if defined(STM32F091xC) || defined (STM32F098xx) -/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper - * @brief ISR Wrapper - * @note applicable on STM32F09x - * @{ - */ -#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */ -#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */ - -#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */ -#if defined(STM32F091xC) -#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */ -#endif -#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */ -#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */ -#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */ -#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */ -#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */ -#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */ -#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */ -#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */ -#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */ -#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */ -#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */ -#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */ -#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */ -#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */ -#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */ -#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */ -#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */ -#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */ -#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */ -#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */ -#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */ -#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */ -#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */ -#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */ -#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */ -#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */ -#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */ -#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */ -#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */ -#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */ -#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */ -#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */ -#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */ -#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */ -#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */ -#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */ -#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */ -#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */ -#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */ -#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */ -#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */ -#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */ -#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */ -#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */ -#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */ -#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */ -#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */ -#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */ -#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */ -#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */ -#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */ -#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */ -#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */ -#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */ -#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */ -#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */ -#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */ -#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */ -#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ -#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ -#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */ -#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */ -#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */ -#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */ -#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */ -#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */ -#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */ -#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */ -/** - * @} - */ -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals - * @brief Freeze/Unfreeze Peripherals in Debug mode - * @{ - */ - -#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) -#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) -#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ - -#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ - -#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) -#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) -#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) -#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) -#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ - -#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) -#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) -#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ - -/** - * @} - */ - -/** @defgroup Memory_Mapping_Selection Memory Mapping Selection - * @{ - */ -#if defined(SYSCFG_CFGR1_MEM_MODE) -/** @brief Main Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) -#endif /* SYSCFG_CFGR1_MEM_MODE */ - -#if defined(SYSCFG_CFGR1_MEM_MODE_0) -/** @brief System Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ - SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ - }while(0) -#endif /* SYSCFG_CFGR1_MEM_MODE_0 */ - -#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) -/** @brief Embedded SRAM mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ - SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ - }while(0) -#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ -/** - * @} - */ - - -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -/** @defgroup HAL_Pin_remap HAL Pin remap - * @brief Pin remapping enable/disable macros - * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping - * @{ - */ -#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ - SYSCFG->CFGR1 |= (__PIN_REMAP__); \ - }while(0) -#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ - SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ - -/** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. - * That you can find above these macros. - */ -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) -#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) -/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable - * @{ - */ -/** @brief SYSCFG Break Lockup lock - * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ - -#if defined(SYSCFG_CFGR2_PVD_LOCK) -/** @defgroup PVD_Lock_Enable PVD Lock - * @{ - */ -/** @brief SYSCFG Break PVD lock - * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_PVD_LOCK */ - -#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) -/** @defgroup SRAM_Parity_Lock SRAM Parity Lock - * @{ - */ -/** @brief SYSCFG Break SRAM PARITY lock - * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ - -#if defined(SYSCFG_CFGR2_SRAM_PEF) -/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM - * @brief Parity check on RAM disable macro - * @note Disabling the parity check on RAM locks the configuration bit. - * To re-enable the parity check on RAM perform a system reset. - * @{ - */ -#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) -/** - * @} - */ -#endif /* SYSCFG_CFGR2_SRAM_PEF */ - - -#if defined(STM32F091xC) || defined (STM32F098xx) -/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check - * @brief ISR wrapper check - * @note This feature is applicable on STM32F09x - * @note Allow to determine interrupt source per line. - * @{ - */ -#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) -/** - * @} - */ -#endif /* (STM32F091xC) || defined (STM32F098xx)*/ - -#if defined(STM32F091xC) || defined (STM32F098xx) -/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection - * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register - * @note This feature is applicable on STM32F09x - * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL - * @{ - */ -#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ - SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ - SYSCFG->CFGR1 |= (__SOURCE__); \ - }while(0) - -#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) -/** - * @} - */ -#endif /* (STM32F091xC) || defined (STM32F098xx)*/ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HAL_Exported_Functions - * @{ - */ - -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h deleted file mode 100644 index 79c5267..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h +++ /dev/null @@ -1,982 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_adc.h - * @author MCD Application Team - * @brief Header file containing functions prototypes of ADC HAL library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_ADC_H -#define __STM32F0xx_HAL_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Types ADC Exported Types - * @{ - */ - -/** - * @brief Structure definition of ADC initialization and regular group - * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') - * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. - This parameter can be a value of @ref ADC_ClockPrescaler - Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. - Note: This parameter can be modified only if the ADC is disabled */ - uint32_t Resolution; /*!< Configures the ADC resolution. - This parameter can be a value of @ref ADC_Resolution */ - uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_Data_align */ - uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. - This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): - If only 1 channel is set: Conversion is performed in single mode. - If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). - This parameter can be a value of @ref ADC_Scan_mode */ - uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. - This parameter can be a value of @ref ADC_EOCSelection. */ - uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous - conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). - This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. - This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed - and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ - uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). - This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). - This parameter can be set to ENABLE or DISABLE. - Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ - uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, - after the selected trigger occurred (software start or external trigger). - This parameter can be set to ENABLE or DISABLE. */ - uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE - Note: Number of discontinuous ranks increment is fixed to one-by-one. */ - uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. - If set to ADC_SOFTWARE_START, external triggers are disabled. - This parameter can be a value of @ref ADC_External_trigger_source_Regular */ - uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. - If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. - This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ - uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) - or in Continuous mode (DMA transfer unlimited, whatever number of conversions). - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten - This parameter has an effect on regular group only, including in DMA mode. - This parameter can be a value of @ref ADC_Overrun */ - uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. - This parameter can be a value of @ref ADC_sampling_times - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ -}ADC_InitTypeDef; - -/** - * @brief Structure definition of ADC channel for regular group - * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled or enabled without conversion on going on regular group. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_channels - Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ - uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. - On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).. - Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. - This parameter can be a value of @ref ADC_rank */ - uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times - Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. - Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure. - If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ -}ADC_ChannelConfTypeDef; - -/** - * @brief Structure definition of ADC analog watchdog - * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. - * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. - */ -typedef struct -{ - uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. - This parameter can be a value of @ref ADC_analog_watchdog_mode. */ - uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. - This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. - This parameter can be a value of @ref ADC_channels. */ - uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. - This parameter can be set to ENABLE or DISABLE */ - uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ - uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ -}ADC_AnalogWDGConfTypeDef; - -/** - * @brief HAL ADC state machine: ADC states definition (bitfields) - * @note ADC state machine is managed by bitfields, state must be compared - * with bit by bit. - * For example: - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " - */ -/* States of ADC global scope */ -#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ - -/* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ - -/* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ - -/* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ - -/* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ - -/* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ - - -/** - * @brief ADC handle Structure definition - */ -typedef struct -{ - ADC_TypeDef *Instance; /*!< Register base address */ - - ADC_InitTypeDef Init; /*!< ADC required parameters */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - - HAL_LockTypeDef Lock; /*!< ADC locking object */ - - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - - __IO uint32_t ErrorCode; /*!< ADC Error code */ -}ADC_HandleTypeDef; -/** - * @} - */ - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_Error_Code ADC Error Code - * @{ - */ -#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, - enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ - -/** - * @} - */ - -/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler - * @{ - */ -#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ - -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ - -/** - * @} - */ - -/** @defgroup ADC_Resolution ADC Resolution - * @{ - */ -#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ -#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ -#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ -#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ -/** - * @} - */ - -/** @defgroup ADC_Data_align ADC Data_align - * @{ - */ -#define ADC_DATAALIGN_RIGHT (0x00000000U) -#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) -/** - * @} - */ - -/** @defgroup ADC_Scan_mode ADC Scan mode - * @{ - */ -/* Note: Scan mode values must be compatible with other STM32 devices having */ -/* a configurable sequencer. */ -/* Scan direction setting values are defined by taking in account */ -/* already defined values for other STM32 devices: */ -/* ADC_SCAN_DISABLE (0x00000000U) */ -/* ADC_SCAN_ENABLE (0x00000001U) */ -/* Scan direction forward is considered as default setting equivalent */ -/* to scan enable. */ -/* Scan direction backward is considered as additional setting. */ -/* In case of migration from another STM32 device, the user will be */ -/* warned of change of setting choices with assert check. */ -#define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ -#define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ - -#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ - -/** - * @} - */ - -/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular - * @{ - */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) -#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) -#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) -/** - * @} - */ - -/** @defgroup ADC_EOCSelection ADC EOCSelection - * @{ - */ -#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) -#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) -/** - * @} - */ - -/** @defgroup ADC_Overrun ADC Overrun - * @{ - */ -#define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) -#define ADC_OVR_DATA_PRESERVED (0x00000001U) -/** - * @} - */ - -/** @defgroup ADC_rank ADC rank - * @{ - */ -#define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ -#define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ -/** - * @} - */ - -/** @defgroup ADC_sampling_times ADC sampling times - * @{ - */ -/* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */ -/* to distinguish this parameter versus reset value 0x00000000, */ -/* in the context of management of parameters "SamplingTimeCommon" */ -/* and "SamplingTime" (obsolete)). */ -#define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */ -#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ -#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ -#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ -#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ -#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ -#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ -#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode - * @{ - */ -#define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) -#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) -#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) -/** - * @} - */ - -/** @defgroup ADC_Event_type ADC Event type - * @{ - */ -#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ -#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition ADC interrupts definition - * @{ - */ -#define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ -#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ -#define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ -#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ -#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ -/** - * @} - */ - -/** @defgroup ADC_flags_definition ADC flags definition - * @{ - */ -#define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ -#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ -#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ -#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ -/** - * @} - */ - -/** - * @} - */ - - -/* Private constants ---------------------------------------------------------*/ - -/** @addtogroup ADC_Private_Constants ADC Private Constants - * @{ - */ - -/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular - * @{ - */ - -/* List of external triggers of regular group for ADC1: */ -/* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U) -#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) -#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) -#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) -#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) -/** - * @} - */ - -/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Macros ADC Exported Macros - * @{ - */ -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ - -/** - * @brief Enable the ADC peripheral - * @param __HANDLE__ ADC handle - * @retval None - */ -#define __HAL_ADC_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) - -/** - * @brief Disable the ADC peripheral - * @param __HANDLE__ ADC handle - * @retval None - */ -#define __HAL_ADC_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ - __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ - } while(0) - -/** - * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC Interrupt - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source - * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source - * @arg ADC_IT_OVR: ADC overrun interrupt source - * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source - * @arg ADC_IT_RDY: ADC Ready interrupt source - * @retval None - */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC Interrupt - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source - * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source - * @arg ADC_IT_OVR: ADC overrun interrupt source - * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source - * @arg ADC_IT_RDY: ADC Ready interrupt source - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - -/** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC interrupt source to check - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source - * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source - * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source - * @arg ADC_IT_OVR: ADC overrun interrupt source - * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source - * @arg ADC_IT_RDY: ADC Ready interrupt source - * @retval State ofinterruption (SET or RESET) - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Get the selected ADC's flag status. - * @param __HANDLE__ ADC handle - * @param __FLAG__ ADC flag - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag - * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag - * @arg ADC_FLAG_AWD: ADC Analog watchdog flag - * @arg ADC_FLAG_OVR: ADC overrun flag - * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag - * @arg ADC_FLAG_RDY: ADC Ready flag - * @retval None - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the ADC's pending flags - * @param __HANDLE__ ADC handle - * @param __FLAG__ ADC flag - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag - * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag - * @arg ADC_FLAG_AWD: ADC Analog watchdog flag - * @arg ADC_FLAG_OVR: ADC overrun flag - * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag - * @arg ADC_FLAG_RDY: ADC Ready flag - * @retval None - */ -/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - (((__HANDLE__)->Instance->ISR) = (__FLAG__)) - -/** @brief Reset ADC handle state - * @param __HANDLE__ ADC handle - * @retval None - */ -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - ((__HANDLE__)->State = HAL_ADC_STATE_RESET) - -/** - * @} - */ - - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - - -/** - * @brief Verification of hardware constraints before ADC can be enabled - * @param __HANDLE__ ADC handle - * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) - */ -#define ADC_ENABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \ - ) == RESET \ - ) ? SET : RESET) - -/** - * @brief Verification of hardware constraints before ADC can be disabled - * @param __HANDLE__ ADC handle - * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) - */ -#define ADC_DISABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ - ) ? SET : RESET) - -/** - * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__ ADC handle - * @retval SET (ADC enabled) or RESET (ADC disabled) - */ -/* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ -/* performed automatically by hardware and flag ADC_FLAG_RDY is not */ -/* set. */ -#define ADC_IS_ENABLE(__HANDLE__) \ - (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ - (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ - ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ - ) ? SET : RESET) - -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__ ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) - -/** - * @brief Check if no conversion on going on regular group - * @param __HANDLE__ ADC handle - * @retval SET (conversion is on going) or RESET (no conversion is on going) - */ -#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ - ) ? RESET : SET) - -/** - * @brief Returns resolution bits in CFGR1 register: RES[1:0]. - * Returned value is among parameters to @ref ADC_Resolution. - * @param __HANDLE__ ADC handle - * @retval None - */ -#define ADC_GET_RESOLUTION(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) - -/** - * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. - * Returned value is among parameters to @ref ADC_Resolution. - * @param __HANDLE__ ADC handle - * @retval None - */ -#define ADC_GET_SAMPLINGTIME(__HANDLE__) \ - (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) - -/** - * @brief Simultaneously clears and sets specific bits of the handle State - * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), - * the first parameter is the ADC handle State, the second parameter is the - * bit field to clear, the third and last parameter is the bit field to set. - * @retval None - */ -#define ADC_STATE_CLR_SET MODIFY_REG - -/** - * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__ ADC handle - * @retval None - */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ - ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) - - -/** - * @brief Configure the channel number into channel selection register - * @param _CHANNEL_ ADC Channel - * @retval None - */ -/* This function converts ADC channels from numbers (see defgroup ADC_channels) - to bitfields, to get the equivalence of CMSIS channels: - ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) - ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) - ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) - ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) - ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) - ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) - ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) - ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) - ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) - ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) - ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) - ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) - ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) - ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) - ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) - ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) - ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) - ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) - ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) -*/ -#define ADC_CHSELR_CHANNEL(_CHANNEL_) \ - ( 1U << (_CHANNEL_)) - -/** - * @brief Set the ADC's sample time - * @param _SAMPLETIME_ Sample time parameter. - * @retval None - */ -/* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ -/* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */ -/* distinguish this parameter versus reset value 0x00000000, */ -/* in the context of management of parameters "SamplingTimeCommon" */ -/* and "SamplingTime" (obsolete)). */ -#define ADC_SMPR_SET(_SAMPLETIME_) \ - ((_SAMPLETIME_) & (ADC_SMPR_SMP)) - -/** - * @brief Set the Analog Watchdog 1 channel. - * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. - * @retval None - */ -#define ADC_CFGR_AWDCH(_CHANNEL_) \ - ((_CHANNEL_) << 26U) - -/** - * @brief Enable ADC discontinuous conversion mode for regular group - * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. - * @retval None - */ -#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ - ((_REG_DISCONTINUOUS_MODE_) << 16U) - -/** - * @brief Enable the ADC auto off mode. - * @param _AUTOOFF_ Auto off bit enable or disable. - * @retval None - */ -#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ - ((_AUTOOFF_) << 15U) - -/** - * @brief Enable the ADC auto delay mode. - * @param _AUTOWAIT_ Auto delay bit enable or disable. - * @retval None - */ -#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ - ((_AUTOWAIT_) << 14U) - -/** - * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_ Continuous mode. - * @retval None - */ -#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ - ((_CONTINUOUS_MODE_) << 13U) - -/** - * @brief Enable ADC overrun mode. - * @param _OVERRUN_MODE_ Overrun mode. - * @retval Overun bit setting to be programmed into CFGR register - */ -/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ -/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ -/* as the default case to be compliant with other STM32 devices. */ -#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ - ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ - )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ - ) - -/** - * @brief Enable ADC scan mode to convert multiple ranks with sequencer. - * @param _SCAN_MODE_ Scan conversion mode. - * @retval None - */ -/* Note: Scan mode set using this macro (instead of parameter direct set) */ -/* due to different modes on other STM32 devices: to avoid any */ -/* unwanted setting, the exact parameter corresponding to the device */ -/* must be passed to this macro. */ -#define ADC_SCANDIR(_SCAN_MODE_) \ - ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ - )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ - ) - -/** - * @brief Enable the ADC DMA continuous request. - * @param _DMACONTREQ_MODE_ DMA continuous request mode. - * @retval None - */ -#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ - ((_DMACONTREQ_MODE_) << 1U) - -/** - * @brief Configure the analog watchdog high threshold into register TR. - * @param _Threshold_ Threshold value - * @retval None - */ -#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ - ((_Threshold_) << 16U) - -/** - * @brief Shift the AWD threshold in function of the selected ADC resolution. - * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. - * If resolution 12 bits, no shift. - * If resolution 10 bits, shift of 2 ranks on the left. - * If resolution 8 bits, shift of 4 ranks on the left. - * If resolution 6 bits, shift of 6 ranks on the left. - * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) - * @param __HANDLE__ ADC handle - * @param _Threshold_ Value to be shifted - * @retval None - */ -#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ - ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2)) - - -#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ - ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ - ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ - ((RESOLUTION) == ADC_RESOLUTION_10B) || \ - ((RESOLUTION) == ADC_RESOLUTION_8B) || \ - ((RESOLUTION) == ADC_RESOLUTION_6B) ) - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ - ((ALIGN) == ADC_DATAALIGN_LEFT) ) - -#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ - ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) - -#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) - -#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) - -#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ - ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) - -#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ - ((WATCHDOG) == ADC_RANK_NONE) ) - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ - ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) - -#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) - -#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ - ((EVENT) == ADC_OVR_EVENT) ) - -/** @defgroup ADC_range_verification ADC range verification - * in function of ADC resolution selected (12, 10, 8 or 6 bits) - * @{ - */ -#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ - ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ - (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ - (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ - (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) -/** - * @} - */ - -/** @defgroup ADC_regular_rank_verification ADC regular rank verification - * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U))) -/** - * @} - */ - -/** - * @} - */ - -/* Include ADC HAL Extension module */ -#include "stm32f0xx_hal_adc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_Exported_Functions_Group1 - * @{ - */ - - -/* Initialization and de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); -/** - * @} - */ - -/* IO operation functions *****************************************************/ - -/** @addtogroup ADC_Exported_Functions_Group2 - * @{ - */ - - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); - -/* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); -/** - * @} - */ - - -/* Peripheral Control functions ***********************************************/ -/** @addtogroup ADC_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); -/** - * @} - */ - - -/* Peripheral State functions *************************************************/ -/** @addtogroup ADC_Exported_Functions_Group4 - * @{ - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_ADC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h deleted file mode 100644 index 23a4b34..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h +++ /dev/null @@ -1,315 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_adc_ex.h - * @author MCD Application Team - * @brief Header file of ADC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_ADC_EX_H -#define __STM32F0xx_HAL_ADC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants ADC Exported Constants - * @{ - */ - -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) -#define ADC_CCR_ALL (ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN) -#else -#define ADC_CCR_ALL (ADC_CCR_TSEN | ADC_CCR_VREFEN) -#endif - -/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular - * @{ - */ -/* List of external triggers with generic trigger name, sorted by trigger */ -/* name: */ - -/* External triggers of regular group for ADC1 */ -#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO -#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4 -#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO -#define ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + 1U) - -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) -#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO -#endif - -#if !defined(STM32F030x6) && !defined(STM32F070x6) && !defined(STM32F042x6) -#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO -#endif - -/** - * @} - */ - - -/** @defgroup ADC_channels ADC channels - * @{ - */ -/* Note: Depending on devices, some channels may not be available on package */ -/* pins. Refer to device datasheet for channels availability. */ -/* Note: Channels are used by bitfields for setting of channel selection */ -/* (register ADC_CHSELR) and used by number for setting of analog */ -/* watchdog channel (bits AWDCH in register ADC_CFGR1). */ -/* Channels are defined with decimal numbers and converted them to */ -/* bitfields when needed. */ -#define ADC_CHANNEL_0 ( 0x00000000U) -#define ADC_CHANNEL_1 ( 0x00000001U) -#define ADC_CHANNEL_2 ( 0x00000002U) -#define ADC_CHANNEL_3 ( 0x00000003U) -#define ADC_CHANNEL_4 ( 0x00000004U) -#define ADC_CHANNEL_5 ( 0x00000005U) -#define ADC_CHANNEL_6 ( 0x00000006U) -#define ADC_CHANNEL_7 ( 0x00000007U) -#define ADC_CHANNEL_8 ( 0x00000008U) -#define ADC_CHANNEL_9 ( 0x00000009U) -#define ADC_CHANNEL_10 ( 0x0000000AU) -#define ADC_CHANNEL_11 ( 0x0000000BU) -#define ADC_CHANNEL_12 ( 0x0000000CU) -#define ADC_CHANNEL_13 ( 0x0000000DU) -#define ADC_CHANNEL_14 ( 0x0000000EU) -#define ADC_CHANNEL_15 ( 0x0000000FU) -#define ADC_CHANNEL_16 ( 0x00000010U) -#define ADC_CHANNEL_17 ( 0x00000011U) - -#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 -#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 - -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) -#define ADC_CHANNEL_18 ( 0x00000012U) -#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup ADCEx_Private_Macros ADCEx Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - -/** - * @brief Test if the selected ADC channel is an internal channel - * VrefInt/TempSensor/Vbat - * Note: On STM32F0, availability of internal channel Vbat depends on - * devices lines. - * @param __CHANNEL__ ADC channel - * @retval None - */ -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) -#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == ADC_CHANNEL_VBAT) \ - ) -#else -#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ - ((__CHANNEL__) == ADC_CHANNEL_VREFINT) \ - ) -#endif - -/** - * @brief Select the internal measurement path to be enabled/disabled - * corresponding to the selected ADC internal channel - * VrefInt/TempSensor/Vbat. - * Note: On STM32F0, availability of internal channel Vbat depends on - * devices lines. - * @param __CHANNEL__ ADC channel - * @retval Bit of register ADC_CCR - */ -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) -#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \ - (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \ - )? \ - (ADC_CCR_TSEN) \ - : \ - ( \ - ( (__CHANNEL__) == ADC_CHANNEL_VREFINT \ - )? \ - (ADC_CCR_VREFEN) \ - : \ - (ADC_CCR_VBATEN) \ - ) \ - ) -#else -#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \ - (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \ - )? \ - (ADC_CCR_TSEN) \ - : \ - (ADC_CCR_VREFEN) \ - ) -#endif - - -#if defined (STM32F030x6) || defined (STM32F070x6) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#elif defined (STM32F042x6) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) - -#elif defined (STM32F030xC) || defined (STM32F070xB) || defined (STM32F030x8) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#else -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#endif - -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ - ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ - ((CHANNEL) == ADC_CHANNEL_VBAT) ) -#else -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ - ((CHANNEL) == ADC_CHANNEL_VREFINT) ) -#endif - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADCEx_Exported_Functions - * @{ - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup ADCEx_Exported_Functions_Group1 - * @{ - */ - -/* ADC calibration */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_ADC_EX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h deleted file mode 100644 index f1f3de8..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h +++ /dev/null @@ -1,149 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_CORTEX_H -#define __STM32F0xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX CORTEX - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) -#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported Macros -----------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ -/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and de-initialization functions *******************************/ -void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * @{ - */ - -/* Peripheral Control functions *************************************************/ -uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h deleted file mode 100644 index 306d23f..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_DEF -#define __STM32F0xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" -#if defined(USE_HAL_LEGACY) - #include "Legacy/stm32_hal_legacy.h" -#endif -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00U, - HAL_ERROR = 0x01U, - HAL_BUSY = 0x02U, - HAL_TIMEOUT = 0x03U -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00U, - HAL_LOCKED = 0x01U -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ - (__DMA_HANDLE_).Parent = (__HANDLE__); \ - } while(0) - -#define UNUSED(x) ((void)(x)) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__ specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) - -#if (USE_RTOS == 1) - #error " USE_RTOS should be 0 in the current HAL release " -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32F0xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h deleted file mode 100644 index f6f5b2c..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h +++ /dev/null @@ -1,579 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_DMA_H -#define __STM32F0xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Types DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ -} DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - -/** - * @brief HAL DMA Callback ID structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ - -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ -} DMA_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ -#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ - -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @{ - */ -#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @{ - */ -#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @{ - */ - -#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ -#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ -#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ -#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ -#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ -#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ -#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ -#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ -#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ -#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ -#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ -#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ -#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ -#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ -#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ -#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ -#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ -#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ -#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ -#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ -#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ -#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ -#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ -#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ -#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ -#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ -#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ -#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ - -/** - * @} - */ - -#if defined(SYSCFG_CFGR1_DMA_RMP) -/** @defgroup HAL_DMA_remapping HAL DMA remapping - * Elements values convention: 0xYYYYYYYY - * - YYYYYYYY : Position in the SYSCFG register CFGR1 - * @{ - */ -#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap - 0: No remap (ADC DMA requests mapped on DMA channel 1 - 1: Remap (ADC DMA requests mapped on DMA channel 2 */ -#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap - 0: No remap (USART1_TX DMA request mapped on DMA channel 2 - 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ -#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap - 0: No remap (USART1_RX DMA request mapped on DMA channel 3 - 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ -#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap - 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) - 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ -#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap - 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 - 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ -#if defined (STM32F070xB) -#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. - 0: Disabled, need to remap before use - 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ - -#endif - -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) -#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only - 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) - 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ -#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only - 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) - 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ -#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) - 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ -#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) - 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ -#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) - 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ -#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) - 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ -#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) - 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ -#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) - 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ -#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) - 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ -#endif - -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_DMA_RMP */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state - * @param __HANDLE__ DMA handle. - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) - - -/* Interrupt & Flag management */ - -/** - * @brief Enables the specified DMA Channel interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified DMA Channel interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) - -/** - * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) - -/** - * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. - * @param __HANDLE__ DMA handle - * - * @retval The number of remaining data units in the current DMA Channel transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) - -#if defined(SYSCFG_CFGR1_DMA_RMP) -/** @brief DMA remapping enable/disable macros - * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping - */ -#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ - SYSCFG->CFGR1 |= (__DMA_REMAP__); \ - }while(0) -#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ - SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ - }while(0) -#endif /* SYSCFG_CFGR1_DMA_RMP */ - -/** - * @} - */ - -/* Include DMA HAL Extension module */ -#include "stm32f0xx_hal_dma_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * @{ - */ -/* Input and Output operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Macros - * @{ - */ -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) - -#if defined(SYSCFG_CFGR1_DMA_RMP) - -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) -#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ - ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ - ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ - ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ - ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ - ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ - ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ - ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ - ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ - ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) -#elif defined (STM32F070xB) -#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ - ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ - ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ - ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) -#else -#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ - ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ - ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ - ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ - ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) -#endif - -#endif /* SYSCFG_CFGR1_DMA_RMP */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h deleted file mode 100644 index d6395df..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h +++ /dev/null @@ -1,827 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_DMA_EX_H -#define __STM32F0xx_HAL_DMA_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants - * @{ - */ -#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#if !defined(STM32F030xC) -#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ -#endif /* !defined(STM32F030xC) */ - -/****************** DMA1 remap bit field definition********************/ -/* DMA1 - Channel 1 */ -#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ -#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ -#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ -#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 2 */ -#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ -#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ -#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ -#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ -#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 3 */ -#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ -#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ -#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 4 */ -#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ -#endif /* !defined(STM32F030xC) */ -#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ -#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ -#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ -#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ -#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ -#endif /* !defined(STM32F030xC) */ - -/* DMA1 - Channel 5 */ -#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ -#if !defined(STM32F030xC) -#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ -#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ -#endif /* !defined(STM32F030xC) */ - -#if !defined(STM32F030xC) -/* DMA1 - Channel 6 */ -#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ -#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ -#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ -/* DMA1 - Channel 7 */ -#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ -#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ -#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ -#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ - -/****************** DMA2 remap bit field definition********************/ -/* DMA2 - Channel 1 */ -#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ -#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ -/* DMA2 - Channel 2 */ -#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ -#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ -/* DMA2 - Channel 3 */ -#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ -#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ -#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ -#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ -/* DMA2 - Channel 4 */ -#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ -#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ -#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ -#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ -/* DMA2 - Channel 5 */ -#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ -#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ -#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ -#endif /* !defined(STM32F030xC) */ - -#if defined(STM32F091xC) || defined(STM32F098xx) -#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ - ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ - ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ - ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) - -#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ - ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ - ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ - ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ - ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ - ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ - ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ - ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ - ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ - ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ - ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ - ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ - ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030xC) -#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ - ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ - ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ - ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ - ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ - ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) -#endif /* STM32F030xC */ - -/** - * @} - */ -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros - * @{ - */ -/* Interrupt & Flag management */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ - DMA_FLAG_GL7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_7 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) - -#elif defined(STM32F091xC) || defined(STM32F098xx) -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - DMA_FLAG_TC5) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - DMA_FLAG_HT5) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - DMA_FLAG_TE5) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ - DMA_FLAG_GL5) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ - (DMA1->ISR & (__FLAG__))) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ - (DMA1->IFCR = (__FLAG__))) - -#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ -/** - * @brief Returns the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - DMA_FLAG_TC5) - -/** - * @brief Returns the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - DMA_FLAG_HT5) - -/** - * @brief Returns the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - DMA_FLAG_TE5) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ - DMA_FLAG_GL5) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_5 to select the DMA Channel flag. - * @retval The state of FLAG (SET or RESET). - */ - -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) - -/** - * @brief Clears the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * Where x can be 1_5 to select the DMA Channel flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) - -#endif - - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __HAL_DMA1_REMAP(__REQUEST__) \ - do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ - DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ - DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ - }while(0) - -#if defined(STM32F091xC) || defined(STM32F098xx) -#define __HAL_DMA2_REMAP(__REQUEST__) \ - do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ - DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ - DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ - }while(0) -#endif /* STM32F091xC || STM32F098xx */ - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_DMA_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h deleted file mode 100644 index f41a41b..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h +++ /dev/null @@ -1,369 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of Flash HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_FLASH_H -#define __STM32F0xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Private_Constants - * @{ - */ -#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ -/** - * @} - */ - -/** @addtogroup FLASH_Private_Macros - * @{ - */ - -#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) - -#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ - ((__LATENCY__) == FLASH_LATENCY_1)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0U, - FLASH_PROC_PAGEERASE = 1U, - FLASH_PROC_MASSERASE = 2U, - FLASH_PROC_PROGRAMHALFWORD = 3U, - FLASH_PROC_PROGRAMWORD = 4U, - FLASH_PROC_PROGRAMDOUBLEWORD = 5U -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ - - __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ - - __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ - - __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ - - HAL_LockTypeDef Lock; /*!< FLASH locking object */ - - __IO uint32_t ErrorCode; /*!< FLASH error code - This parameter can be a value of @ref FLASH_Error_Codes */ -} FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error_Codes FLASH Error Codes - * @{ - */ - -#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ -#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ -#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ - -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) - - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * The value of this parameter depend on device used within the same series - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - -/** - * @} - */ - -/** @defgroup FLASH_Prefetch FLASH Prefetch - * @brief macros to handle FLASH Prefetch buffer - * @{ - */ -/** - * @brief Enable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) - -/** - * @} - */ - -/** @defgroup FLASH_Interrupt FLASH Interrupts - * @brief macros to handle FLASH interrupts - * @{ - */ - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__ specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg @ref FLASH_FLAG_BSY FLASH Busy flag - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Include FLASH HAL Extended module */ -#include "stm32f0xx_hal_flash_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); - -/* FLASH IRQ handler function */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -uint32_t HAL_FLASH_GetError(void); - -/** - * @} - */ - -/** - * @} - */ - -/* Private function -------------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions - * @{ - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h deleted file mode 100644 index d382a9d..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h +++ /dev/null @@ -1,464 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of Flash HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_FLASH_EX_H -#define __STM32F0xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/** @addtogroup FLASHEx_Private_Macros - * @{ - */ -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) - -#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)) - -#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ - ((VALUE) == OB_WRPSTATE_ENABLE)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_1))/*||\ - ((LEVEL) == OB_RDP_LEVEL_2))*/ - -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) - -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) - -#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) - -#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) - -#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) - -#if defined(FLASH_OBR_BOOT_SEL) -#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET)) -#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) -#endif /* FLASH_OBR_BOOT_SEL */ - - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) - -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END) - -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types - * @{ - */ -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - - uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled - This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */ - - uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. - This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Options bytes program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASHEx_OB_Type */ - - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_OB_WRP_State */ - - uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected - This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ - - uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. - This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ - - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: - IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY - This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, - @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and - @ref FLASHEx_OB_RAM_Parity_Check_Enable */ - - uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed - This parameter can be a value of @ref FLASHEx_OB_Data_Address */ - - uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ -} FLASH_OBProgramInitTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Page_Size FLASHEx Page Size - * @{ - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \ - || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6) -#define FLASH_PAGE_SIZE 0x400U -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define FLASH_PAGE_SIZE 0x800U -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ -/** - * @} - */ - -/** @defgroup FLASHEx_Type_Erase FLASH Type Erase - * @{ - */ -#define FLASH_TYPEERASE_PAGES (0x00U) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_GPIO_H -#define __STM32F0xx_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins - This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ -}GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0U, - GPIO_PIN_SET -}GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ -/** @defgroup GPIO_pins GPIO pins - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ - -#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode GPIO mode - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) - * @{ - */ -#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup GPIO_speed GPIO speed - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */ -/** - * @} - */ - - /** @defgroup GPIO_pull GPIO pull - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ -#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Check whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__ specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending flags. - * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Check whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending bits. - * @param __EXTI_LINE__ specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) - -#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ - ((__MODE__) == GPIO_MODE_AF_PP) ||\ - ((__MODE__) == GPIO_MODE_AF_OD) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING) ||\ - ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ - ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_ANALOG)) - -#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) - -#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ - ((__PULL__) == GPIO_PULLUP) || \ - ((__PULL__) == GPIO_PULLDOWN)) -/** - * @} - */ - -/* Include GPIO HAL Extended module */ -#include "stm32f0xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); - -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h deleted file mode 100644 index 22b94ef..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h +++ /dev/null @@ -1,816 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_GPIO_EX_H -#define __STM32F0xx_HAL_GPIO_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants - * @{ - */ - -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ - -#if defined (STM32F030x6) -/*------------------------- STM32F030x6---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F030x6 */ - -/*---------------------------------- STM32F030x8 -------------------------------------------*/ -#if defined (STM32F030x8) -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F030x8 */ - -#if defined (STM32F031x6) || defined (STM32F038xx) -/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDAT ((uint8_t)0x00U) /*!< AF0: SWDAT Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F031x6 || STM32F038xx */ - -#if defined (STM32F051x8) || defined (STM32F058xx) -/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F051x8/STM32F058xx */ - -#if defined (STM32F071xB) -/*--------------------------- STM32F071xB ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: AEVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F071xB */ - - -#if defined(STM32F091xC) || defined(STM32F098xx) -/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ -#define GPIO_AF0_USART8 ((uint8_t)0x00U) /*!< AF0: USART8 Alternate Function mapping */ -#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_USART4 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ -#define GPIO_AF1_USART5 ((uint8_t)0x01U) /*!< AF1: USART5 Alternate Function mapping */ -#define GPIO_AF1_USART6 ((uint8_t)0x01U) /*!< AF1: USART6 Alternate Function mapping */ -#define GPIO_AF1_USART7 ((uint8_t)0x01U) /*!< AF1: USART7 Alternate Function mapping */ -#define GPIO_AF1_USART8 ((uint8_t)0x01U) /*!< AF1: USART8 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ -#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ -#define GPIO_AF2_USART7 ((uint8_t)0x02U) /*!< AF2: USART7 Alternate Function mapping */ -#define GPIO_AF2_USART8 ((uint8_t)0x02U) /*!< AF2: USART8 Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ -#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030xC) -/*--------------------------- STM32F030xC ----------------------------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ -#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ -#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F030xC */ - -#if defined (STM32F072xB) || defined (STM32F078xx) -/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ -#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ -#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -/* AF 7 */ -#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ -#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) - -#endif /* STM32F072xB || STM32F078xx */ - -#if defined (STM32F070xB) -/*---------------------------------- STM32F070xB ---------------------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ -#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ -#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ -#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ -#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F070xB */ - -#if defined (STM32F042x6) || defined (STM32F048xx) -/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ -#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ -#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined (STM32F070x6) -/*--------------------------------------- STM32F070x6 ----------------------------------------*/ -/* AF 0 */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ -#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ -#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ - -/* AF 1 */ -#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ -#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ -#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ -#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ - -/* AF 2 */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ -#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ - -/* AF 3 */ -#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ -#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ - -/* AF 4 */ -#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ - -/* AF 5 */ -#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ -#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ -#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ -#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ -#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ - -/* AF 6 */ -#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) - -#endif /* STM32F070x6 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros - * @{ - */ - -/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index -* @{ - */ -#if defined(GPIOD) && defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 5U) -#endif - -#if defined(GPIOD) && !defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U : 5U) -#endif - -#if !defined(GPIOD) && defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOE))? 4U : 5U) -#endif - -#if !defined(GPIOD) && !defined(GPIOE) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 5U) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h deleted file mode 100644 index 7970425..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h +++ /dev/null @@ -1,708 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c.h - * @author MCD Application Team - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_I2C_H -#define __STM32F0xx_HAL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ - -} I2C_InitTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap :\n - * b7-b6 Error information\n - * 00 : No Error\n - * 01 : Abort (Abort user request on going)\n - * 10 : Timeout\n - * 11 : Error\n - * b5 IP initilisation status\n - * 0 : Reset (IP not initialized)\n - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n - * b4 (not used)\n - * x : Should be set to 0\n - * b3\n - * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (IP in Address Listen Mode)\n - * b2 Intrinsic process state\n - * 0 : Ready\n - * 1 : Busy (IP busy with some configuration or internal operations)\n - * b1 Rx state\n - * 0 : Ready (no Rx operation ongoing)\n - * 1 : Busy (Rx operation ongoing)\n - * b0 Tx state\n - * 0 : Ready (no Tx operation ongoing)\n - * 1 : Busy (Tx operation ongoing) - * @{ - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ - -} HAL_I2C_StateTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap :\n - * b7 (not used)\n - * x : Should be set to 0\n - * b6\n - * 0 : None\n - * 1 : Memory (HAL I2C communication is in Memory Mode)\n - * b5\n - * 0 : None\n - * 1 : Slave (HAL I2C communication is in Slave Mode)\n - * b4\n - * 0 : None\n - * 1 : Master (HAL I2C communication is in Master Mode)\n - * b3-b2-b1-b0 (not used)\n - * xxxx : Should be set to 0000 - * @{ - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -} HAL_I2C_ModeTypeDef; - -/** - * @} - */ - -/** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition - * @{ - */ -#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ - */ -typedef struct __I2C_HandleTypeDef -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can - be a value of @ref I2C_XFEROPTIONS */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -} I2C_HandleTypeDef; -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options - * @{ - */ -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -/** - * @} - */ - -/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE (0x00000000U) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks - * @{ - */ -#define I2C_OA2_NOMASK ((uint8_t)0x00U) -#define I2C_OA2_MASK01 ((uint8_t)0x01U) -#define I2C_OA2_MASK02 ((uint8_t)0x02U) -#define I2C_OA2_MASK03 ((uint8_t)0x03U) -#define I2C_OA2_MASK04 ((uint8_t)0x04U) -#define I2C_OA2_MASK05 ((uint8_t)0x05U) -#define I2C_OA2_MASK06 ((uint8_t)0x06U) -#define I2C_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - -/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE (0x00000000U) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE (0x00000000U) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT (0x00000001U) -#define I2C_MEMADD_SIZE_16BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View - * @{ - */ -#define I2C_DIRECTION_TRANSMIT (0x00000000U) -#define I2C_DIRECTION_RECEIVE (0x00000001U) -/** - * @} - */ - -/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode - * @{ - */ -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode - * @{ - */ -#define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @brief I2C Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) - -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_TXIS Transmit interrupt status - * @arg @ref I2C_FLAG_RXNE Receive data register not empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_TC Transfer complete (master mode) - * @arg @ref I2C_FLAG_TCR Transfer complete reload - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * @arg @ref I2C_FLAG_BUSY Bus busy - * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -/** - * @} - */ - -/* Include I2C HAL Extended module */ -#include "stm32f0xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions******************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* IO operation functions ****************************************************/ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -/** - * @} - */ - -/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @{ - */ -/* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32f0xx_hal_i2c.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h deleted file mode 100644 index 815213a..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h +++ /dev/null @@ -1,188 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c_ex.h - * @author MCD Application Team - * @brief Header file of I2C HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_I2C_EX_H -#define __STM32F0xx_HAL_I2C_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE 0x00000000U -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus - * @{ - */ -#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ -#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) -#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ -#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ -#else -#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */ -#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */ -#endif -#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ -#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ -#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ -#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) -#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ -#else -#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ -#endif -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) -#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ -#else -#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ -#endif -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -#if defined(I2C_CR1_WUPEN) -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); -#endif -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ - ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions - * @{ - */ -/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_I2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h deleted file mode 100644 index 8f1f7dd..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_PWR_H -#define __STM32F0xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON (0x00000000U) -#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro PWR Exported Macro - * @{ - */ - -/** @brief Check PWR flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * Warning: this Flag is not available on STM32F030x8 products - * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference - * voltage VREFINT is ready. - * Warning: this Flag is not available on STM32F030x8 products - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) - - -/** - * @} - */ - -/* Include PWR HAL Extension module */ -#include "stm32f0xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); - -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions **********************************************/ -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); - -/* WakeUp pins configuration functions ****************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes configuration functions ************************************/ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h deleted file mode 100644 index dab4f98..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h +++ /dev/null @@ -1,475 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_PWR_EX_H -#define __STM32F0xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Types PWREx Exported Types - * @{ - */ - -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level - This parameter can be a value of @ref PWREx_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWREx_PVD_Mode */ -}PWR_PVDTypeDef; - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ - - -/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins - * @{ - */ -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) -#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) -#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) -#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) -#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) -#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) -#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8) - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN5) || \ - ((PIN) == PWR_WAKEUP_PIN6) || \ - ((PIN) == PWR_WAKEUP_PIN7) || \ - ((PIN) == PWR_WAKEUP_PIN8)) - -#elif defined(STM32F030xC) || defined (STM32F070xB) -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) -#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) -#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) -#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) -#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN5) || \ - ((PIN) == PWR_WAKEUP_PIN6) || \ - ((PIN) == PWR_WAKEUP_PIN7)) - -#elif defined(STM32F042x6) || defined (STM32F048xx) -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) -#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) -#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) -#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN6) || \ - ((PIN) == PWR_WAKEUP_PIN7)) - -#else -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) - - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2)) - -#endif - -/** - * @} - */ - -/** @defgroup PWREx_EXTI_Line PWREx EXTI Line - * @{ - */ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) - -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) - -#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ - -#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) ||*/ -/** - * @} - */ - -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) -/** - * @} - */ - -/** @defgroup PWREx_PVD_Mode PWREx PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ - -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) -/** - * @} - */ -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -/** @defgroup PWREx_Flag PWREx Flag - * @{ - */ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC) -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#else -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Macros PWREx Exported Macros - * @{ - */ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -/** - * @brief Enable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - -/** - * @brief PVD EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) - -/** - * @brief PVD EXTI line configuration: set rising edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - -/** - * @brief Check whether the specified PVD EXTI interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD EXTI flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) - -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -/** - * @brief Enable interrupt on Vddio2 Monitor Exti Line 31. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Disable interrupt on Vddio2 Monitor Exti Line 31. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \ - do{ \ - EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ - EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ - } while(0) - -/** - * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) - -/** - * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. - * @retval EXTI VDDIO2 Monitor Line Status. - */ -#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Clear the VDDIO2 Monitor EXTI flag. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2)) - - -#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 - * @{ - */ -/* I/O operation functions ***************************************************/ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -void HAL_PWREx_Vddio2Monitor_IRQHandler(void); -void HAL_PWREx_Vddio2MonitorCallback(void); -#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/* Peripheral Control functions **********************************************/ -#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F072xB) || \ - defined (STM32F091xC) -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); -#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F072xB) || */ - /* defined (STM32F091xC) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -void HAL_PWREx_EnableVddio2Monitor(void); -void HAL_PWREx_DisableVddio2Monitor(void); -#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h deleted file mode 100644 index ce9bda5..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h +++ /dev/null @@ -1,1702 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_RCC_H -#define __STM32F0xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @addtogroup RCC_Private_Constants - * @{ - */ - -/** @defgroup RCC_Timeout RCC Timeout - * @{ - */ - -/* Disable Backup domain write protection state change timeout */ -#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ -/* LSE state change timeout */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#if defined(RCC_HSI48_SUPPORT) -#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_Register_Offset Register offsets - * @{ - */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00 -#define RCC_CFGR_OFFSET 0x04 -#define RCC_CIR_OFFSET 0x08 -#define RCC_BDCR_OFFSET 0x20 -#define RCC_CSR_OFFSET 0x24 - -/** - * @} - */ - - -/* CR register byte 2 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) - -/* Defines used for Flags */ -#define CR_REG_INDEX ((uint8_t)1U) -#define CR2_REG_INDEX ((uint8_t)2U) -#define BDCR_REG_INDEX ((uint8_t)3U) -#define CSR_REG_INDEX ((uint8_t)4U) - -/* Bits position in in the CFGR register */ -#define RCC_CFGR_PLLMUL_BITNUMBER 18U -#define RCC_CFGR_HPRE_BITNUMBER 4U -#define RCC_CFGR_PPRE_BITNUMBER 8U -/* Flags in the CFGR2 register */ -#define RCC_CFGR2_PREDIV_BITNUMBER 0 -/* Flags in the CR register */ -#define RCC_CR_HSIRDY_BitNumber 1 -#define RCC_CR_HSERDY_BitNumber 17 -#define RCC_CR_PLLRDY_BitNumber 25 -/* Flags in the CR2 register */ -#define RCC_CR2_HSI14RDY_BitNumber 1 -#define RCC_CR2_HSI48RDY_BitNumber 16 -/* Flags in the BDCR register */ -#define RCC_BDCR_LSERDY_BitNumber 1 -/* Flags in the CSR register */ -#define RCC_CSR_LSIRDY_BitNumber 1 -#define RCC_CSR_V18PWRRSTF_BitNumber 23 -#define RCC_CSR_RMVF_BitNumber 24 -#define RCC_CSR_OBLRSTF_BitNumber 25 -#define RCC_CSR_PINRSTF_BitNumber 26 -#define RCC_CSR_PORRSTF_BitNumber 27 -#define RCC_CSR_SFTRSTF_BitNumber 28 -#define RCC_CSR_IWDGRSTF_BitNumber 29 -#define RCC_CSR_WWDGRSTF_BitNumber 30 -#define RCC_CSR_LPWRRSTF_BitNumber 31 -/* Flags in the HSITRIM register */ -#define RCC_CR_HSITRIM_BitNumber 3 -#define RCC_HSI14TRIM_BIT_NUMBER 3 -#define RCC_FLAG_MASK ((uint8_t)0x1FU) - -/** - * @} - */ - -/** @addtogroup RCC_Private_Macros - * @{ - */ -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL)) -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) -#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ - ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ - ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ - ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ - ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ - ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ - ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ - ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) - -#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ - ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ - ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ - ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ - ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ - ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ - ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ - ((__MUL__) == RCC_PLL_MUL16)) -#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ - (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ - (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) -#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) -#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< PLLState: The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ - - uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ - -} RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ - - uint32_t HSI14State; /*!< The new state of the HSI14. - This parameter can be a value of @ref RCC_HSI14_Config */ - - uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - -#if defined(RCC_HSI48_SUPPORT) - uint32_t HSI48State; /*!< The new state of the HSI48. - This parameter can be a value of @ref RCC_HSI48_Config */ - -#endif /* RCC_HSI48_SUPPORT */ - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ - -} RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_Clock_Source */ - -} RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ - -#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ - -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE (0x00000000U) -#define RCC_OSCILLATORTYPE_HSE (0x00000001U) -#define RCC_OSCILLATORTYPE_HSI (0x00000002U) -#define RCC_OSCILLATORTYPE_LSE (0x00000004U) -#define RCC_OSCILLATORTYPE_LSI (0x00000008U) -#define RCC_OSCILLATORTYPE_HSI14 (0x00000010U) -#if defined(RCC_HSI48_SUPPORT) -#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ -#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ -#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ -#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ -#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ - -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ - -#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ - -/** - * @} - */ - -/** @defgroup RCC_HSI14_Config RCC HSI14 Config - * @{ - */ -#define RCC_HSI14_OFF (0x00000000U) -#define RCC_HSI14_ON RCC_CR2_HSI14ON -#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) - -#define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ - -/** - * @} - */ - -#if defined(RCC_HSI48_SUPPORT) -/** @defgroup RCC_HSI48_Config HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF ((uint8_t)0x00U) -#define RCC_HSI48_ON ((uint8_t)0x01U) - -/** - * @} - */ -#endif /* RCC_HSI48_SUPPORT */ - -/** @defgroup RCC_PLL_Config PLL Config - * @{ - */ -#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ -#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ -#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ - -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor - * @{ - */ -#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 -#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 -#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 -#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 -#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 -#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 -#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 -#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 -#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 -#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 -#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 -#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 -#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 -#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 -#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 - -/** - * @} - */ - -/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor - * @{ - */ - -#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 -#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 -#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 -#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 -#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 -#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 -#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 -#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 -#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 -#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 -#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 -#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 -#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 -#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 -#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 -#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 - -/** - * @} - */ - - -/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source - * @{ - */ -#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK -#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK -#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE -#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI - -/** - * @} - */ - -/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source - * @{ - */ -#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI -#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK - -/** - * @} - */ -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 (0x00000000U) -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ - -/** - * @} - */ - -/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK -#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI -#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE -#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK -#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE -#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL -#define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14 - -/** - * @} - */ - -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ -#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ -#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ -#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ -#define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */ -#if defined(RCC_CIR_HSI48RDYF) -#define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */ -#endif -#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: XXXYYYYYb - * - YYYYY : Flag position in the register - * - XXX : Register index - * - 001: CR register - * - 010: CR2 register - * - 011: BDCR register - * - 0100: CSR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber)) -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber)) -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber)) -/* Flags in the CR2 register */ -#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber)) - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber)) -#if defined(RCC_CSR_V18PWRRSTF) -#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber)) -#endif -#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber)) -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */ -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */ -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */ - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable - * @brief Enable or disable the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) -#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) -#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) -#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) -#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) -#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) -#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) -/** - * @} - */ - - -/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) -#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) -#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) -#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) -#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) -#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset - * @brief Force or release AHB peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) -#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) - -#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) -#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) -#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) -#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) -#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) -#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) -#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) -#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) -#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) -/** - * @} - */ -/** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) -#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) - -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber) - -/** - * @} - */ - -/** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ - -/** @brief Macro to enable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - */ -#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) - -/** @brief Macro to disable the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) - -/** - * @} - */ - -/** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg @ref RCC_HSE_ON turn ON the HSE oscillator - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if ((__STATE__) == RCC_HSE_OFF) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - else if ((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - }while(0U) - -/** - * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. - * @note Predivision factor can not be changed if PLL is used as system clock - * In this case, you have to select another source of the system clock, disable the PLL and - * then change the HSE predivision factor. - * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. - * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. - */ -#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if ((__STATE__) == RCC_LSE_OFF) \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - else if ((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - }while(0U) - -/** - * @} - */ - -/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration - * @{ - */ - -/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14). - * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software - * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be - * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used. - * clock cycles. - */ -#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) - -/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14). - * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI14 can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI14. - * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) - -/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. - */ -#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) - -/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. - */ -#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) - -/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI14 RC. - * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value - * (default is RCC_HSI14CALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \ - MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER) -/** - * @} - */ - -/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config - * @{ - */ - -/** @brief Macro to configure the USART1 clock (USART1CLK). - * @param __USART1CLKSOURCE__ specifies the USART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock - */ -#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) - -/** @brief Macro to get the USART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock - */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) - -/** - * @} - */ - -/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config - * @{ - */ - -/** @brief Macro to configure the I2C1 clock (I2C1CLK). - * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) - -/** @brief Macro to get the I2C1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ - */ - -/** @brief Macro to enable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to disable the main PLL. - * @note The main PLL can not be disabled if it is used as system clock source - */ -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock - * This parameter can be one of the following values: - * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. - * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock - * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \ - do { \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ - } while(0U) - - -/** @brief Get oscillator clock selected as PLL input clock - * @retval The clock source used for PLL entry. The returned value can be one - * of the following: - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) - -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source Get Clock source - * @{ - */ - -/** - * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. - */ -#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) - -/** - * @} - */ - -/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - -#if defined(RCC_CFGR_MCOPRE) -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - @if STM32F042x6 - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F048xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F071xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F072xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F078xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F091xC - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F098xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F030x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F030xC - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F031x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F038xx - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F070x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F070xB - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @endif - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 - * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 - * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 - * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 - * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 - * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 - * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 - * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 - */ -#else -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source - */ -#endif -#if defined(RCC_CFGR_MCOPRE) -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) -#else - -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) - -#endif - -/** - * @} - */ - - /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ - -/** @brief Macro to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it cannot be changed unless the - * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * - * @param __RTC_CLKSOURCE__ specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, - * the RTC cannot be used in STOP and STANDBY modes. - * @note The system must always be configured so as to get a PCLK frequency greater than or - * equal to the RTCCLK frequency for a proper operation of the RTC. - */ -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - -/** @brief Macro to get the RTC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) - -/** @brief Macro to enable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -/** @brief Macro to disable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -/** @brief Macro to force the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_BDCR register. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -/** @brief Macros to release the Backup domain reset. - */ -#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) - -/** @brief Clear the RCC's interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - * @arg @ref RCC_IT_CSS Clock Security System interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - * @arg @ref RCC_IT_CSS Clock Security System interrupt - * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable - @if STM32F042x6 - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F048xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F071xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F072xB - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F078xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F091xC - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @elseif STM32F098xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - @endif - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags. - * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. - * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. - * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready - @if STM32F038xx - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F042x6 - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F048xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F058xx - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F071xB - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F072xB - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F078xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @elseif STM32F091xC - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - @elseif STM32F098xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready - * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain - @endif - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. - * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. - * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset - * @arg @ref RCC_FLAG_PINRST Pin reset. - * @arg @ref RCC_FLAG_PORRST POR/PDR reset. - * @arg @ref RCC_FLAG_SFTRST Software reset. - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. - * @arg @ref RCC_FLAG_LPWRRST Low Power reset. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ - (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \ - (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ - RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) - -/** - * @} - */ - -/** - * @} - */ - -/* Include RCC HAL Extension module */ -#include "stm32f0xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h deleted file mode 100644 index 4804e6e..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h +++ /dev/null @@ -1,2101 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_RCC_EX_H -#define __STM32F0xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @addtogroup RCC_Private_Macros - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) - -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) - -#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) - -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) - -#else - -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) - -#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#endif /* RCC_HSI48_SUPPORT */ - -#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI14)) - -#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI48)) - -#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI14)) - -#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Constants - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) - -/** @addtogroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV -#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV - -/** - * @} - */ - -/** @addtogroup RCC_Interrupt - * @{ - */ -#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -/** - * @} - */ - -/** @addtogroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) -/** - * @} - */ - -/** @addtogroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 -/** - * @} - */ - -/** @addtogroup RCC_System_Clock_Source_Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 -/** - * @} - */ - -#else -/** @addtogroup RCC_PLL_Clock_Source - * @{ - */ - -#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV -#else -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 -#endif - -/** - * @} - */ - -#endif /* RCC_HSI48_SUPPORT */ - -/** @addtogroup RCC_MCO_Clock_Source - * @{ - */ - -#if defined(RCC_CFGR_PLLNODIV) - -#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) - -#endif /* RCC_CFGR_PLLNODIV */ - -#if defined(RCC_CFGR_MCO_HSI48) - -#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 - -#endif /* SRCC_CFGR_MCO_HSI48 */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Private Constants -------------------------------------------------------------*/ -#if defined(CRS) -/** @addtogroup RCCEx_Private_Constants - * @{ - */ - -/* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) - -/* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) - -/** - * @} - */ -#endif /* CRS */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F030xC) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_RTC)) -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || - STM32F030xC */ - -#if defined(STM32F070x6) || defined(STM32F070xB) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_USB)) -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined(STM32F051x8) || defined(STM32F058xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) -#endif /* STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC)) -#endif /* STM32F071xB */ - -#if defined(STM32F072xB) || defined(STM32F078xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) -#endif /* STM32F072xB || STM32F078xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) - -#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ - ((SOURCE) == RCC_USBCLKSOURCE_PLL)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ - -#if defined(STM32F070x6) || defined(STM32F070xB) - -#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ - ((SOURCE) == RCC_USBCLKSOURCE_PLL)) - -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) -#endif /* STM32F091xC || STM32F098xx */ - - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_CECCLKSOURCE_LSE)) -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(RCC_CFGR_MCOPRE) - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ - ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ - ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ - ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) -#else - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) - -#endif /* RCC_CFGR_MCOPRE */ - -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) - -#if defined(CRS) - -#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) -#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) -#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ - ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) -#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) -#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) -#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) -#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ - ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) -#endif /* CRS */ -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief RCC extended clocks structure definition - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F030xC) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || - STM32F030xC */ - -#if defined(STM32F070x6) || defined(STM32F070xB) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t UsbClockSelection; /*!< USB clock source - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - - uint32_t UsbClockSelection; /*!< USB clock source - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined(STM32F051x8) || defined(STM32F058xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F071xB */ - -#if defined(STM32F072xB) || defined(STM32F078xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - - uint32_t UsbClockSelection; /*!< USB clock source - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F072xB || STM32F078xx */ - - -#if defined(STM32F091xC) || defined(STM32F098xx) -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCC_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t Usart3ClockSelection; /*!< USART3 clock source - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCC_I2C1_Clock_Source */ - - uint32_t CecClockSelection; /*!< HDMI CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -/** - * @brief RCC_CRS Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. - This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ - - uint32_t Source; /*!< Specifies the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ - - uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ - - uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. - It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) - This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ - - uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. - This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ - - uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ - -}RCC_CRSInitTypeDef; - -/** - * @brief RCC_CRS Synchronization structure definition - */ -typedef struct -{ - uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFFU */ - - uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3FU */ - - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter - value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFFU */ - - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. - It shows whether the actual frequency is below or above the target. - This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ - -}RCC_CRSSynchroInfoTypeDef; - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection - * @{ - */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F030xC) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_RTC (0x00010000U) - -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || - STM32F030xC */ - -#if defined(STM32F070x6) || defined(STM32F070xB) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USB (0x00020000U) - -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USB (0x00020000U) - -#endif /* STM32F042x6 || STM32F048xx */ - -#if defined(STM32F051x8) || defined(STM32F058xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) - -#endif /* STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_USART2 (0x00000002U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) - -#endif /* STM32F071xB */ - -#if defined(STM32F072xB) || defined(STM32F078xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_USART2 (0x00000002U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USB (0x00020000U) - -#endif /* STM32F072xB || STM32F078xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) -#define RCC_PERIPHCLK_USART1 (0x00000001U) -#define RCC_PERIPHCLK_USART2 (0x00000002U) -#define RCC_PERIPHCLK_I2C1 (0x00000020U) -#define RCC_PERIPHCLK_CEC (0x00000400U) -#define RCC_PERIPHCLK_RTC (0x00010000U) -#define RCC_PERIPHCLK_USART3 (0x00040000U) - -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) - -/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source - * @{ - */ -#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ -#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ - -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ - -#if defined(STM32F070x6) || defined(STM32F070xB) - -/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source - * @{ - */ -#define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ -#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ - -/** - * @} - */ - -#endif /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source - * @{ - */ -#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK -#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK -#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE -#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI - -/** - * @} - */ - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source - * @{ - */ -#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK -#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK -#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE -#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI - -/** - * @} - */ - -#endif /* STM32F091xC || STM32F098xx */ - - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source - * @{ - */ -#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 -#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE - -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler - * @{ - */ - -#if defined(RCC_CFGR_MCOPRE) - -#define RCC_MCODIV_1 (0x00000000U) -#define RCC_MCODIV_2 (0x10000000U) -#define RCC_MCODIV_4 (0x20000000U) -#define RCC_MCODIV_8 (0x30000000U) -#define RCC_MCODIV_16 (0x40000000U) -#define RCC_MCODIV_32 (0x50000000U) -#define RCC_MCODIV_64 (0x60000000U) -#define RCC_MCODIV_128 (0x70000000U) - -#else - -#define RCC_MCODIV_1 (0x00000000U) - -#endif /* RCC_CFGR_MCOPRE */ - -/** - * @} - */ - -/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration - * @{ - */ - -#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_CRS_Status RCCEx CRS Status - * @{ - */ -#define RCC_CRS_NONE (0x00000000U) -#define RCC_CRS_TIMEOUT (0x00000001U) -#define RCC_CRS_SYNCOK (0x00000002U) -#define RCC_CRS_SYNCWARN (0x00000004U) -#define RCC_CRS_SYNCERR (0x00000008U) -#define RCC_CRS_SYNCMISS (0x00000010U) -#define RCC_CRS_TRIMOVF (0x00000020U) - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source - * @{ - */ -#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ -#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider - * @{ - */ -#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ -#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity - * @{ - */ -#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value - * @{ - */ -#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value - * @{ - */ -#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye - * @{ - */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. - The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction - * @{ - */ -#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources - * @{ - */ -#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ -#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ -#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ -#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ -#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ -#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ -#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags - * @{ - */ -#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ -#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ -#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ -#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ -#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ -#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(GPIOD) - -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) - -#endif /* GPIOD */ - -#if defined(GPIOE) - -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) - -#endif /* GPIOE */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TSC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) - -#endif /* STM32F091xC || STM32F098xx */ - -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) - -#endif /* STM32F031x6 || STM32F038xx || */ - /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030x8) \ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) - -#endif /* STM32F030x8 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) - -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) - -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F072xB || STM32F078xx || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -#define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) - -#endif /* CRS */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_USART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) -#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) - -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - - -/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset - * @brief Forces or releases peripheral reset. - * @{ - */ - -/** @brief Force or release AHB peripheral reset. - */ -#if defined(GPIOD) - -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) - -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) - -#endif /* GPIOD */ - -#if defined(GPIOE) - -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) - -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) - -#endif /* GPIOE */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) - -#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -/** @brief Force or release APB1 peripheral reset. - */ -#if defined(STM32F030x8) \ - || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) - -#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) - -#endif /* STM32F031x6 || STM32F038xx || */ - /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030x8) \ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) - -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) - -#endif /* STM32F030x8 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) - -#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) - -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) - -#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) - -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) - -#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) - -#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F072xB || STM32F078xx || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) - -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) - -#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) - -#endif /* CRS */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) - -#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - - -/** @brief Force or release APB2 peripheral reset. - */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) - -#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) - -#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) -#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) - -#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) -#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) - -#endif /* STM32F091xC || STM32F098xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -/** @brief AHB Peripheral Clock Enable Disable Status - */ -#if defined(GPIOD) - -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) - -#endif /* GPIOD */ - -#if defined(GPIOE) - -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) - -#endif /* GPIOE */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) -#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx */ - -/** @brief APB1 Peripheral Clock Enable Disable Status - */ -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F030x8)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F031x6) || defined(STM32F038xx)\ - || defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) - -#endif /* STM32F031x6 || STM32F038xx || */ - /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F030x8) \ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) - -#endif /* STM32F030x8 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) -#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) - -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) - -#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) -#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F072xB || STM32F078xx || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) - -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(CRS) - -#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) -#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) - -#endif /* CRS */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) -#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -/** @brief APB1 Peripheral Clock Enable Disable Status - */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ - || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) - -#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ - /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - -#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) -#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - -#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) -#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) -#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) -#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) - -#endif /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - - -/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable - * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI48 can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI14. - * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software - * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be - * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. - * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator - * clock cycles. - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) - -#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) -#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) - -/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_HSI48_ON HSI48 enabled - * @arg @ref RCC_HSI48_OFF HSI48 disabled - */ -#define __HAL_RCC_GET_HSI48_STATE() \ - (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) - -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config - * @{ - */ -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F070x6) || defined(STM32F070xB) - -/** @brief Macro to configure the USB clock (USBCLK). - * @param __USBCLKSOURCE__ specifies the USB clock source. - * This parameter can be one of the following values: -@if STM32F070xB -@elseif STM32F070x6 -@else - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock -@endif - * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock - */ -#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) - -/** @brief Macro to get the USB clock source. - * @retval The clock source can be one of the following values: -@if STM32F070xB -@elseif STM32F070x6 -@else - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock -@endif - * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock - */ -#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F072xB || STM32F078xx || */ - /* STM32F070x6 || STM32F070xB */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - -/** @brief Macro to configure the CEC clock. - * @param __CECCLKSOURCE__ specifies the CEC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock - * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock - */ -#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) - -/** @brief Macro to get the HDMI CEC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock - * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock - */ -#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || defined(STM32F098xx) */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) -/** @brief Macro to configure the USART2 clock (USART2CLK). - * @param __USART2CLKSOURCE__ specifies the USART2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - */ -#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) - -/** @brief Macro to get the USART2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ - -#if defined(STM32F091xC) || defined(STM32F098xx) -/** @brief Macro to configure the USART3 clock (USART3CLK). - * @param __USART3CLKSOURCE__ specifies the USART3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - */ -#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) - -/** @brief Macro to get the USART3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) - -#endif /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - -/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. - * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. - * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. - * @retval None - */ -#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ - RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag - * @{ - */ -/* Interrupt & Flag management */ - -/** - * @brief Enable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) - -/** - * @brief Disable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) - -/** @brief Check whether the CRS interrupt has occurred or not. - * @param __INTERRUPT__ specifies the CRS interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** @brief Clear the CRS interrupt pending bits - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt - * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt - * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt - */ -#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ - } \ - } while(0U) - -/** - * @brief Check whether the specified CRS flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @retval The new state of _FLAG_ (TRUE or FALSE). - */ -#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the CRS specified FLAG. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR - * @retval None - */ -#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__FLAG__)); \ - } \ - } while(0U) - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features - * @{ - */ -/** - * @brief Enable the oscillator clock for frequency error counter. - * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Disable the oscillator clock for frequency error counter. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Enable the automatic hardware adjustement of TRIM bits. - * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Disable the automatic hardware adjustement of TRIM bits. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to - * reach the expected synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval None - */ -#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -/** - * @} - */ - -#if defined(CRS) - -/** @addtogroup RCCEx_Exported_Functions_Group3 - * @{ - */ - -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); -void HAL_RCCEx_CRS_IRQHandler(void); -void HAL_RCCEx_CRS_SyncOkCallback(void); -void HAL_RCCEx_CRS_SyncWarnCallback(void); -void HAL_RCCEx_CRS_ExpectedSyncCallback(void); -void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h deleted file mode 100644 index c1149b4..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h +++ /dev/null @@ -1,1830 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_TIM_H -#define __STM32F0xx_HAL_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - - -/** - * @brief TIM Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; - -/** - * @brief TIM Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -}TIM_SlaveConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -typedef struct -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref TIM_DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP (0x0000U) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 (0x0000U) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes - * @{ - */ -#define TIM_OCMODE_TIMING (0x0000U) -#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE (0x0000U) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH (0x0000U) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH (0x0000U) -#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 (0x0000U) -#define TIM_CHANNEL_2 (0x0004U) -#define TIM_CHANNEL_3 (0x0008U) -#define TIM_CHANNEL_4 (0x000CU) -#define TIM_CHANNEL_ALL (0x0018U) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_COM (TIM_DIER_COMIE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) -#define TIM_IT_BREAK (TIM_DIER_BIE) -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE (0x0000U) - -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_COM (TIM_DIER_COMDE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_COM (TIM_SR_COMIF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_BREAK (TIM_SR_BIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 (0x0000U) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF (0x0000U) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable - * @{ - */ -#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW (0x0000U) -#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) -/** - * @} - */ -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET (0x0000U) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave Mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE (0x0000U) -#define TIM_SLAVEMODE_RESET (0x0004U) -#define TIM_SLAVEMODE_GATED (0x0005U) -#define TIM_SLAVEMODE_TRIGGER (0x0006U) -#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) -#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 (0x0000U) -#define TIM_TS_ITR1 (0x0010U) -#define TIM_TS_ITR2 (0x0020U) -#define TIM_TS_ITR3 (0x0030U) -#define TIM_TS_TI1F_ED (0x0040U) -#define TIM_TS_TI1FP1 (0x0050U) -#define TIM_TS_TI2FP2 (0x0060U) -#define TIM_TS_ETRF (0x0070U) -#define TIM_TS_NONE (0xFFFFU) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 (0x0000U) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_OR (0x00000013) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) -/** - * @} - */ - -/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE (0x0001U) -#define TIM_CCx_DISABLE (0x0000U) -#define TIM_CCxN_ENABLE (0x0004U) -#define TIM_CCxN_DISABLE (0x0000U) -/** - * @} - */ - -/** - * @} - */ - -/* Private Constants -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ - -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) - -/** - * @} - */ - -/* Private Macros -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ - -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ - ((MODE) == TIM_COUNTERMODE_DOWN) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ - ((MODE) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ - ((MODE) == TIM_OCMODE_ACTIVE) || \ - ((MODE) == TIM_OCMODE_INACTIVE) || \ - ((MODE) == TIM_OCMODE_TOGGLE) || \ - ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) - -#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ - ((STATE) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ - ((STATE) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ - ((STATE) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3)) - -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) - -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ - ((MODE) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ - ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) - -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) - -#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_TRIGGER) || \ - ((FLAG) == TIM_FLAG_BREAK) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) - -#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ - ((STATE) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ - ((STATE) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ - ((LEVEL) == TIM_LOCKLEVEL_1) || \ - ((LEVEL) == TIM_LOCKLEVEL_2) || \ - ((LEVEL) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ - ((STATE) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ - ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) - -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ - ((MODE) == TIM_SLAVEMODE_GATED) || \ - ((MODE) == TIM_SLAVEMODE_RESET) || \ - ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ - ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) - -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_NONE)) - -#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ - ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ - ((BASE) == TIM_DMABASE_CR2) || \ - ((BASE) == TIM_DMABASE_SMCR) || \ - ((BASE) == TIM_DMABASE_DIER) || \ - ((BASE) == TIM_DMABASE_SR) || \ - ((BASE) == TIM_DMABASE_EGR) || \ - ((BASE) == TIM_DMABASE_CCMR1) || \ - ((BASE) == TIM_DMABASE_CCMR2) || \ - ((BASE) == TIM_DMABASE_CCER) || \ - ((BASE) == TIM_DMABASE_CNT) || \ - ((BASE) == TIM_DMABASE_PSC) || \ - ((BASE) == TIM_DMABASE_ARR) || \ - ((BASE) == TIM_DMABASE_RCR) || \ - ((BASE) == TIM_DMABASE_CCR1) || \ - ((BASE) == TIM_DMABASE_CCR2) || \ - ((BASE) == TIM_DMABASE_CCR3) || \ - ((BASE) == TIM_DMABASE_CCR4) || \ - ((BASE) == TIM_DMABASE_BDTR) || \ - ((BASE) == TIM_DMABASE_DCR) || \ - ((BASE) == TIM_DMABASE_OR)) - -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) - -/** @brief Set TIM IC prescaler - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @param __ICPSC__ specifies the prescaler value. - * @retval None - */ -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) - -/** @brief Reset TIM IC prescaler - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @retval None - */ -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - - -/** @brief Set TIM IC polarity - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @param __POLARITY__ specifies TIM Channel Polarity - * @retval None - */ -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U))) - -/** @brief Reset TIM IC polarity - * @param __HANDLE__ TIM handle - * @param __CHANNEL__ specifies TIM Channel - * @retval None - */ -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -/** - * @} - */ - -/* Private Functions --------------------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state - * @param __HANDLE__ TIM handle. - * @retval None - */ -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) -/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/* The Main Output Enable of a timer instance is disabled unconditionally */ -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled uncondiotionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** - * @brief Enables the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** - * @brief Enables the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** - * @brief Disables the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** - * @brief Checks whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clears the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Checks whether the specified TIM interrupt has occurred or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** - * @brief Clear the TIM interrupt pending bits - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** - * @brief Sets the TIM active prescaler register value on update event. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the active prescaler register new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Sets the TIM Capture Compare Register value on runtime without - * calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) - -/** - * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) - -/** - * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) - -/** - * @brief Sets the TIM Autoreload Register value on runtime without calling - * another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) - -/** - * @brief Sets the TIM Clock Division value on runtime without calling - * another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Sets the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) - -/** - * @brief Resets the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) - - -/** - * @brief Sets the TIM Input Capture prescaler on runtime without calling - * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * (+) Counter overflow/underflow - * (+) Setting the UG bit - * (+) Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) - -/** - * @brief Sets the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** - * @} - */ - -/* Include TIM HAL Extension module */ -#include "stm32f0xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 - * @{ - */ -/* Timer Output Compare functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 - * @{ - */ -/* Timer PWM functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 - * @{ - */ -/* Timer Input Capture functions ***********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 - * @{ - */ -/* Timer One Pulse functions ***************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 - * @{ - */ -/* Timer Encoder functions *****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 - * @{ - */ -/* Interrupt Handler functions **********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group8 - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group9 - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group10 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); - -/** - * @} - */ - -/** - * @} - */ - -/* Private Functions --------------------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h deleted file mode 100644 index 77125de..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h +++ /dev/null @@ -1,325 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_TIM_EX_H -#define __STM32F0xx_HAL_TIM_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal_def.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIMEx Exported Types - * @{ - */ - - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; - -/** - * @brief TIM Master configuration Structure definition - */ -typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ -}TIM_MasterConfigTypeDef; - -/** - * @brief TIM Break and Dead time configuration Structure definition - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIMEx Remap - * @{ - */ - -#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */ -#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */ -#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */ -#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */ -/** - * @} - */ - -/** @defgroup TIMEx_Clock_Clear_Input_Source TIMEx Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_NONE (0x00000000U) -#define TIM_CLEARINPUTSOURCE_ETR (0x00000001U) -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined (STM32F098xx) -#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x00000002U) -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || defined (STM32F098xx) */ -/** - * @} - */ - -/** - * @} - */ - -/* Private Macros -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\ - ((TIM_REMAP) == TIM_TIM14_RTC) ||\ - ((TIM_REMAP) == TIM_TIM14_HSE) ||\ - ((TIM_REMAP) == TIM_TIM14_MCO)) - -#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */ - -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined (STM32F098xx) -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR)) -#else -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || defined (STM32F098xx) */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 - * @{ - */ -/* Extension Callback *********************************************************/ -void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 - * @{ - */ -/* Extension Peripheral State functions **************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions -* @{ -*/ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -/** -* @} -*/ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F0xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h deleted file mode 100644 index 2aa2bb6..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h +++ /dev/null @@ -1,861 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_bus.h - * @author MCD Application Team - * @brief Header file of BUS LL module. - - @verbatim - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each LL_{BUS}_GRP{x}_EnableClock() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_BUS_H -#define __STM32F0xx_LL_BUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup BUS_LL BUS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants - * @{ - */ - -/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH - * @{ - */ -#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN -#if defined(DMA2) -#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN -#endif /*DMA2*/ -#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN -#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN -#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN -#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN -#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN -#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN -#if defined(GPIOD) -#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN -#endif /*GPIOD*/ -#if defined(GPIOE) -#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN -#endif /*GPIOE*/ -#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN -#if defined(TSC) -#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN -#endif /*TSC*/ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH - * @{ - */ -#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#if defined(TIM2) -#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN -#endif /*TIM2*/ -#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN -#if defined(TIM6) -#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN -#endif /*TIM6*/ -#if defined(TIM7) -#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN -#endif /*TIM7*/ -#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN -#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN -#if defined(SPI2) -#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN -#endif /*SPI2*/ -#if defined(USART2) -#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN -#endif /* USART2 */ -#if defined(USART3) -#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN -#endif /* USART3 */ -#if defined(USART4) -#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN -#endif /* USART4 */ -#if defined(USART5) -#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN -#endif /* USART5 */ -#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN -#if defined(I2C2) -#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN -#endif /*I2C2*/ -#if defined(USB) -#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN -#endif /* USB */ -#if defined(CAN) -#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN -#endif /*CAN*/ -#if defined(CRS) -#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN -#endif /*CRS*/ -#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN -#if defined(DAC) -#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN -#endif /*DAC*/ -#if defined(CEC) -#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN -#endif /*CEC*/ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH - * @{ - */ -#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU -#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN -#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN -#if defined(USART8) -#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN -#endif /*USART8*/ -#if defined(USART7) -#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN -#endif /*USART7*/ -#if defined(USART6) -#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN -#endif /*USART6*/ -#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN -#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN -#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN -#if defined(TIM15) -#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN -#endif /*TIM15*/ -#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN -#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN -#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions - * @{ - */ - -/** @defgroup BUS_LL_EF_AHB1 AHB1 - * @{ - */ - -/** - * @brief Enable AHB1 peripherals clock. - * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n - * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n - * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n - * AHBENR TSCEN LL_AHB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHBENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHBENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n - * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB1 peripherals clock. - * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n - * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n - * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n - * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n - * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n - * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n - * AHBENR TSCEN LL_AHB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBENR, Periphs); -} - -/** - * @brief Force AHB1 peripherals reset. - * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n - * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHBRSTR, Periphs); -} - -/** - * @brief Release AHB1 peripherals reset. - * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n - * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBRSTR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 - * @{ - */ - -/** - * @brief Enable APB1 peripherals clock (available in register 1). - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n - * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n - * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n - * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n - * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n - * APB1ENR CECEN LL_APB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB1 peripherals clock (available in register 1). - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n - * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n - * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n - * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n - * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n - * APB1ENR CECEN LL_APB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1ENR, Periphs); -} - -/** - * @brief Force APB1 peripherals reset (available in register 1). - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @brief Release APB1 peripherals reset (available in register 1). - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 - * @{ - */ - -/** - * @brief Enable APB1 peripherals clock (available in register 2). - * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n - * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n - * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n - * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not (available in register 2). - * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n - * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB1 peripherals clock (available in register 2). - * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n - * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n - * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n - * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2ENR, Periphs); -} - -/** - * @brief Force APB1 peripherals reset (available in register 2). - * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n - * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n - * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Release APB1 peripherals reset (available in register 2). - * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n - * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_BUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h deleted file mode 100644 index 2ae1b8f..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_cortex.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL CORTEX driver contains a set of generic APIs that can be - used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick - functions - (+) Low power mode configuration (SCB register of Cortex-MCU) - (+) API to access to MCU info (CPUID register) - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_CORTEX_H -#define __STM32F0xx_LL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -/** @defgroup CORTEX_LL CORTEX - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source - * @{ - */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK - * @{ - */ - -/** - * @brief This function checks if the Systick counter flag is active or not. - * @note It can be used in timeout function on application side. - * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); -} - -/** - * @brief Configures the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) -{ - if (Source == LL_SYSTICK_CLKSOURCE_HCLK) - { - SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } - else - { - CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } -} - -/** - * @brief Get the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - */ -__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) -{ - return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); -} - -/** - * @brief Enable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_EnableIT(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Disable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_DisableIT(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Checks if the SYSTICK interrupt is enabled or disabled. - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) -{ - return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE - * @{ - */ - -/** - * @brief Processor uses sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleep(void) -{ - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Processor uses deep sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) -{ - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. - * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an - * empty main application. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Do not sleep when returning to Thread mode. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the - * processor. - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) -{ - /* Set SEVEONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are - * excluded - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) -{ - /* Clear SEVEONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO - * @{ - */ - -/** - * @brief Get Implementer code - * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer - * @retval Value should be equal to 0x41 for ARM - */ -__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); -} - -/** - * @brief Get Variant number (The r value in the rnpn product revision identifier) - * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant - * @retval Value between 0 and 255 (0x0: revision 0) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); -} - -/** - * @brief Get Architecture number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture - * @retval Value should be equal to 0xC for Cortex-M0 devices - */ -__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); -} - -/** - * @brief Get Part number - * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo - * @retval Value should be equal to 0xC20 for Cortex-M0 - */ -__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); -} - -/** - * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) - * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision - * @retval Value between 0 and 255 (0x1: patch 1) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_CORTEX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h deleted file mode 100644 index 93358ce..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_crs.h +++ /dev/null @@ -1,799 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_crs.h - * @author MCD Application Team - * @brief Header file of CRS LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_CRS_H -#define __STM32F0xx_LL_CRS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(CRS) - -/** @defgroup CRS_LL CRS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants - * @{ - */ - -/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_CRS_ReadReg function - * @{ - */ -#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF -#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF -#define LL_CRS_ISR_ERRF CRS_ISR_ERRF -#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF -#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR -#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS -#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF -/** - * @} - */ - -/** @defgroup CRS_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions - * @{ - */ -#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE -#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE -#define LL_CRS_CR_ERRIE CRS_CR_ERRIE -#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider - * @{ - */ -#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ -#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source - * @{ - */ -#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ -#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity - * @{ - */ -#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ -#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction - * @{ - */ -#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ -#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values - * @{ - */ -/** - * @brief Reset value of the RELOAD field - * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz - * and a synchronization signal frequency of 1 kHz (SOF signal from USB) - */ -#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) - -/** - * @brief Reset value of Frequency error limit. - */ -#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) - -/** - * @brief Reset value of the HSI48 Calibration field - * @note The default value is 32, which corresponds to the middle of the trimming interval. - * The trimming step is around 67 kHz between two consecutive TRIM steps. - * A higher TRIM value corresponds to a higher output frequency - */ -#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros - * @{ - */ - -/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in CRS register - * @param __INSTANCE__ CRS Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in CRS register - * @param __INSTANCE__ CRS Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload - * @{ - */ - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between - * the target frequency and the frequency of the synchronization source after - * prescaling. It is then decreased by one in order to reach the expected - * synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval Reload value (in Hz) - */ -#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions - * @{ - */ - -/** @defgroup CRS_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable Frequency error counter - * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified - * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) -{ - SET_BIT(CRS->CR, CRS_CR_CEN); -} - -/** - * @brief Disable Frequency error counter - * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_CEN); -} - -/** - * @brief Check if Frequency error counter is enabled or not - * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); -} - -/** - * @brief Enable Automatic trimming counter - * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) -{ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); -} - -/** - * @brief Disable Automatic trimming counter - * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); -} - -/** - * @brief Check if Automatic trimming is enabled or not - * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); -} - -/** - * @brief Set HSI48 oscillator smooth trimming - * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only - * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming - * @param Value a number between Min_Data = 0 and Max_Data = 63 - * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) -{ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); -} - -/** - * @brief Get HSI48 oscillator smooth trimming - * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming - * @retval a number between Min_Data = 0 and Max_Data = 63 - */ -__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) -{ - return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); -} - -/** - * @brief Set counter reload value - * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter - * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF - * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT - * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); -} - -/** - * @brief Get counter reload value - * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter - * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); -} - -/** - * @brief Set frequency error limit - * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit - * @param Value a number between Min_Data = 0 and Max_Data = 255 - * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); -} - -/** - * @brief Get frequency error limit - * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit - * @retval A number between Min_Data = 0 and Max_Data = 255 - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); -} - -/** - * @brief Set division factor for SYNC signal - * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider - * @param Divider This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 - * @arg @ref LL_CRS_SYNC_DIV_2 - * @arg @ref LL_CRS_SYNC_DIV_4 - * @arg @ref LL_CRS_SYNC_DIV_8 - * @arg @ref LL_CRS_SYNC_DIV_16 - * @arg @ref LL_CRS_SYNC_DIV_32 - * @arg @ref LL_CRS_SYNC_DIV_64 - * @arg @ref LL_CRS_SYNC_DIV_128 - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); -} - -/** - * @brief Get division factor for SYNC signal - * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 - * @arg @ref LL_CRS_SYNC_DIV_2 - * @arg @ref LL_CRS_SYNC_DIV_4 - * @arg @ref LL_CRS_SYNC_DIV_8 - * @arg @ref LL_CRS_SYNC_DIV_16 - * @arg @ref LL_CRS_SYNC_DIV_32 - * @arg @ref LL_CRS_SYNC_DIV_64 - * @arg @ref LL_CRS_SYNC_DIV_128 - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); -} - -/** - * @brief Set SYNC signal source - * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO - * @arg @ref LL_CRS_SYNC_SOURCE_LSE - * @arg @ref LL_CRS_SYNC_SOURCE_USB - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); -} - -/** - * @brief Get SYNC signal source - * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO - * @arg @ref LL_CRS_SYNC_SOURCE_LSE - * @arg @ref LL_CRS_SYNC_SOURCE_USB - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); -} - -/** - * @brief Set input polarity for the SYNC signal source - * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_POLARITY_RISING - * @arg @ref LL_CRS_SYNC_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); -} - -/** - * @brief Get input polarity for the SYNC signal source - * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_POLARITY_RISING - * @arg @ref LL_CRS_SYNC_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); -} - -/** - * @brief Configure CRS for the synchronization - * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n - * CFGR RELOAD LL_CRS_ConfigSynchronization\n - * CFGR FELIM LL_CRS_ConfigSynchronization\n - * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n - * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n - * CFGR SYNCPOL LL_CRS_ConfigSynchronization - * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 - * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF - * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 - * @param Settings This parameter can be a combination of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 - * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB - * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) -{ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); - MODIFY_REG(CRS->CFGR, - CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, - ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_CRS_Management CRS_Management - * @{ - */ - -/** - * @brief Generate software SYNC event - * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Get the frequency error direction latched in the time of the last - * SYNC event - * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP - * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) -{ - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** - * @brief Get the frequency error counter value latched in the time of the last SYNC event - * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture - * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) -{ - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if SYNC event OK signal occurred or not - * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); -} - -/** - * @brief Check if SYNC warning signal occurred or not - * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); -} - -/** - * @brief Check if Synchronization or trimming error signal occurred or not - * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); -} - -/** - * @brief Check if Expected SYNC signal occurred or not - * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); -} - -/** - * @brief Check if SYNC error signal occurred or not - * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); -} - -/** - * @brief Check if SYNC missed error signal occurred or not - * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); -} - -/** - * @brief Check if Trimming overflow or underflow occurred or not - * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) -{ - return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); -} - -/** - * @brief Clear the SYNC event OK flag - * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); -} - -/** - * @brief Clear the SYNC warning flag - * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); -} - -/** - * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also - * the ERR flag - * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); -} - -/** - * @brief Clear Expected SYNC flag - * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable SYNC event OK interrupt - * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) -{ - SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); -} - -/** - * @brief Disable SYNC event OK interrupt - * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); -} - -/** - * @brief Check if SYNC event OK interrupt is enabled or not - * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); -} - -/** - * @brief Enable SYNC warning interrupt - * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) -{ - SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); -} - -/** - * @brief Disable SYNC warning interrupt - * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); -} - -/** - * @brief Check if SYNC warning interrupt is enabled or not - * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); -} - -/** - * @brief Enable Synchronization or trimming error interrupt - * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) -{ - SET_BIT(CRS->CR, CRS_CR_ERRIE); -} - -/** - * @brief Disable Synchronization or trimming error interrupt - * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); -} - -/** - * @brief Check if Synchronization or trimming error interrupt is enabled or not - * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); -} - -/** - * @brief Enable Expected SYNC interrupt - * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) -{ - SET_BIT(CRS->CR, CRS_CR_ESYNCIE); -} - -/** - * @brief Disable Expected SYNC interrupt - * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); -} - -/** - * @brief Check if Expected SYNC interrupt is enabled or not - * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) -{ - return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_CRS_DeInit(void); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(CRS) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_CRS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h deleted file mode 100644 index 4c60438..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_dma.h +++ /dev/null @@ -1,2224 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_dma.h - * @author MCD Application Team - * @brief Header file of DMA LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_DMA_H -#define __STM32F0xx_LL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (DMA1) || defined (DMA2) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Variables DMA Private Variables - * @{ - */ -/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ -static const uint8_t CHANNEL_OFFSET_TAB[] = -{ - (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), -#if defined(DMA1_Channel6) - (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), -#endif /*DMA1_Channel6*/ -#if defined(DMA1_Channel7) - (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) -#endif /*DMA1_Channel7*/ -}; -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Constants DMA Private Constants - * @{ - */ -/* Define used to get CSELR register offset */ -#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) - -/* Defines used for the bit position in the register and perform offsets */ -#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_Private_Macros DMA Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer - or as Source base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer - or as Destination base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_LL_EC_DIRECTION - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ - - uint32_t Mode; /*!< Specifies the normal or circular operation mode. - This parameter can be a value of @ref DMA_LL_EC_MODE - @note: The circular buffer mode cannot be used if the memory to memory - data transfer direction is configured on the selected Channel - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ - - uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_PERIPH - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ - - uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_MEMORY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ - - uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ - - uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ - - uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. - The data unit is equal to the source buffer configuration set in PeripheralSize - or MemorySize parameters depending in the transfer direction. - This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) - - uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMA_LL_EC_REQUEST - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ -#endif - - uint32_t Priority; /*!< Specifies the channel priority level. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ - -} LL_DMA_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants - * @{ - */ -/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_DMA_WriteReg function - * @{ - */ -#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ -#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ -#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ -#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ -#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ -#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ -#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ -#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ -#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ -#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ -#if defined(DMA1_Channel6) -#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ -#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ -#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ -#endif -#if defined(DMA1_Channel7) -#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ -#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ -#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ -#endif -/** - * @} - */ - -/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_DMA_ReadReg function - * @{ - */ -#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ -#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ -#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ -#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ -#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ -#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ -#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ -#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ -#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ -#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ -#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ -#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ -#if defined(DMA1_Channel6) -#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ -#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ -#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ -#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ -#endif -#if defined(DMA1_Channel7) -#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ -#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ -#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ -#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ -#endif -/** - * @} - */ - -/** @defgroup DMA_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions - * @{ - */ -#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ -#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ -#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CHANNEL CHANNEL - * @{ - */ -#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ -#if defined(DMA1_Channel6) -#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ -#endif -#if defined(DMA1_Channel7) -#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ -#endif -#if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ -#endif /*USE_FULL_LL_DRIVER*/ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction - * @{ - */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MODE Transfer mode - * @{ - */ -#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ -#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode - * @{ - */ -#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MEMORY Memory increment mode - * @{ - */ -#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment - * @{ - */ -#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ -#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ -#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment - * @{ - */ -#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ -#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ -#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level - * @{ - */ -#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ -#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ -#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ -/** - * @} - */ - -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) -/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request - * @{ - */ -#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ -#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ -#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ -#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ -#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ -#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ -#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ -#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ -#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ -#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ -#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ -#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ -#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ -#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ -#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ -#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ -/** - * @} - */ -#endif - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely - * @{ - */ -/** - * @brief Convert DMAx_Channely into DMAx - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval DMAx - */ -#if defined(DMA2) -#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) -#else -#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) -#endif - -/** - * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval LL_DMA_CHANNEL_y - */ -#if defined (DMA2) -#if defined (DMA2_Channel6) && defined (DMA2_Channel7) -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#else -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#endif -#else -#if defined (DMA1_Channel6) && defined (DMA1_Channel7) -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#elif defined (DMA1_Channel6) -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - LL_DMA_CHANNEL_6) -#else -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - LL_DMA_CHANNEL_5) -#endif /* DMA1_Channel6 && DMA1_Channel7 */ -#endif - -/** - * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely - * @param __DMA_INSTANCE__ DMAx - * @param __CHANNEL__ LL_DMA_CHANNEL_y - * @retval DMAx_Channely - */ -#if defined (DMA2) -#if defined (DMA2_Channel6) && defined (DMA2_Channel7) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ - DMA2_Channel7) -#else -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#endif -#else -#if defined (DMA1_Channel6) && defined (DMA1_Channel7) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#elif defined (DMA1_Channel6) -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - DMA1_Channel6) -#else -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - DMA1_Channel5) -#endif /* DMA1_Channel6 && DMA1_Channel7 */ -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable DMA channel. - * @rmtoll CCR EN LL_DMA_EnableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Disable DMA channel. - * @rmtoll CCR EN LL_DMA_DisableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Check if DMA channel is enabled or disabled. - * @rmtoll CCR EN LL_DMA_IsEnabledChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)); -} - -/** - * @brief Configure all parameters link to DMA transfer. - * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n - * CCR MEM2MEM LL_DMA_ConfigTransfer\n - * CCR CIRC LL_DMA_ConfigTransfer\n - * CCR PINC LL_DMA_ConfigTransfer\n - * CCR MINC LL_DMA_ConfigTransfer\n - * CCR PSIZE LL_DMA_ConfigTransfer\n - * CCR MSIZE LL_DMA_ConfigTransfer\n - * CCR PL LL_DMA_ConfigTransfer - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD - * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD - * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, - Configuration); -} - -/** - * @brief Set Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_SetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); -} - -/** - * @brief Get Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_GetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM)); -} - -/** - * @brief Set DMA mode circular or normal. - * @note The circular buffer mode cannot be used if the memory-to-memory - * data transfer is configured on the selected Channel. - * @rmtoll CCR CIRC LL_DMA_SetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, - Mode); -} - -/** - * @brief Get DMA mode circular or normal. - * @rmtoll CCR CIRC LL_DMA_GetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_CIRC)); -} - -/** - * @brief Set Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, - PeriphOrM2MSrcIncMode); -} - -/** - * @brief Get Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PINC)); -} - -/** - * @brief Set Memory increment mode. - * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, - MemoryOrM2MDstIncMode); -} - -/** - * @brief Get Memory increment mode. - * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MINC)); -} - -/** - * @brief Set Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, - PeriphOrM2MSrcDataSize); -} - -/** - * @brief Get Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PSIZE)); -} - -/** - * @brief Set Memory size. - * @rmtoll CCR MSIZE LL_DMA_SetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, - MemoryOrM2MDstDataSize); -} - -/** - * @brief Get Memory size. - * @rmtoll CCR MSIZE LL_DMA_GetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MSIZE)); -} - -/** - * @brief Set Channel priority level. - * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param Priority This parameter can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, - Priority); -} - -/** - * @brief Get Channel priority level. - * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PL)); -} - -/** - * @brief Set Number of data to transfer. - * @note This action has no effect if - * channel is enabled. - * @rmtoll CNDTR NDT LL_DMA_SetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT, NbData); -} - -/** - * @brief Get Number of data to transfer. - * @note Once the channel is enabled, the return value indicate the - * remaining bytes to be transmitted. - * @rmtoll CNDTR NDT LL_DMA_GetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT)); -} - -/** - * @brief Configure the Source and Destination addresses. - * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). - * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n - * CMAR MA LL_DMA_ConfigAddresses - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, - uint32_t DstAddress, uint32_t Direction) -{ - /* Direction Memory to Periph */ - if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); - } - /* Direction Periph to Memory and Memory to Memory */ - else - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); - } -} - -/** - * @brief Set the Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Set the Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); -} - -/** - * @brief Get Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CMAR MA LL_DMA_GetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -/** - * @brief Get Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CPAR PA LL_DMA_GetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Set the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); -} - -/** - * @brief Set the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Get the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Get the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) -/** - * @brief Set DMA request for DMA instance on Channel x. - * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. - * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n - * CSELR C2S LL_DMA_SetPeriphRequest\n - * CSELR C3S LL_DMA_SetPeriphRequest\n - * CSELR C4S LL_DMA_SetPeriphRequest\n - * CSELR C5S LL_DMA_SetPeriphRequest\n - * CSELR C6S LL_DMA_SetPeriphRequest\n - * CSELR C7S LL_DMA_SetPeriphRequest - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @param PeriphRequest This parameter can be one of the following values: - * @arg @ref LL_DMA_REQUEST_0 - * @arg @ref LL_DMA_REQUEST_1 - * @arg @ref LL_DMA_REQUEST_2 - * @arg @ref LL_DMA_REQUEST_3 - * @arg @ref LL_DMA_REQUEST_4 - * @arg @ref LL_DMA_REQUEST_5 - * @arg @ref LL_DMA_REQUEST_6 - * @arg @ref LL_DMA_REQUEST_7 - * @arg @ref LL_DMA_REQUEST_8 - * @arg @ref LL_DMA_REQUEST_9 - * @arg @ref LL_DMA_REQUEST_10 - * @arg @ref LL_DMA_REQUEST_11 - * @arg @ref LL_DMA_REQUEST_12 - * @arg @ref LL_DMA_REQUEST_13 - * @arg @ref LL_DMA_REQUEST_14 - * @arg @ref LL_DMA_REQUEST_15 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) -{ - MODIFY_REG(DMAx->CSELR, - DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); -} - -/** - * @brief Get DMA request for DMA instance on Channel x. - * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n - * CSELR C2S LL_DMA_GetPeriphRequest\n - * CSELR C3S LL_DMA_GetPeriphRequest\n - * CSELR C4S LL_DMA_GetPeriphRequest\n - * CSELR C5S LL_DMA_GetPeriphRequest\n - * CSELR C6S LL_DMA_GetPeriphRequest\n - * CSELR C7S LL_DMA_GetPeriphRequest - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_REQUEST_0 - * @arg @ref LL_DMA_REQUEST_1 - * @arg @ref LL_DMA_REQUEST_2 - * @arg @ref LL_DMA_REQUEST_3 - * @arg @ref LL_DMA_REQUEST_4 - * @arg @ref LL_DMA_REQUEST_5 - * @arg @ref LL_DMA_REQUEST_6 - * @arg @ref LL_DMA_REQUEST_7 - * @arg @ref LL_DMA_REQUEST_8 - * @arg @ref LL_DMA_REQUEST_9 - * @arg @ref LL_DMA_REQUEST_10 - * @arg @ref LL_DMA_REQUEST_11 - * @arg @ref LL_DMA_REQUEST_12 - * @arg @ref LL_DMA_REQUEST_13 - * @arg @ref LL_DMA_REQUEST_14 - * @arg @ref LL_DMA_REQUEST_15 - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(DMAx->CSELR, - DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); -} -#endif - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Channel 1 global interrupt flag. - * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); -} - -/** - * @brief Get Channel 2 global interrupt flag. - * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); -} - -/** - * @brief Get Channel 3 global interrupt flag. - * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); -} - -/** - * @brief Get Channel 4 global interrupt flag. - * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); -} - -/** - * @brief Get Channel 5 global interrupt flag. - * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 global interrupt flag. - * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 global interrupt flag. - * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); -} -#endif - -/** - * @brief Get Channel 1 transfer complete flag. - * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); -} - -/** - * @brief Get Channel 2 transfer complete flag. - * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); -} - -/** - * @brief Get Channel 3 transfer complete flag. - * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); -} - -/** - * @brief Get Channel 4 transfer complete flag. - * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); -} - -/** - * @brief Get Channel 5 transfer complete flag. - * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 transfer complete flag. - * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 transfer complete flag. - * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); -} -#endif - -/** - * @brief Get Channel 1 half transfer flag. - * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); -} - -/** - * @brief Get Channel 2 half transfer flag. - * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); -} - -/** - * @brief Get Channel 3 half transfer flag. - * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); -} - -/** - * @brief Get Channel 4 half transfer flag. - * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); -} - -/** - * @brief Get Channel 5 half transfer flag. - * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 half transfer flag. - * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 half transfer flag. - * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); -} -#endif - -/** - * @brief Get Channel 1 transfer error flag. - * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); -} - -/** - * @brief Get Channel 2 transfer error flag. - * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); -} - -/** - * @brief Get Channel 3 transfer error flag. - * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); -} - -/** - * @brief Get Channel 4 transfer error flag. - * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); -} - -/** - * @brief Get Channel 5 transfer error flag. - * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); -} - -#if defined(DMA1_Channel6) -/** - * @brief Get Channel 6 transfer error flag. - * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Get Channel 7 transfer error flag. - * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); -} -#endif - -/** - * @brief Clear Channel 1 global interrupt flag. - * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); -} - -/** - * @brief Clear Channel 2 global interrupt flag. - * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); -} - -/** - * @brief Clear Channel 3 global interrupt flag. - * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); -} - -/** - * @brief Clear Channel 4 global interrupt flag. - * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); -} - -/** - * @brief Clear Channel 5 global interrupt flag. - * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 global interrupt flag. - * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 global interrupt flag. - * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); -} -#endif - -/** - * @brief Clear Channel 1 transfer complete flag. - * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); -} - -/** - * @brief Clear Channel 2 transfer complete flag. - * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); -} - -/** - * @brief Clear Channel 3 transfer complete flag. - * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); -} - -/** - * @brief Clear Channel 4 transfer complete flag. - * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); -} - -/** - * @brief Clear Channel 5 transfer complete flag. - * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 transfer complete flag. - * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 transfer complete flag. - * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); -} -#endif - -/** - * @brief Clear Channel 1 half transfer flag. - * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); -} - -/** - * @brief Clear Channel 2 half transfer flag. - * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); -} - -/** - * @brief Clear Channel 3 half transfer flag. - * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); -} - -/** - * @brief Clear Channel 4 half transfer flag. - * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); -} - -/** - * @brief Clear Channel 5 half transfer flag. - * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 half transfer flag. - * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 half transfer flag. - * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); -} -#endif - -/** - * @brief Clear Channel 1 transfer error flag. - * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); -} - -/** - * @brief Clear Channel 2 transfer error flag. - * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); -} - -/** - * @brief Clear Channel 3 transfer error flag. - * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); -} - -/** - * @brief Clear Channel 4 transfer error flag. - * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); -} - -/** - * @brief Clear Channel 5 transfer error flag. - * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); -} - -#if defined(DMA1_Channel6) -/** - * @brief Clear Channel 6 transfer error flag. - * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); -} -#endif - -#if defined(DMA1_Channel7) -/** - * @brief Clear Channel 7 transfer error flag. - * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); -} -#endif - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_IT_Management IT_Management - * @{ - */ -/** - * @brief Enable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_EnableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Enable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_EnableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Enable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_EnableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Disable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_DisableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Disable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_DisableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Disable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_DisableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Check if Transfer complete Interrupt is enabled. - * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TCIE) == (DMA_CCR_TCIE)); -} - -/** - * @brief Check if Half transfer Interrupt is enabled. - * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_HTIE) == (DMA_CCR_HTIE)); -} - -/** - * @brief Check if Transfer error Interrupt is enabled. - * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TEIE) == (DMA_CCR_TEIE)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h deleted file mode 100644 index 7ef46fa..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_exti.h +++ /dev/null @@ -1,1032 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_exti.h - * @author MCD Application Team - * @brief Header file of EXTI LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_EXTI_H -#define __STM32F0xx_LL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private Macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure - * @{ - */ -typedef struct -{ - - uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 - This parameter can be any combination of @ref EXTI_LL_EC_LINE */ - - FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ - - uint8_t Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_MODE. */ - - uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ -} LL_EXTI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_LL_EC_LINE LINE - * @{ - */ -#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ -#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ -#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ -#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ -#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ -#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ -#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ -#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ -#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ -#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ -#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ -#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ -#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ -#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ -#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ -#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ -#if defined(EXTI_IMR_IM16) -#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ -#endif -#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ -#if defined(EXTI_IMR_IM18) -#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ -#endif -#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ -#if defined(EXTI_IMR_IM20) -#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ -#endif -#if defined(EXTI_IMR_IM21) -#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ -#endif -#if defined(EXTI_IMR_IM22) -#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ -#endif -#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ -#if defined(EXTI_IMR_IM24) -#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ -#endif -#if defined(EXTI_IMR_IM25) -#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ -#endif -#if defined(EXTI_IMR_IM26) -#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ -#endif -#if defined(EXTI_IMR_IM27) -#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ -#endif -#if defined(EXTI_IMR_IM28) -#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ -#endif -#if defined(EXTI_IMR_IM29) -#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ -#endif -#if defined(EXTI_IMR_IM30) -#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ -#endif -#if defined(EXTI_IMR_IM31) -#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ -#endif -#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ - - -#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ - -#if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup EXTI_LL_EC_MODE Mode - * @{ - */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger - * @{ - */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ - -/** - * @} - */ - - -#endif /*USE_FULL_LL_DRIVER*/ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in EXTI register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) - -/** - * @brief Read a value in EXTI register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) -/** - * @} - */ - - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ -/** @defgroup EXTI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->IMR, ExtiLine); -} - -/** - * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->IMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Event_Management Event_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->EMR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->EMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 - * @arg @ref LL_EXTI_LINE_25 - * @arg @ref LL_EXTI_LINE_26 - * @arg @ref LL_EXTI_LINE_27 - * @arg @ref LL_EXTI_LINE_28 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); - -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a Falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for the same interrupt line. - * In this case, both generate a trigger condition. - * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management - * @{ - */ - -/** - * @brief Generate a software Interrupt Event for Lines in range 0 to 31 - * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to - * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR - * resulting in an interrupt request generation. - * This bit is cleared by clearing the corresponding bit in the EXTI_PR - * register (by writing a 1 into the bit) - * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SWIER, ExtiLine); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management - * @{ - */ - -/** - * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); -} - - -/** - * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) -{ - return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); -} - - -/** - * @brief Clear ExtLine Flags for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_29 - * @arg @ref LL_EXTI_LINE_30 - * @arg @ref LL_EXTI_LINE_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->PR, ExtiLine); -} - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); -uint32_t LL_EXTI_DeInit(void); -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* EXTI */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_EXTI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h deleted file mode 100644 index 84c3fb5..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_gpio.h +++ /dev/null @@ -1,955 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_GPIO_H -#define __STM32F0xx_LL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) - -/** @defgroup GPIO_LL GPIO - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures - * @{ - */ - -/** - * @brief LL GPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_LL_EC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_MODE. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_SPEED. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ - - uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ - - uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_PULL. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ - - uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_AF. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ -} LL_GPIO_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_LL_EC_PIN PIN - * @{ - */ -#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ -#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ -#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ -#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ -#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ -#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ -#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ -#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ -#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ -#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ -#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ -#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ -#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ -#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ -#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ -#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ -#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ - GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ - GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ - GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ - GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ - GPIO_BSRR_BS_15) /*!< Select all pins */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_MODE Mode - * @{ - */ -#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ -#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ -#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ -#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_OUTPUT Output Type - * @{ - */ -#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ -#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_SPEED Output Speed - * @{ - */ -#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ -#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEEDR0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEEDR0 /*!< Select I/O high output speed */ -/** - * @} - */ -#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW -#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM -#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_HIGH - -/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down - * @{ - */ -#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ -#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ -#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_AF Alternate Function - * @{ - */ -#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @brief Configure gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_SetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0), ((Pin * Pin) * Mode)); -} - -/** - * @brief Return gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_GetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @param OutputType This parameter can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) -{ - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); -} - -/** - * @brief Return gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); -} - -/** - * @brief Configure gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Speed This parameter can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) -{ - MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0), ((Pin * Pin) * Speed)); -} - -/** - * @brief Return gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEEDR0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Pull This parameter can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) -{ - MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0), ((Pin * Pin) * Pull)); -} - -/** - * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPDR0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), - ((((Pin * Pin) * Pin) * Pin) * Alternate)); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * - (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); -} - - -/** - * @brief Lock configuration of several pins for a dedicated port. - * @note When the lock sequence has been applied on a port bit, the - * value of this port bit can no longer be modified until the - * next reset. - * @note Each lock bit freezes a specific configuration register - * (control and alternate function registers). - * @rmtoll LCKR LCKK LL_GPIO_LockPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - __IO uint32_t temp; - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - WRITE_REG(GPIOx->LCKR, PinMask); - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - temp = READ_REG(GPIOx->LCKR); - (void) temp; -} - -/** - * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. - * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); -} - -/** - * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. - * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked - * @param GPIOx GPIO Port - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) -{ - return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); -} - -/** - * @} - */ - -/** @defgroup GPIO_LL_EF_Data_Access Data Access - * @{ - */ - -/** - * @brief Return full input data register value for a dedicated port. - * @rmtoll IDR IDy LL_GPIO_ReadInputPort - * @param GPIOx GPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->IDR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll IDR IDy LL_GPIO_IsInputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); -} - -/** - * @brief Write output data register for the port. - * @rmtoll ODR ODy LL_GPIO_WriteOutputPort - * @param GPIOx GPIO Port - * @param PortValue Level value for each pin of the port - * @retval None - */ -__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) -{ - WRITE_REG(GPIOx->ODR, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @rmtoll ODR ODy LL_GPIO_ReadOutputPort - * @param GPIOx GPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->ODR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @rmtoll BSRR BSy LL_GPIO_SetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, PinMask); -} - -/** - * @brief Set several pins to low level on dedicated gpio port. - * @rmtoll BRR BRy LL_GPIO_ResetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BRR, PinMask); -} - -/** - * @brief Toggle data value for several pin of dedicated port. - * @rmtoll ODR ODy LL_GPIO_TogglePin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h deleted file mode 100644 index 02a4bf4..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_pwr.h +++ /dev/null @@ -1,568 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_pwr.h - * @author MCD Application Team - * @brief Header file of PWR LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_PWR_H -#define __STM32F0xx_LL_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(PWR) - -/** @defgroup PWR_LL PWR - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_PWR_WriteReg function - * @{ - */ -#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ -#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_PWR_ReadReg function - * @{ - */ -#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ -#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ -#if defined(PWR_PVD_SUPPORT) -#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ -#endif /* PWR_PVD_SUPPORT */ -#if defined(PWR_CSR_VREFINTRDYF) -#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ -#endif /* PWR_CSR_VREFINTRDYF */ -#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ -#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ -#if defined(PWR_CSR_EWUP3) -#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ -#endif /* PWR_CSR_EWUP3 */ -#if defined(PWR_CSR_EWUP4) -#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ -#endif /* PWR_CSR_EWUP4 */ -#if defined(PWR_CSR_EWUP5) -#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ -#endif /* PWR_CSR_EWUP5 */ -#if defined(PWR_CSR_EWUP6) -#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ -#endif /* PWR_CSR_EWUP6 */ -#if defined(PWR_CSR_EWUP7) -#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ -#endif /* PWR_CSR_EWUP7 */ -#if defined(PWR_CSR_EWUP8) -#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ -#endif /* PWR_CSR_EWUP8 */ -/** - * @} - */ - - -/** @defgroup PWR_LL_EC_MODE_PWR Mode Power - * @{ - */ -#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ -/** - * @} - */ - -#if defined(PWR_CR_LPDS) -/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode - * @{ - */ -#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ -/** - * @} - */ -#endif /* PWR_CR_LPDS */ - -#if defined(PWR_PVD_SUPPORT) -/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level - * @{ - */ -#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */ -#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */ -#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */ -#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */ -#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */ -#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */ -#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */ -#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */ -/** - * @} - */ -#endif /* PWR_PVD_SUPPORT */ -/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins - * @{ - */ -#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ -#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ -#if defined(PWR_CSR_EWUP3) -#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ -#endif /* PWR_CSR_EWUP3 */ -#if defined(PWR_CSR_EWUP4) -#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ -#endif /* PWR_CSR_EWUP4 */ -#if defined(PWR_CSR_EWUP5) -#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ -#endif /* PWR_CSR_EWUP5 */ -#if defined(PWR_CSR_EWUP6) -#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ -#endif /* PWR_CSR_EWUP6 */ -#if defined(PWR_CSR_EWUP7) -#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ -#endif /* PWR_CSR_EWUP7 */ -#if defined(PWR_CSR_EWUP8) -#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ -#endif /* PWR_CSR_EWUP8 */ -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in PWR register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) - -/** - * @brief Read a value in PWR register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable access to the backup domain - * @rmtoll CR DBP LL_PWR_EnableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Disable access to the backup domain - * @rmtoll CR DBP LL_PWR_DisableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Check if the backup domain is enabled - * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); -} - -#if defined(PWR_CR_LPDS) -/** - * @brief Set voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_SetRegulModeDS - * @param RegulMode This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) -{ - MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); -} - -/** - * @brief Get voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_GetRegulModeDS - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); -} -#endif /* PWR_CR_LPDS */ - -/** - * @brief Set Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_SetPowerMode\n - * @rmtoll CR LPDS LL_PWR_SetPowerMode - * @param PDMode This parameter can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STANDBY - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) -{ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); -} - -/** - * @brief Get Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_GetPowerMode\n - * @rmtoll CR LPDS LL_PWR_GetPowerMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STANDBY - */ -__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); -} - -#if defined(PWR_PVD_SUPPORT) -/** - * @brief Configure the voltage threshold detected by the Power Voltage Detector - * @rmtoll CR PLS LL_PWR_SetPVDLevel - * @param PVDLevel This parameter can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) -{ - MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); -} - -/** - * @brief Get the voltage threshold detection - * @rmtoll CR PLS LL_PWR_GetPVDLevel - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - */ -__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); -} - -/** - * @brief Enable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_EnablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Disable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_DisablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Check if Power Voltage Detector is enabled - * @rmtoll CR PVDE LL_PWR_IsEnabledPVD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); -} -#endif /* PWR_PVD_SUPPORT */ - -/** - * @brief Enable the WakeUp PINx functionality - * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * @arg @ref LL_PWR_WAKEUP_PIN4 (*) - * @arg @ref LL_PWR_WAKEUP_PIN5 (*) - * @arg @ref LL_PWR_WAKEUP_PIN6 (*) - * @arg @ref LL_PWR_WAKEUP_PIN7 (*) - * @arg @ref LL_PWR_WAKEUP_PIN8 (*) - * - * (*) not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) -{ - SET_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Disable the WakeUp PINx functionality - * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * @arg @ref LL_PWR_WAKEUP_PIN4 (*) - * @arg @ref LL_PWR_WAKEUP_PIN5 (*) - * @arg @ref LL_PWR_WAKEUP_PIN6 (*) - * @arg @ref LL_PWR_WAKEUP_PIN7 (*) - * @arg @ref LL_PWR_WAKEUP_PIN8 (*) - * - * (*) not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Check if the WakeUp PINx functionality is enabled - * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * @arg @ref LL_PWR_WAKEUP_PIN4 (*) - * @arg @ref LL_PWR_WAKEUP_PIN5 (*) - * @arg @ref LL_PWR_WAKEUP_PIN6 (*) - * @arg @ref LL_PWR_WAKEUP_PIN7 (*) - * @arg @ref LL_PWR_WAKEUP_PIN8 (*) - * - * (*) not available on all devices - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) -{ - return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); -} - - -/** - * @} - */ - -/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Wake-up Flag - * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); -} - -/** - * @brief Get Standby Flag - * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); -} - -#if defined(PWR_PVD_SUPPORT) -/** - * @brief Indicate whether VDD voltage is below the selected PVD threshold - * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); -} -#endif /* PWR_PVD_SUPPORT */ - -#if defined(PWR_CSR_VREFINTRDYF) -/** - * @brief Get Internal Reference VrefInt Flag - * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); -} -#endif /* PWR_CSR_VREFINTRDYF */ -/** - * @brief Clear Standby Flag - * @rmtoll CR CSBF LL_PWR_ClearFlag_SB - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) -{ - SET_BIT(PWR->CR, PWR_CR_CSBF); -} - -/** - * @brief Clear Wake-up Flags - * @rmtoll CR CWUF LL_PWR_ClearFlag_WU - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) -{ - SET_BIT(PWR->CR, PWR_CR_CWUF); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup PWR_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_PWR_DeInit(void); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(PWR) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h deleted file mode 100644 index 93f2327..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_rcc.h +++ /dev/null @@ -1,2257 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_rcc.h - * @author MCD Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_RCC_H -#define __STM32F0xx_LL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Constants RCC Private Constants - * @{ - */ -/* Defines used for the bit position in the register and perform offsets*/ -#define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_HSICAL (uint32_t)8U /*!< field position in register RCC_CR */ -#define RCC_POSITION_HSITRIM (uint32_t)3U /*!< field position in register RCC_CR */ -#define RCC_POSITION_HSI14TRIM (uint32_t)3U /*!< field position in register RCC_CR2 */ -#define RCC_POSITION_HSI14CAL (uint32_t)8U /*!< field position in register RCC_CR2 */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_POSITION_HSI48CAL (uint32_t)24U /*!< field position in register RCC_CR2 */ -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ -#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ -#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Private_Macros RCC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Exported_Types RCC Exported Types - * @{ - */ - -/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure - * @{ - */ - -/** - * @brief RCC Clocks Frequency Structure - */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ -} LL_RCC_ClocksTypeDef; - -/** - * @} - */ - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation - * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to - * HW set-up. - * @{ - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ -#if defined(RCC_HSI48_SUPPORT) - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ -#endif /* HSI48_VALUE */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_RCC_WriteReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ -#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ -#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ -#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ -#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ -#define LL_RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC /*!< HSI14 Ready Interrupt Clear */ -#if defined(RCC_HSI48_SUPPORT) -#define LL_RCC_CIR_HSI48RDYC RCC_CIR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ -#endif /* RCC_HSI48_SUPPORT */ -#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RCC_ReadReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ -#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#define LL_RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF /*!< HSI14 Ready Interrupt flag */ -#if defined(RCC_HSI48_SUPPORT) -#define LL_RCC_CIR_HSI48RDYF RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -#endif /* RCC_HSI48_SUPPORT */ -#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ -#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ -#if defined(RCC_CSR_V18PWRRSTF) -#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ -#endif /* RCC_CSR_V18PWRRSTF */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions - * @{ - */ -#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ -#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ -#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ -#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ -#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#define LL_RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE /*!< HSI14 Ready Interrupt Enable */ -#if defined(RCC_HSI48_SUPPORT) -#define LL_RCC_CIR_HSI48RDYIE RCC_CIR_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability - * @{ - */ -#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ -#if defined(RCC_CFGR_SW_HSI48) -#define LL_RCC_SYS_CLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 /*!< HSI48 selection as system clock */ -#endif /* RCC_CFGR_SW_HSI48 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -#if defined(RCC_CFGR_SWS_HSI48) -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 /*!< HSI48 used as system clock */ -#endif /* RCC_CFGR_SWS_HSI48 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler - * @{ - */ -#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) - * @{ - */ -#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection - * @{ - */ -#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ -#define LL_RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCOSEL_HSI14 /*!< HSI14 oscillator clock selected */ -#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ -#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ -#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ -#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ -#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ -#if defined(RCC_CFGR_MCOSEL_HSI48) -#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ -#endif /* RCC_CFGR_MCOSEL_HSI48 */ -#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ -#if defined(RCC_CFGR_PLLNODIV) -#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ -#endif /* RCC_CFGR_PLLNODIV */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler - * @{ - */ -#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ -#if defined(RCC_CFGR_MCOPRE) -#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ -#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ -#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ -#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ -#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ -#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ -#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ -#endif /* RCC_CFGR_MCOPRE */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency - * @{ - */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_PCLK) /*!< PCLK1 clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ -#if defined(RCC_CFGR3_USART2SW) -#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ -#endif /* RCC_CFGR3_USART2SW */ -#if defined(RCC_CFGR3_USART3SW) -#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ -#endif /* RCC_CFGR3_USART3SW */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI /*!< HSI oscillator clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /*!< System clock selected as I2C1 clock source */ -/** - * @} - */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ -#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ -/** - * @} - */ - -#endif /* CEC */ - -#if defined(USB) -/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection - * @{ - */ -#if defined(RCC_CFGR3_USBSW_HSI48) -#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 oscillator clock used as USB clock source */ -#else -#define LL_RCC_USB_CLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB Clock disabled */ -#endif /*RCC_CFGR3_USBSW_HSI48*/ -#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL selected as USB clock source */ -/** - * @} - */ - -#endif /* USB */ - -/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ -#if defined(RCC_CFGR3_USART2SW) -#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ -#endif /* RCC_CFGR3_USART2SW */ -#if defined(RCC_CFGR3_USART3SW) -#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ -#endif /* RCC_CFGR3_USART3SW */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ -/** - * @} - */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ -/** - * @} - */ -#endif /* CEC */ - -#if defined(USB) -/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source - * @{ - */ -#define LL_RCC_USB_CLKSOURCE RCC_CFGR3_USBSW /*!< USB Clock source selection */ -/** - * @} - */ -#endif /* USB */ - -/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection - * @{ - */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor - * @{ - */ -#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ -#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ -#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ -#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ -#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ -#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ -#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ -#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ -#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ -#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ -#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ -#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ -#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ -#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ -#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE - * @{ - */ -#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) -#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ -#if defined(RCC_CFGR_SW_HSI48) -#define LL_RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< HSI48/PREDIV clock selected as PLL entry clock source */ -#endif /* RCC_CFGR_SW_HSI48 */ -#else -#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor - * @{ - */ -#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ -#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ -#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ -#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ -#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ -#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ -#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ -#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ -#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ -#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ -#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ -#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ -#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ -#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ -#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ -#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RCC register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RCC register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) -/** - * @} - */ - -/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies - * @{ - */ - -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) -/** - * @brief Helper macro to calculate the PLLCLK frequency - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() - * , @ref LL_RCC_PLL_GetPrediv()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/HSI48) - * @param __PLLMUL__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @param __PLLPREDIV__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PREDIV_DIV_1 - * @arg @ref LL_RCC_PREDIV_DIV_2 - * @arg @ref LL_RCC_PREDIV_DIV_3 - * @arg @ref LL_RCC_PREDIV_DIV_4 - * @arg @ref LL_RCC_PREDIV_DIV_5 - * @arg @ref LL_RCC_PREDIV_DIV_6 - * @arg @ref LL_RCC_PREDIV_DIV_7 - * @arg @ref LL_RCC_PREDIV_DIV_8 - * @arg @ref LL_RCC_PREDIV_DIV_9 - * @arg @ref LL_RCC_PREDIV_DIV_10 - * @arg @ref LL_RCC_PREDIV_DIV_11 - * @arg @ref LL_RCC_PREDIV_DIV_12 - * @arg @ref LL_RCC_PREDIV_DIV_13 - * @arg @ref LL_RCC_PREDIV_DIV_14 - * @arg @ref LL_RCC_PREDIV_DIV_15 - * @arg @ref LL_RCC_PREDIV_DIV_16 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ - (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) - -#else -/** - * @brief Helper macro to calculate the PLLCLK frequency - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) - * @param __PLLMUL__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ - ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -/** - * @brief Helper macro to calculate the HCLK frequency - * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler - * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) - * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval HCLK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) - -/** - * @brief Helper macro to calculate the PCLK1 frequency (ABP1) - * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler - * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval PCLK1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos]) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_LL_EF_HSE HSE - * @{ - */ - -/** - * @brief Enable the Clock Security System. - * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Disable the Clock Security System. - * @note Cannot be disabled in HSE is ready (only by hardware) - * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Disable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI HSI - * @{ - */ - -/** - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Disable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); -} - -/** - * @brief Get HSI Calibration value - * @note When HSITRIM is written, HSICAL is updated with the sum of - * HSITRIM and the factory trim value - * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); -} - -/** - * @brief Set HSI Calibration trimming - * @note user-programmable trimming value that is added to the HSICAL - * @note Default value is 16, which, when added to the HSICAL value, - * should trim the HSI to 16 MHz +/- 1 % - * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming - * @param Value between Min_Data = 0x00 and Max_Data = 0x1F - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); -} - -/** - * @brief Get HSI Calibration trimming - * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming - * @retval Between Min_Data = 0x00 and Max_Data = 0x1F - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); -} - -/** - * @} - */ - -#if defined(RCC_HSI48_SUPPORT) -/** @defgroup RCC_LL_EF_HSI48 HSI48 - * @{ - */ - -/** - * @brief Enable HSI48 - * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI48_Enable(void) -{ - SET_BIT(RCC->CR2, RCC_CR2_HSI48ON); -} - -/** - * @brief Disable HSI48 - * @rmtoll CR2 HSI48ON LL_RCC_HSI48_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI48_Disable(void) -{ - CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON); -} - -/** - * @brief Check if HSI48 oscillator Ready - * @rmtoll CR2 HSI48RDY LL_RCC_HSI48_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) -{ - return (READ_BIT(RCC->CR2, RCC_CR2_HSI48RDY) == (RCC_CR2_HSI48RDY)); -} - -/** - * @brief Get HSI48 Calibration value - * @rmtoll CR2 HSI48CAL LL_RCC_HSI48_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48CAL) >> RCC_POSITION_HSI48CAL); -} - -/** - * @} - */ - -#endif /* RCC_HSI48_SUPPORT */ - -/** @defgroup RCC_LL_EF_HSI14 HSI14 - * @{ - */ - -/** - * @brief Enable HSI14 - * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_Enable(void) -{ - SET_BIT(RCC->CR2, RCC_CR2_HSI14ON); -} - -/** - * @brief Disable HSI14 - * @rmtoll CR2 HSI14ON LL_RCC_HSI14_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_Disable(void) -{ - CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON); -} - -/** - * @brief Check if HSI14 oscillator Ready - * @rmtoll CR2 HSI14RDY LL_RCC_HSI14_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI14_IsReady(void) -{ - return (READ_BIT(RCC->CR2, RCC_CR2_HSI14RDY) == (RCC_CR2_HSI14RDY)); -} - -/** - * @brief ADC interface can turn on the HSI14 oscillator - * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_EnableADCControl - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_EnableADCControl(void) -{ - CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS); -} - -/** - * @brief ADC interface can not turn on the HSI14 oscillator - * @rmtoll CR2 HSI14DIS LL_RCC_HSI14_DisableADCControl - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_DisableADCControl(void) -{ - SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS); -} - -/** - * @brief Set HSI14 Calibration trimming - * @note user-programmable trimming value that is added to the HSI14CAL - * @note Default value is 16, which, when added to the HSI14CAL value, - * should trim the HSI14 to 14 MHz +/- 1 % - * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_SetCalibTrimming - * @param Value between Min_Data = 0x00 and Max_Data = 0xFF - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI14_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, Value << RCC_POSITION_HSI14TRIM); -} - -/** - * @brief Get HSI14 Calibration value - * @note When HSI14TRIM is written, HSI14CAL is updated with the sum of - * HSI14TRIM and the factory trim value - * @rmtoll CR2 HSI14TRIM LL_RCC_HSI14_GetCalibTrimming - * @retval Between Min_Data = 0x00 and Max_Data = 0x1F - */ -__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14TRIM) >> RCC_POSITION_HSI14TRIM); -} - -/** - * @brief Get HSI14 Calibration trimming - * @rmtoll CR2 HSI14CAL LL_RCC_HSI14_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0x1F - */ -__STATIC_INLINE uint32_t LL_RCC_HSI14_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI14CAL) >> RCC_POSITION_HSI14CAL); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSE LSE - * @{ - */ - -/** - * @brief Enable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Disable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Enable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Disable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Set LSE oscillator drive capability - * @note The oscillator is in Xtal mode when it is not in bypass mode. - * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability - * @param LSEDrive This parameter can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); -} - -/** - * @brief Get LSE oscillator drive capability - * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_HIGH - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); -} - -/** - * @brief Check if LSE oscillator Ready - * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSI LSI - * @{ - */ - -/** - * @brief Enable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Enable(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Disable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Disable(void) -{ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Check if LSI is Ready - * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_System System - * @{ - */ - -/** - * @brief Configure the system clock source - * @rmtoll CFGR SW LL_RCC_SetSysClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI48 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); -} - -/** - * @brief Get the system clock source - * @rmtoll CFGR SWS LL_RCC_GetSysClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); -} - -/** - * @brief Set AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); -} - -/** - * @brief Set APB1 prescaler - * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); -} - -/** - * @brief Get AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); -} - -/** - * @brief Get APB1 prescaler - * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MCO MCO - * @{ - */ - -/** - * @brief Configure MCOx - * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n - * CFGR MCOPRE LL_RCC_ConfigMCO\n - * CFGR PLLNODIV LL_RCC_ConfigMCO - * @param MCOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK - * @arg @ref LL_RCC_MCO1SOURCE_HSI14 - * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_LSI - * @arg @ref LL_RCC_MCO1SOURCE_LSE - * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 - * - * (*) value not defined in all devices - * @param MCOxPrescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_DIV_1 - * @arg @ref LL_RCC_MCO1_DIV_2 (*) - * @arg @ref LL_RCC_MCO1_DIV_4 (*) - * @arg @ref LL_RCC_MCO1_DIV_8 (*) - * @arg @ref LL_RCC_MCO1_DIV_16 (*) - * @arg @ref LL_RCC_MCO1_DIV_32 (*) - * @arg @ref LL_RCC_MCO1_DIV_64 (*) - * @arg @ref LL_RCC_MCO1_DIV_128 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) -{ -#if defined(RCC_CFGR_MCOPRE) -#if defined(RCC_CFGR_PLLNODIV) - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); -#else - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); -#endif /* RCC_CFGR_PLLNODIV */ -#else - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); -#endif /* RCC_CFGR_MCOPRE */ -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source - * @{ - */ - -/** - * @brief Configure USARTx clock source - * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n - * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n - * CFGR3 USART3SW LL_RCC_SetUSARTClockSource - * @param USARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) -{ - MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); -} - -/** - * @brief Configure I2Cx clock source - * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource - * @param I2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) -{ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, I2CxSource); -} - -#if defined(CEC) -/** - * @brief Configure CEC clock source - * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource - * @param CECxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) -{ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); -} -#endif /* CEC */ - -#if defined(USB) -/** - * @brief Configure USB clock source - * @rmtoll CFGR3 USBSW LL_RCC_SetUSBClockSource - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) -{ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, USBxSource); -} -#endif /* USB */ - -/** - * @brief Get USARTx clock source - * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n - * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n - * CFGR3 USART3SW LL_RCC_GetUSARTClockSource - * @param USARTx This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE (*) - * - * (*) value not defined in all devices. - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); -} - -/** - * @brief Get I2Cx clock source - * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource - * @param I2Cx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx)); -} - -#if defined(CEC) -/** - * @brief Get CEC clock source - * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource - * @param CECx This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); -} -#endif /* CEC */ - -#if defined(USB) -/** - * @brief Get USBx clock source - * @rmtoll CFGR3 USBSW LL_RCC_GetUSBClockSource - * @param USBx This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, USBx)); -} -#endif /* USB */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_RTC RTC - * @{ - */ - -/** - * @brief Set RTC Clock Source - * @note Once the RTC clock source has been selected, it cannot be changed any more unless - * the Backup domain is reset. The BDRST bit can be used to reset them. - * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); -} - -/** - * @brief Get RTC Clock Source - * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); -} - -/** - * @brief Enable RTC - * @rmtoll BDCR RTCEN LL_RCC_EnableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableRTC(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Disable RTC - * @rmtoll BDCR RTCEN LL_RCC_DisableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableRTC(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Check if RTC has been enabled or not - * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); -} - -/** - * @brief Force the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Release the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLL PLL - * @{ - */ - -/** - * @brief Enable PLL - * @rmtoll CR PLLON LL_RCC_PLL_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Disable PLL - * @note Cannot be disabled if the PLL clock is used as the system clock - * @rmtoll CR PLLON LL_RCC_PLL_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Check if PLL Ready - * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); -} - -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) -/** - * @brief Configure PLL used for SYSCLK Domain - * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) - * - * (*) value not defined in all devices - * @param PLLMul This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @param PLLDiv This parameter can be one of the following values: - * @arg @ref LL_RCC_PREDIV_DIV_1 - * @arg @ref LL_RCC_PREDIV_DIV_2 - * @arg @ref LL_RCC_PREDIV_DIV_3 - * @arg @ref LL_RCC_PREDIV_DIV_4 - * @arg @ref LL_RCC_PREDIV_DIV_5 - * @arg @ref LL_RCC_PREDIV_DIV_6 - * @arg @ref LL_RCC_PREDIV_DIV_7 - * @arg @ref LL_RCC_PREDIV_DIV_8 - * @arg @ref LL_RCC_PREDIV_DIV_9 - * @arg @ref LL_RCC_PREDIV_DIV_10 - * @arg @ref LL_RCC_PREDIV_DIV_11 - * @arg @ref LL_RCC_PREDIV_DIV_12 - * @arg @ref LL_RCC_PREDIV_DIV_13 - * @arg @ref LL_RCC_PREDIV_DIV_14 - * @arg @ref LL_RCC_PREDIV_DIV_15 - * @arg @ref LL_RCC_PREDIV_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); -} - -#else - -/** - * @brief Configure PLL used for SYSCLK Domain - * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n - * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 - * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 - * @param PLLMul This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); -} -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI (*) - * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); -} - -/** - * @brief Get PLL multiplication Factor - * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL_MUL_2 - * @arg @ref LL_RCC_PLL_MUL_3 - * @arg @ref LL_RCC_PLL_MUL_4 - * @arg @ref LL_RCC_PLL_MUL_5 - * @arg @ref LL_RCC_PLL_MUL_6 - * @arg @ref LL_RCC_PLL_MUL_7 - * @arg @ref LL_RCC_PLL_MUL_8 - * @arg @ref LL_RCC_PLL_MUL_9 - * @arg @ref LL_RCC_PLL_MUL_10 - * @arg @ref LL_RCC_PLL_MUL_11 - * @arg @ref LL_RCC_PLL_MUL_12 - * @arg @ref LL_RCC_PLL_MUL_13 - * @arg @ref LL_RCC_PLL_MUL_14 - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); -} - -/** - * @brief Get PREDIV division factor for the main PLL - * @note They can be written only when the PLL is disabled - * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PREDIV_DIV_1 - * @arg @ref LL_RCC_PREDIV_DIV_2 - * @arg @ref LL_RCC_PREDIV_DIV_3 - * @arg @ref LL_RCC_PREDIV_DIV_4 - * @arg @ref LL_RCC_PREDIV_DIV_5 - * @arg @ref LL_RCC_PREDIV_DIV_6 - * @arg @ref LL_RCC_PREDIV_DIV_7 - * @arg @ref LL_RCC_PREDIV_DIV_8 - * @arg @ref LL_RCC_PREDIV_DIV_9 - * @arg @ref LL_RCC_PREDIV_DIV_10 - * @arg @ref LL_RCC_PREDIV_DIV_11 - * @arg @ref LL_RCC_PREDIV_DIV_12 - * @arg @ref LL_RCC_PREDIV_DIV_13 - * @arg @ref LL_RCC_PREDIV_DIV_14 - * @arg @ref LL_RCC_PREDIV_DIV_15 - * @arg @ref LL_RCC_PREDIV_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Clear LSI ready interrupt flag - * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); -} - -/** - * @brief Clear LSE ready interrupt flag - * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); -} - -/** - * @brief Clear HSI ready interrupt flag - * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); -} - -/** - * @brief Clear HSE ready interrupt flag - * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); -} - -/** - * @brief Clear PLL ready interrupt flag - * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); -} - -/** - * @brief Clear HSI14 ready interrupt flag - * @rmtoll CIR HSI14RDYC LL_RCC_ClearFlag_HSI14RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSI14RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYC); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Clear HSI48 ready interrupt flag - * @rmtoll CIR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYC); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Clear Clock security system interrupt flag - * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_CSSC); -} - -/** - * @brief Check if LSI ready interrupt occurred or not - * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); -} - -/** - * @brief Check if LSE ready interrupt occurred or not - * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); -} - -/** - * @brief Check if HSI ready interrupt occurred or not - * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); -} - -/** - * @brief Check if HSE ready interrupt occurred or not - * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); -} - -/** - * @brief Check if PLL ready interrupt occurred or not - * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); -} - -/** - * @brief Check if HSI14 ready interrupt occurred or not - * @rmtoll CIR HSI14RDYF LL_RCC_IsActiveFlag_HSI14RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI14RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYF) == (RCC_CIR_HSI14RDYF)); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Check if HSI48 ready interrupt occurred or not - * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYF) == (RCC_CIR_HSI48RDYF)); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); -} - -/** - * @brief Check if RCC flag Independent Watchdog reset is set or not. - * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); -} - -/** - * @brief Check if RCC flag Low Power reset is set or not. - * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); -} - -/** - * @brief Check if RCC flag is set or not. - * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); -} - -/** - * @brief Check if RCC flag Pin reset is set or not. - * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); -} - -/** - * @brief Check if RCC flag POR/PDR reset is set or not. - * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); -} - -/** - * @brief Check if RCC flag Software reset is set or not. - * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); -} - -/** - * @brief Check if RCC flag Window Watchdog reset is set or not. - * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); -} - -#if defined(RCC_CSR_V18PWRRSTF) -/** - * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. - * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); -} -#endif /* RCC_CSR_V18PWRRSTF */ - -/** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearResetFlags(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Enable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Enable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Enable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Enable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -/** - * @brief Enable HSI14 ready interrupt - * @rmtoll CIR HSI14RDYIE LL_RCC_EnableIT_HSI14RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSI14RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Enable HSI48 ready interrupt - * @rmtoll CIR HSI48RDYIE LL_RCC_EnableIT_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Disable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Disable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Disable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Disable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Disable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -/** - * @brief Disable HSI14 ready interrupt - * @rmtoll CIR HSI14RDYIE LL_RCC_DisableIT_HSI14RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSI14RDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Disable HSI48 ready interrupt - * @rmtoll CIR HSI48RDYIE LL_RCC_DisableIT_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @brief Checks if LSI ready interrupt source is enabled or disabled. - * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); -} - -/** - * @brief Checks if LSE ready interrupt source is enabled or disabled. - * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); -} - -/** - * @brief Checks if HSI ready interrupt source is enabled or disabled. - * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); -} - -/** - * @brief Checks if HSE ready interrupt source is enabled or disabled. - * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); -} - -/** - * @brief Checks if PLL ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); -} - -/** - * @brief Checks if HSI14 ready interrupt source is enabled or disabled. - * @rmtoll CIR HSI14RDYIE LL_RCC_IsEnabledIT_HSI14RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI14RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI14RDYIE) == (RCC_CIR_HSI14RDYIE)); -} - -#if defined(RCC_HSI48_SUPPORT) -/** - * @brief Checks if HSI48 ready interrupt source is enabled or disabled. - * @rmtoll CIR HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSI48RDYIE) == (RCC_CIR_HSI48RDYIE)); -} -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_RCC_DeInit(void); -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions - * @{ - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); -uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); -#if defined(USB_OTG_FS) || defined(USB) -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); -#endif /* USB_OTG_FS || USB */ -#if defined(CEC) -uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); -#endif /* CEC */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* RCC */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h deleted file mode 100644 index 7eecd25..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h +++ /dev/null @@ -1,1868 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_system.h - * @author MCD Application Team - * @brief Header file of SYSTEM LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL SYSTEM driver contains a set of generic APIs that can be - used by user: - (+) Some of the FLASH features need to be handled in the SYSTEM file. - (+) Access to DBGCMU registers - (+) Access to SYSCFG registers - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_SYSTEM_H -#define __STM32F0xx_LL_SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) - -/** @defgroup SYSTEM_LL SYSTEM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - -/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap -* @{ -*/ -#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ -/** - * @} - */ - -#if defined(SYSCFG_CFGR1_IR_MOD) -/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation - * @{ - */ -#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< Timer16 is selected as IR Modulation enveloppe source */ -#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< USART1 is selected as IR Modulation enveloppe source */ -#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< USART4 is selected as IR Modulation enveloppe source */ -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_IR_MOD */ - -#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap - * @{ - */ -#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP) -#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_TX DMA request mapped on DMA channel 2U */ -#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1_TX DMA request mapped on DMA channel 4U */ -#endif /*SYSCFG_CFGR1_USART1TX_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP) -#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART1_RX DMA request mapped on DMA channel 3U */ -#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1_RX DMA request mapped on DMA channel 5 */ -#endif /*SYSCFG_CFGR1_USART1RX_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_USART2_DMA_RMP) -#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively */ -#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ -#endif /*SYSCFG_CFGR1_USART2_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_USART3_DMA_RMP) -#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively */ -#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) | SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively */ -#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */ -/** - * @} - */ -#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ - -#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap - * @{ - */ -#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively */ -#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /*!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively */ -/** - * @} - */ - -#endif /*SYSCFG_CFGR1_SPI2_DMA_RMP*/ - -#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap - * @{ - */ -#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively */ -#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /*!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively */ -/** - * @} - */ - -#endif /*SYSCFG_CFGR1_I2C1_DMA_RMP*/ - -#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap - * @{ - */ -#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /*!< ADC DMA request mapped on DMA channel 1U */ -#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /*!< ADC DMA request mapped on DMA channel 2U */ -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) -/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap - * @{ - */ -#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) -#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2) -#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ -#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP | SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ -#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 */ -#else -#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 */ -#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 */ -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */ -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */ -#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP) -#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2) -#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ -#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP | SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ -#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 */ -#else -#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 */ -#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 */ -#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */ -#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */ -#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP) -#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively */ -#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ -#endif /*SYSCFG_CFGR1_TIM1_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP) -#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively */ -#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ -#endif /*SYSCFG_CFGR1_TIM2_DMA_RMP*/ -#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP) -#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | (uint32_t)0x00000000U) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 */ -#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) | SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 */ -#endif /*SYSCFG_CFGR1_TIM3_DMA_RMP*/ -/** - * @} - */ - -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ - -/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS - * @{ - */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< I2C PB6 Fast mode plus */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< I2C PB7 Fast mode plus */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< I2C PB8 Fast mode plus */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< I2C PB9 Fast mode plus */ -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ -#endif /*SYSCFG_CFGR1_I2C_FMP_I2C1*/ -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable I2C2 Fast mode plus */ -#endif /*SYSCFG_CFGR1_I2C_FMP_I2C2*/ -#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) -#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ -#endif /*SYSCFG_CFGR1_I2C_FMP_PA9*/ -#if defined(SYSCFG_CFGR1_I2C_FMP_PA10) -#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ -#endif /*SYSCFG_CFGR1_I2C_FMP_PA10*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT - * @{ - */ -#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */ -#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */ -#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */ -#if defined(GPIOD_BASE) -#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */ -#endif /*GPIOD_BASE*/ -#if defined(GPIOE_BASE) -#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */ -#endif /*GPIOE_BASE*/ -#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE - * @{ - */ -#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK - * @{ - */ -#if defined(SYSCFG_CFGR2_PVD_LOCK) -#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection - with TIM1/15/16U/17 Break Input and also - the PVDE and PLS bits of the Power Control Interface */ -#endif /*SYSCFG_CFGR2_PVD_LOCK*/ -#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal - with Break Input of TIM1/15/16/17 */ -#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of - CortexM0 with Break Input of TIM1/15/16/17 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP - * @{ - */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_TIM2_STOP*/ -#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_TIM6_STOP*/ -#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/ -#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ -#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP - * @{ - */ -#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ -#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) -#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ -#endif /*DBGMCU_APB2_FZ_DBG_TIM15_STOP*/ -#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY - * @{ - */ -#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ -#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions - * @{ - */ - -/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG - * @{ - */ - -/** - * @brief Set memory mapping at address 0x00000000 - * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory - * @param Memory This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); -} - -/** - * @brief Get memory mapping at address 0x00000000 - * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); -} - -#if defined(SYSCFG_CFGR1_IR_MOD) -/** - * @brief Set IR Modulation Envelope signal source. - * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_IR_MOD_TIM16 - * @arg @ref LL_SYSCFG_IR_MOD_USART1 - * @arg @ref LL_SYSCFG_IR_MOD_USART4 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source); -} - -/** - * @brief Get IR Modulation Envelope signal source. - * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_IR_MOD_TIM16 - * @arg @ref LL_SYSCFG_IR_MOD_USART1 - * @arg @ref LL_SYSCFG_IR_MOD_USART4 - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD)); -} -#endif /* SYSCFG_CFGR1_IR_MOD */ - -#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) || defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) || defined(SYSCFG_CFGR1_USART2_DMA_RMP) || defined(SYSCFG_CFGR1_USART3_DMA_RMP) -/** - * @brief Set DMA request remapping bits for USART - * @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n - * SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n - * SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n - * SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*) - * @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*) - * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*) - * @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*) - * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*) - * @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*) - * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*) - * @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); -} -#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP || SYSCFG_CFGR1_USART1RX_DMA_RMP || SYSCFG_CFGR1_USART2_DMA_RMP || SYSCFG_CFGR1_USART3_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP) -/** - * @brief Set DMA request remapping bits for SPI - * @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45 - * @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap); -} -#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP) -/** - * @brief Set DMA request remapping bits for I2C - * @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32 - * @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap); -} -#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_ADC_DMA_RMP) -/** - * @brief Set DMA request remapping bits for ADC - * @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1 - * @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap); -} -#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) || defined(SYSCFG_CFGR1_TIM17_DMA_RMP) || defined(SYSCFG_CFGR1_TIM1_DMA_RMP) || defined(SYSCFG_CFGR1_TIM2_DMA_RMP) || defined(SYSCFG_CFGR1_TIM3_DMA_RMP) -/** - * @brief Set DMA request remapping bits for TIM - * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n - * SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM - * @param Remap This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*) - * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*) - * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*) - * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*) - * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*) - * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*) - * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*) - * @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*) - * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*) - * @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*) - * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*) - * @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) -{ - MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U)); -} -#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP || SYSCFG_CFGR1_TIM17_DMA_RMP || SYSCFG_CFGR1_TIM1_DMA_RMP || SYSCFG_CFGR1_TIM2_DMA_RMP || SYSCFG_CFGR1_TIM3_DMA_RMP */ - -#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) -/** - * @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either - * PA9/10 or PA11/12 pin pair on small pin-count packages) - * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); -} - -/** - * @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either - * PA9/10 or PA11/12 pin pair on small pin-count packages) - * @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP); -} -#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ - -/** - * @brief Enable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); -} - -/** - * @brief Configure source input for the EXTI external interrupt. - * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource - * @param Port This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD (*) - * @arg @ref LL_SYSCFG_EXTI_PORTE (*) - * @arg @ref LL_SYSCFG_EXTI_PORTF - * - * (*) value not defined in all devices - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) -{ - MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16)); -} - -/** - * @brief Get the configured defined for specific EXTI Line - * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD (*) - * @arg @ref LL_SYSCFG_EXTI_PORTE (*) - * @arg @ref LL_SYSCFG_EXTI_PORTF - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) -{ - return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16)); -} - -#if defined(SYSCFG_ITLINE0_SR_EWDG) -/** - * @brief Check if Window watchdog interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)); -} -#endif /* SYSCFG_ITLINE0_SR_EWDG */ - -#if defined(SYSCFG_ITLINE1_SR_PVDOUT) -/** - * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16). - * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)); -} -#endif /* SYSCFG_ITLINE1_SR_PVDOUT */ - -#if defined(SYSCFG_ITLINE1_SR_VDDIO2) -/** - * @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31). - * @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2)); -} -#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */ - -#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP) -/** - * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20). - * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP)); -} -#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */ - -#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP) -/** - * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19). - * @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP)); -} -#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */ - -#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA) -/** - * @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17). - * @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA)); -} -#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */ - -#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF) -/** - * @brief Check if Flash interface interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)); -} -#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */ - -#if defined(SYSCFG_ITLINE4_SR_CRS) -/** - * @brief Check if Clock recovery system interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)); -} -#endif /* SYSCFG_ITLINE4_SR_CRS */ - -#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL) -/** - * @brief Check if Reset and clock control interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)); -} -#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */ - -#if defined(SYSCFG_ITLINE5_SR_EXTI0) -/** - * @brief Check if EXTI line 0 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)); -} -#endif /* SYSCFG_ITLINE5_SR_EXTI0 */ - -#if defined(SYSCFG_ITLINE5_SR_EXTI1) -/** - * @brief Check if EXTI line 1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)); -} -#endif /* SYSCFG_ITLINE5_SR_EXTI1 */ - -#if defined(SYSCFG_ITLINE6_SR_EXTI2) -/** - * @brief Check if EXTI line 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)); -} -#endif /* SYSCFG_ITLINE6_SR_EXTI2 */ - -#if defined(SYSCFG_ITLINE6_SR_EXTI3) -/** - * @brief Check if EXTI line 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)); -} -#endif /* SYSCFG_ITLINE6_SR_EXTI3 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI4) -/** - * @brief Check if EXTI line 4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI4 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI5) -/** - * @brief Check if EXTI line 5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI5 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI6) -/** - * @brief Check if EXTI line 6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI6 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI7) -/** - * @brief Check if EXTI line 7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI7 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI8) -/** - * @brief Check if EXTI line 8 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI8 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI9) -/** - * @brief Check if EXTI line 9 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI9 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI10) -/** - * @brief Check if EXTI line 10 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI10 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI11) -/** - * @brief Check if EXTI line 11 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI11 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI12) -/** - * @brief Check if EXTI line 12 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI12 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI13) -/** - * @brief Check if EXTI line 13 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI13 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI14) -/** - * @brief Check if EXTI line 14 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI14 */ - -#if defined(SYSCFG_ITLINE7_SR_EXTI15) -/** - * @brief Check if EXTI line 15 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)); -} -#endif /* SYSCFG_ITLINE7_SR_EXTI15 */ - -#if defined(SYSCFG_ITLINE8_SR_TSC_EOA) -/** - * @brief Check if Touch sensing controller end of acquisition interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA)); -} -#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */ - -#if defined(SYSCFG_ITLINE8_SR_TSC_MCE) -/** - * @brief Check if Touch sensing controller max counterror interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE)); -} -#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */ - -#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1) -/** - * @brief Check if DMA1 channel 1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)); -} -#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2) -/** - * @brief Check if DMA1 channel 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3) -/** - * @brief Check if DMA1 channel 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1) -/** - * @brief Check if DMA2 channel 1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */ - -#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2) -/** - * @brief Check if DMA2 channel 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2)); -} -#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4) -/** - * @brief Check if DMA1 channel 4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5) -/** - * @brief Check if DMA1 channel 5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6) -/** - * @brief Check if DMA1 channel 6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7) -/** - * @brief Check if DMA1 channel 7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3) -/** - * @brief Check if DMA2 channel 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4) -/** - * @brief Check if DMA2 channel 4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */ - -#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5) -/** - * @brief Check if DMA2 channel 5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)); -} -#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */ - -#if defined(SYSCFG_ITLINE12_SR_ADC) -/** - * @brief Check if ADC interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)); -} -#endif /* SYSCFG_ITLINE12_SR_ADC */ - -#if defined(SYSCFG_ITLINE12_SR_COMP1) -/** - * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21). - * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)); -} -#endif /* SYSCFG_ITLINE12_SR_COMP1 */ - -#if defined(SYSCFG_ITLINE12_SR_COMP2) -/** - * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22). - * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)); -} -#endif /* SYSCFG_ITLINE12_SR_COMP2 */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK) -/** - * @brief Check if Timer 1 break interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD) -/** - * @brief Check if Timer 1 update interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG) -/** - * @brief Check if Timer 1 trigger interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */ - -#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU) -/** - * @brief Check if Timer 1 commutation interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)); -} -#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */ - -#if defined(SYSCFG_ITLINE14_SR_TIM1_CC) -/** - * @brief Check if Timer 1 capture compare interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)); -} -#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */ - -#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB) -/** - * @brief Check if Timer 2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)); -} -#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */ - -#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB) -/** - * @brief Check if Timer 3 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)); -} -#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */ - -#if defined(SYSCFG_ITLINE17_SR_DAC) -/** - * @brief Check if DAC underrun interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)); -} -#endif /* SYSCFG_ITLINE17_SR_DAC */ - -#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB) -/** - * @brief Check if Timer 6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)); -} -#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */ - -#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB) -/** - * @brief Check if Timer 7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)); -} -#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */ - -#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB) -/** - * @brief Check if Timer 14 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)); -} -#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */ - -#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB) -/** - * @brief Check if Timer 15 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)); -} -#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */ - -#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB) -/** - * @brief Check if Timer 16 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)); -} -#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */ - -#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB) -/** - * @brief Check if Timer 17 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)); -} -#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */ - -#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB) -/** - * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23. - * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)); -} -#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */ - -#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB) -/** - * @brief Check if I2C2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)); -} -#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */ - -#if defined(SYSCFG_ITLINE25_SR_SPI1) -/** - * @brief Check if SPI1 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)); -} -#endif /* SYSCFG_ITLINE25_SR_SPI1 */ - -#if defined(SYSCFG_ITLINE26_SR_SPI2) -/** - * @brief Check if SPI2 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)); -} -#endif /* SYSCFG_ITLINE26_SR_SPI2 */ - -#if defined(SYSCFG_ITLINE27_SR_USART1_GLB) -/** - * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25. - * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)); -} -#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */ - -#if defined(SYSCFG_ITLINE28_SR_USART2_GLB) -/** - * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26. - * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)); -} -#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART3_GLB) -/** - * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28. - * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART4_GLB) -/** - * @brief Check if USART4 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART5_GLB) -/** - * @brief Check if USART5 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART6_GLB) -/** - * @brief Check if USART6 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART7_GLB) -/** - * @brief Check if USART7 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */ - -#if defined(SYSCFG_ITLINE29_SR_USART8_GLB) -/** - * @brief Check if USART8 interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB)); -} -#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */ - -#if defined(SYSCFG_ITLINE30_SR_CAN) -/** - * @brief Check if CAN interrupt occurred or not. - * @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN)); -} -#endif /* SYSCFG_ITLINE30_SR_CAN */ - -#if defined(SYSCFG_ITLINE30_SR_CEC) -/** - * @brief Check if CEC interrupt occurred or not, combined with EXTI line 27. - * @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void) -{ - return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)); -} -#endif /* SYSCFG_ITLINE30_SR_CEC */ - -/** - * @brief Set connections to TIMx Break inputs - * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs - * @param Break This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) - * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) -{ -#if defined(SYSCFG_CFGR2_PVD_LOCK) - MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); -#else - MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break); -#endif /*SYSCFG_CFGR2_PVD_LOCK*/ -} - -/** - * @brief Get connections to TIMx Break inputs - * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs - * @retval Returned value can be can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) - * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) -{ -#if defined(SYSCFG_CFGR2_PVD_LOCK) - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, - SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)); -#else - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)); -#endif /*SYSCFG_CFGR2_PVD_LOCK*/ -} - -/** - * @brief Check if SRAM parity error detected - * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) -{ - return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF)); -} - -/** - * @brief Clear SRAM parity error flag - * @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) -{ - SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF); -} - -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU - * @{ - */ - -/** - * @brief Return the device identifier - * @note For STM32F03x devices, the device ID is 0x444 - * @note For STM32F04x devices, the device ID is 0x445. - * @note For STM32F05x devices, the device ID is 0x440 - * @note For STM32F07x devices, the device ID is 0x448 - * @note For STM32F09x devices, the device ID is 0x442 - * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); -} - -/** - * @brief Return the device revision identifier - * @note This field indicates the revision of the device. - For example, it is read as 0x1000 for Revision 1.0. - * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Freeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Freeze APB1 peripherals (group2 peripherals) - * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB2FZ, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group2 peripherals) - * @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n - * DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB2FZ, Periphs); -} -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_FLASH FLASH - * @{ - */ - -/** - * @brief Set FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency - * @param Latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); -} - -/** - * @brief Get FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); -} - -/** - * @brief Enable Prefetch - * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); -} - -/** - * @brief Disable Prefetch - * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); -} - -/** - * @brief Check if Prefetch buffer is enabled - * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) -{ - return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); -} - - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_SYSTEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_usart.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_usart.h deleted file mode 100644 index 54eadcb..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_usart.h +++ /dev/null @@ -1,3819 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_usart.h - * @author MCD Application Team - * @brief Header file of USART LL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_USART_H -#define __STM32F0xx_LL_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) || defined (USART7) || defined (USART8) - -/** @defgroup USART_LL USART - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_Private_Macros USART Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_ES_INIT USART Exported Init structures - * @{ - */ - -/** - * @brief LL USART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ - - uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_LL_EC_STOPBITS. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_LL_EC_PARITY. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ - - uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_DIRECTION. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ - - uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ - - uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. - This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ - -} LL_USART_InitTypeDef; - -/** - * @brief LL USART Clock Init Structure definition - */ -typedef struct -{ - uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_CLOCK. - - USART HW configuration can be modified afterwards using unitary functions - @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). - For more details, refer to description of this function. */ - - uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_LL_EC_POLARITY. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). - For more details, refer to description of this function. */ - - uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_LL_EC_PHASE. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). - For more details, refer to description of this function. */ - - uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). - For more details, refer to description of this function. */ - -} LL_USART_ClockInitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Constants USART Exported Constants - * @{ - */ - -/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_USART_WriteReg function - * @{ - */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#if defined(USART_LIN_SUPPORT) -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ -#endif -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ -#if defined(USART_SMARTCARD_SUPPORT) -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ -#endif -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#if defined(USART_WUSM_SUPPORT) -#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ -#endif -/** - * @} - */ - -/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_USART_ReadReg function - * @{ - */ -#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ -#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ -#if defined(USART_LIN_SUPPORT) -#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ -#endif -#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ -#if defined(USART_SMARTCARD_SUPPORT) -#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ -#endif -#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ -#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ -#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#if defined(USART_WUSM_SUPPORT) -#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ -#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#endif -/** - * @} - */ - -/** @defgroup USART_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions - * @{ - */ -#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ -#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ -#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ -#if defined(USART_SMARTCARD_SUPPORT) -#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ -#endif -#if defined(USART_LIN_SUPPORT) -#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ -#endif -#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#if defined(USART_WUSM_SUPPORT) -#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ -#endif -/** - * @} - */ - -/** @defgroup USART_LL_EC_DIRECTION Communication Direction - * @{ - */ -#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PARITY Parity Control - * @{ - */ -#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_WAKEUP Wakeup - * @{ - */ -#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ -#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#if defined(USART_7BITS_SUPPORT) -#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ -#else -#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ -#endif -/** - * @} - */ - -/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling - * @{ - */ -#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EC_CLOCK Clock Signal - * @{ - */ - -#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ -#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse - * @{ - */ -#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ -#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PHASE Clock Phase - * @{ - */ -#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ -#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ -#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_STOPBITS Stop Bits - * @{ - */ -#if defined(USART_SMARTCARD_SUPPORT) -#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ -#endif -#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#if defined(USART_SMARTCARD_SUPPORT) -#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ -#endif -#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap - * @{ - */ -#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion - * @{ - */ -#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion - * @{ - */ -#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion - * @{ - */ -#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ -#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_BITORDER Bit Order - * @{ - */ -#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ -#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection - * @{ - */ -#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ -#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ -#if defined(USART_FABR_SUPPORT) -#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ -#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ -#endif -/** - * @} - */ - -/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection - * @{ - */ -#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_HWCONTROL Hardware Control - * @{ - */ -#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ -/** - * @} - */ - -#if defined(USART_WUSM_SUPPORT) -/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation - * @{ - */ -#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ -#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ -#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ -/** - * @} - */ -#endif - -#if defined(USART_IRDA_SUPPORT) -/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power - * @{ - */ -#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ -#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ -/** - * @} - */ -#endif - -#if defined(USART_LIN_SUPPORT) -/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length - * @{ - */ -#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ -#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ -/** - * @} - */ -#endif - -/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity - * @{ - */ -#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data - * @{ - */ -#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Macros USART Exported Macros - * @{ - */ - -/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper - * @{ - */ - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case - */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case - */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USART_LL_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_LL_EF_Configuration Configuration functions - * @{ - */ - -/** - * @brief USART Enable - * @rmtoll CR1 UE LL_USART_Enable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief USART Disable (all USART prescalers and outputs are disabled) - * @note When USART is disabled, USART prescalers and outputs are stopped immediately, - * and current operations are discarded. The configuration of the USART is kept, but all the status - * flags, in the USARTx_ISR are set to their default values. - * @rmtoll CR1 UE LL_USART_Disable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief Indicate if USART is enabled - * @rmtoll CR1 UE LL_USART_IsEnabled - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); -} - -#if defined(USART_WUSM_SUPPORT) -/** - * @brief USART enabled in STOP Mode. - * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that - * USART clock selection is HSI or LSE in RCC. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_EnableInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief USART disabled in STOP Mode. - * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_DisableInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); -} -#endif - -/** - * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) - * @rmtoll CR1 RE LL_USART_EnableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Receiver Disable - * @rmtoll CR1 RE LL_USART_DisableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Transmitter Enable - * @rmtoll CR1 TE LL_USART_EnableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Transmitter Disable - * @rmtoll CR1 TE LL_USART_DisableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Configure simultaneously enabled/disabled states - * of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_SetTransferDirection\n - * CR1 TE LL_USART_SetTransferDirection - * @param USARTx USART Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); -} - -/** - * @brief Return enabled/disabled states of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_GetTransferDirection\n - * CR1 TE LL_USART_GetTransferDirection - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); -} - -/** - * @brief Configure Parity (enabled/disabled and parity mode if enabled). - * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. - * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position - * (9th or 8th bit depending on data width) and parity is checked on the received data. - * @rmtoll CR1 PS LL_USART_SetParity\n - * CR1 PCE LL_USART_SetParity - * @param USARTx USART Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); -} - -/** - * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) - * @rmtoll CR1 PS LL_USART_GetParity\n - * CR1 PCE LL_USART_GetParity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); -} - -/** - * @brief Set Receiver Wake Up method from Mute mode. - * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod - * @param USARTx USART Instance - * @param Method This parameter can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - * @retval None - */ -__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); -} - -/** - * @brief Return Receiver Wake Up method from Mute mode - * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); -} - -/** - * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M0 LL_USART_SetDataWidth\n - * CR1 M1 LL_USART_SetDataWidth - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B (*) - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * - * (*) Values not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); -} - -/** - * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M0 LL_USART_GetDataWidth\n - * CR1 M1 LL_USART_GetDataWidth - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B (*) - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * - * (*) Values not available on all devices - */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); -} - -/** - * @brief Allow switch between Mute Mode and Active mode - * @rmtoll CR1 MME LL_USART_EnableMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. - * @rmtoll CR1 MME LL_USART_DisableMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Indicate if switch between Mute Mode and Active mode is allowed - * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); -} - -/** - * @brief Set Oversampling to 8-bit or 16-bit mode - * @rmtoll CR1 OVER8 LL_USART_SetOverSampling - * @param USARTx USART Instance - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); -} - -/** - * @brief Return Oversampling mode - * @rmtoll CR1 OVER8 LL_USART_GetOverSampling - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); -} - -/** - * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput - * @param USARTx USART Instance - * @param LastBitClockPulse This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); -} - -/** - * @brief Retrieve Clock pulse of the last data bit output configuration - * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); -} - -/** - * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_SetClockPhase - * @param USARTx USART Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); -} - -/** - * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_GetClockPhase - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); -} - -/** - * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_SetClockPolarity - * @param USARTx USART Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); -} - -/** - * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_GetClockPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); -} - -/** - * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function - * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function - * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function - * @rmtoll CR2 CPHA LL_USART_ConfigClock\n - * CR2 CPOL LL_USART_ConfigClock\n - * CR2 LBCL LL_USART_ConfigClock - * @param USARTx USART Instance - * @param Phase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @param LBCPOutput This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); -} - -/** - * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); -} - -/** - * @brief Set the length of the stop bits - * @rmtoll CR2 STOP LL_USART_SetStopBitsLength - * @param USARTx USART Instance - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 (*) - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 (*) - * @arg @ref LL_USART_STOPBITS_2 - * - * (*) Values not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Retrieve the length of the stop bits - * @rmtoll CR2 STOP LL_USART_GetStopBitsLength - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 (*) - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 (*) - * @arg @ref LL_USART_STOPBITS_2 - * - * (*) Values not available on all devices - */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); -} - -/** - * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) - * @note Call of this function is equivalent to following function call sequence : - * - Data Width configuration using @ref LL_USART_SetDataWidth() function - * - Parity Control and mode configuration using @ref LL_USART_SetParity() function - * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function - * @rmtoll CR1 PS LL_USART_ConfigCharacter\n - * CR1 PCE LL_USART_ConfigCharacter\n - * CR1 M0 LL_USART_ConfigCharacter\n - * CR1 M1 LL_USART_ConfigCharacter\n - * CR2 STOP LL_USART_ConfigCharacter - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B (*) - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 (*) - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 (*) - * @arg @ref LL_USART_STOPBITS_2 - * - * (*) Values not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, - uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Configure TX/RX pins swapping setting. - * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap - * @param USARTx USART Instance - * @param SwapConfig This parameter can be one of the following values: - * @arg @ref LL_USART_TXRX_STANDARD - * @arg @ref LL_USART_TXRX_SWAPPED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); -} - -/** - * @brief Retrieve TX/RX pins swapping configuration. - * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_TXRX_STANDARD - * @arg @ref LL_USART_TXRX_SWAPPED - */ -__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); -} - -/** - * @brief Configure RX pin active level logic - * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel - * @param USARTx USART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); -} - -/** - * @brief Retrieve RX pin active level logic configuration - * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); -} - -/** - * @brief Configure TX pin active level logic - * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel - * @param USARTx USART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); -} - -/** - * @brief Retrieve TX pin active level logic configuration - * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); -} - -/** - * @brief Configure Binary data logic. - * @note Allow to define how Logical data from the data register are send/received : - * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) - * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic - * @param USARTx USART Instance - * @param DataLogic This parameter can be one of the following values: - * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); -} - -/** - * @brief Retrieve Binary data configuration - * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE - */ -__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); -} - -/** - * @brief Configure transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder - * @param USARTx USART Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref LL_USART_BITORDER_LSBFIRST - * @arg @ref LL_USART_BITORDER_MSBFIRST - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); -} - -/** - * @brief Return transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_BITORDER_LSBFIRST - * @arg @ref LL_USART_BITORDER_MSBFIRST - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); -} - -/** - * @brief Enable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_ABREN); -} - -/** - * @brief Disable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); -} - -/** - * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)); -} - -/** - * @brief Set Auto Baud-Rate mode bits - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode - * @param USARTx USART Instance - * @param AutoBaudRateMode This parameter can be one of the following values: - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME (*) - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (*) - * - * (*) Values not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); -} - -/** - * @brief Return Auto Baud-Rate mode - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME (*) - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (*) - * - * (*) Values not available on all devices - */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); -} - -/** - * @brief Enable Receiver Timeout - * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_RTOEN); -} - -/** - * @brief Disable Receiver Timeout - * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); -} - -/** - * @brief Indicate if Receiver Timeout feature is enabled - * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)); -} - -/** - * @brief Set Address of the USART node. - * @note This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with address mark detection. - * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. - * (b7-b4 should be set to 0) - * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. - * (This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with 7-bit address mark detection. - * The MSB of the character sent by the transmitter should be equal to 1. - * It may also be used for character detection during normal reception, - * Mute mode inactive (for example, end of block detection in ModBus protocol). - * In this case, the whole received character (8-bit) is compared to the ADD[7:0] - * value and CMF flag is set on match) - * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n - * CR2 ADDM7 LL_USART_ConfigNodeAddress - * @param USARTx USART Instance - * @param AddressLen This parameter can be one of the following values: - * @arg @ref LL_USART_ADDRESS_DETECT_4B - * @arg @ref LL_USART_ADDRESS_DETECT_7B - * @param NodeAddress 4 or 7 bit Address of the USART node. - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, - (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); -} - -/** - * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. - * @note If 4-bit Address Detection is selected in ADDM7, - * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) - * If 7-bit Address Detection is selected in ADDM7, - * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) - * @rmtoll CR2 ADD LL_USART_GetNodeAddress - * @param USARTx USART Instance - * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); -} - -/** - * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) - * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_ADDRESS_DETECT_4B - * @arg @ref LL_USART_ADDRESS_DETECT_7B - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); -} - -/** - * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n - * CR3 CTSE LL_USART_SetHWFlowCtrl - * @param USARTx USART Instance - * @param HardwareFlowControl This parameter can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - * @retval None - */ -__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); -} - -/** - * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n - * CR3 CTSE LL_USART_GetHWFlowCtrl - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); -} - -/** - * @brief Enable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Disable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Indicate if One bit sampling method is enabled - * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); -} - -/** - * @brief Enable Overrun detection - * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Disable Overrun detection - * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Indicate if Overrun detection is enabled - * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); -} - -#if defined(USART_WUSM_SUPPORT) -/** - * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUS LL_USART_SetWKUPType - * @param USARTx USART Instance - * @param Type This parameter can be one of the following values: - * @arg @ref LL_USART_WAKEUP_ON_ADDRESS - * @arg @ref LL_USART_WAKEUP_ON_STARTBIT - * @arg @ref LL_USART_WAKEUP_ON_RXNE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); -} - -/** - * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUS LL_USART_GetWKUPType - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_WAKEUP_ON_ADDRESS - * @arg @ref LL_USART_WAKEUP_ON_STARTBIT - * @arg @ref LL_USART_WAKEUP_ON_RXNE - */ -__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); -} -#endif - -/** - * @brief Configure USART BRR register for achieving expected Baud Rate value. - * @note Compute and set USARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values - * @note Peripheral clock and Baud rate values provided as function parameters should be valid - * (Baud rate value != 0) - * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. - * @rmtoll BRR BRR LL_USART_SetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, - uint32_t BaudRate) -{ - register uint32_t usartdiv = 0x0U; - register uint32_t brrtemp = 0x0U; - - if (OverSampling == LL_USART_OVERSAMPLING_8) - { - usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); - brrtemp = usartdiv & 0xFFF0U; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - USARTx->BRR = brrtemp; - } - else - { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); - } -} - -/** - * @brief Return current Baud Rate value, according to USARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock and Oversampling mode values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. - * @rmtoll BRR BRR LL_USART_GetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) -{ - register uint32_t usartdiv = 0x0U; - register uint32_t brrresult = 0x0U; - - usartdiv = USARTx->BRR; - - if (OverSampling == LL_USART_OVERSAMPLING_8) - { - if ((usartdiv & 0xFFF7U) != 0U) - { - usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; - brrresult = (PeriphClk * 2U) / usartdiv; - } - } - else - { - if ((usartdiv & 0xFFFFU) != 0U) - { - brrresult = PeriphClk / usartdiv; - } - } - return (brrresult); -} - -/** - * @brief Set Receiver Time Out Value (expressed in nb of bits duration) - * @rmtoll RTOR RTO LL_USART_SetRxTimeout - * @param USARTx USART Instance - * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) -{ - MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); -} - -/** - * @brief Get Receiver Time Out Value (expressed in nb of bits duration) - * @rmtoll RTOR RTO LL_USART_GetRxTimeout - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF - */ -__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Set Block Length value in reception - * @rmtoll RTOR BLEN LL_USART_SetBlockLength - * @param USARTx USART Instance - * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) -{ - MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); -} - -/** - * @brief Get Block Length value in reception - * @rmtoll RTOR BLEN LL_USART_GetBlockLength - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); -} -#endif - -/** - * @} - */ - -#if defined(USART_IRDA_SUPPORT) -/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature - * @{ - */ - -/** - * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_EnableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_DisableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_IsEnabledIrda - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); -} - -/** - * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode - * @param USARTx USART Instance - * @param PowerMode This parameter can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_IRDA_POWER_LOW - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); -} - -/** - * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); -} - -/** - * @brief Set Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); -} - -/** - * @brief Return Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler - * @param USARTx USART Instance - * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @} - */ -#endif - -#if defined(USART_SMARTCARD_SUPPORT) -/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature - * @{ - */ - -/** - * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); -} - -/** - * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_EnableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_DisableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); -} - -/** - * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. - * In transmission mode, it specifies the number of automatic retransmission retries, before - * generating a transmission error (FE bit set). - * In reception mode, it specifies the number or erroneous reception trials, before generating a - * reception error (RXNE and PE bits set) - * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount - * @param USARTx USART Instance - * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); -} - -/** - * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount - * @param USARTx USART Instance - * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); -} - -/** - * @brief Set Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); -} - -/** - * @brief Return Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler - * @param USARTx USART Instance - * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime - * @param USARTx USART Instance - * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos); -} - -/** - * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime - * @param USARTx USART Instance - * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); -} - -/** - * @} - */ -#endif - -/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature - * @{ - */ - -/** - * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); -} - -/** - * @} - */ - -#if defined(USART_LIN_SUPPORT) -/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature - * @{ - */ - -/** - * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen - * @param USARTx USART Instance - * @param LINBDLength This parameter can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); -} - -/** - * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); -} - -/** - * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_EnableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_DisableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); -} - -/** - * @} - */ -#endif - -/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature - * @{ - */ - -/** - * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime - * @param USARTx USART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); -} - -/** - * @brief Return DEDT (Driver Enable De-Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime - * @param USARTx USART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 - */ -__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); -} - -/** - * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime - * @param USARTx USART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); -} - -/** - * @brief Return DEAT (Driver Enable Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime - * @param USARTx USART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 - */ -__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); -} - -/** - * @brief Enable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_EnableDEMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Disable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_DisableDEMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Indicate if Driver Enable (DE) Mode is enabled - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)); -} - -/** - * @brief Select Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity - * @param USARTx USART Instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_DE_POLARITY_HIGH - * @arg @ref LL_USART_DE_POLARITY_LOW - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); -} - -/** - * @brief Return Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DE_POLARITY_HIGH - * @arg @ref LL_USART_DE_POLARITY_LOW - */ -__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services - * @{ - */ - -/** - * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) - * @note In UART mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register (if LIN feature is supported), - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register (if Smartcard feature is supported), - * - IREN bit in the USART_CR3 register (if Irda feature is supported), - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function (if LIN feature is supported) - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function (if Smartcard feature is supported) - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function (if Irda feature is supported) - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Asynchronous Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n - * CR2 CLKEN LL_USART_ConfigAsyncMode\n - * CR3 SCEN LL_USART_ConfigAsyncMode\n - * CR3 IREN LL_USART_ConfigAsyncMode\n - * CR3 HDSEL LL_USART_ConfigAsyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) -{ - /* In Asynchronous mode, the following bits must be kept cleared: - - LINEN (if LIN feature is supported), CLKEN bits in the USART_CR2 register, - - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.*/ -#if defined(USART_LIN_SUPPORT) - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); -#else - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -#endif -#if defined(USART_SMARTCARD_SUPPORT) -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); -#endif -#else -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -#endif -#endif -} - -/** - * @brief Perform basic configuration of USART for enabling use in Synchronous Mode - * @note In Synchronous mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register (if LIN feature is supported), - * - SCEN bit in the USART_CR3 register (if Smartcard feature is supported), - * - IREN bit in the USART_CR3 register (if Irda feature is supported), - * - HDSEL bit in the USART_CR3 register. - * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function (if LIN feature is supported) - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function (if Irda feature is supported) - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function (if Smartcard feature is supported) - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * @note Other remaining configurations items related to Synchronous Mode - * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n - * CR2 CLKEN LL_USART_ConfigSyncMode\n - * CR3 SCEN LL_USART_ConfigSyncMode\n - * CR3 IREN LL_USART_ConfigSyncMode\n - * CR3 HDSEL LL_USART_ConfigSyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) -{ - /* In Synchronous mode, the following bits must be kept cleared: - - LINEN (if LIN feature is supported) bit in the USART_CR2 register, - - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.*/ -#if defined(USART_LIN_SUPPORT) - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); -#endif -#if defined(USART_SMARTCARD_SUPPORT) -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); -#endif -#else -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -#endif -#endif - /* set the UART/USART in Synchronous mode */ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -#if defined(USART_LIN_SUPPORT) -/** - * @brief Perform basic configuration of USART for enabling use in LIN Mode - * @note In LIN mode, the following bits must be kept cleared: - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register (if Smartcard feature is supported), - * - IREN bit in the USART_CR3 register (if Irda feature is supported), - * - HDSEL bit in the USART_CR3 register. - * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function (if Smartcard feature is supported) - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function (if Irda feature is supported) - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function - * @note Other remaining configurations items related to LIN Mode - * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n - * CR2 STOP LL_USART_ConfigLINMode\n - * CR2 LINEN LL_USART_ConfigLINMode\n - * CR3 IREN LL_USART_ConfigLINMode\n - * CR3 SCEN LL_USART_ConfigLINMode\n - * CR3 HDSEL LL_USART_ConfigLINMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) -{ - /* In LIN mode, the following bits must be kept cleared: - - STOP and CLKEN bits in the USART_CR2 register, - - IREN (if Irda feature is supported), SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); -#if defined(USART_SMARTCARD_SUPPORT) -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); -#endif -#else -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -#endif -#endif - /* Set the UART/USART in LIN mode */ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} -#endif - -/** - * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode - * @note In Half Duplex mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register (if LIN feature is supported), - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register (if Smartcard feature is supported), - * - IREN bit in the USART_CR3 register (if Irda feature is supported), - * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function (if LIN feature is supported) - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function (if Smartcard feature is supported) - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function (if Irda feature is supported) - * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function - * @note Other remaining configurations items related to Half Duplex Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n - * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n - * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n - * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n - * CR3 IREN LL_USART_ConfigHalfDuplexMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) -{ - /* In Half Duplex mode, the following bits must be kept cleared: - - LINEN (if LIN feature is supported), CLKEN bits in the USART_CR2 register, - - SCEN (if Smartcard feature is supported) and IREN (if Irda feature is supported) bits in the USART_CR3 register.*/ -#if defined(USART_LIN_SUPPORT) - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); -#else - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -#endif -#if defined(USART_SMARTCARD_SUPPORT) -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN)); -#endif -#else -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN)); -#endif -#endif - /* set the UART/USART in Half Duplex mode */ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Perform basic configuration of USART for enabling use in Smartcard Mode - * @note In Smartcard mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register (if LIN feature is supported), - * - IREN bit in the USART_CR3 register (if Irda feature is supported), - * - HDSEL bit in the USART_CR3 register. - * This function also configures Stop bits to 1.5 bits and - * sets the USART in Smartcard mode (SCEN bit). - * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function (if LIN feature is supported) - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function (if Irda feature is supported) - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function - * @note Other remaining configurations items related to Smartcard Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n - * CR2 STOP LL_USART_ConfigSmartcardMode\n - * CR2 CLKEN LL_USART_ConfigSmartcardMode\n - * CR3 HDSEL LL_USART_ConfigSmartcardMode\n - * CR3 SCEN LL_USART_ConfigSmartcardMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) -{ - /* In Smartcard mode, the following bits must be kept cleared: - - LINEN (if LIN feature is supported) bit in the USART_CR2 register, - - IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.*/ -#if defined(USART_LIN_SUPPORT) - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); -#endif -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL)); -#endif - /* Configure Stop bits to 1.5 bits */ - /* Synchronous mode is activated by default */ - SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); - /* set the UART/USART in Smartcard mode */ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} -#endif - -#if defined(USART_IRDA_SUPPORT) -/** - * @brief Perform basic configuration of USART for enabling use in Irda Mode - * @note In IRDA mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register (if LIN feature is supported), - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register (if Smartcard feature is supported), - * - HDSEL bit in the USART_CR3 register. - * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function (if LIN feature is supported) - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function (if Smartcard feature is supported) - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function - * @note Other remaining configurations items related to Irda Mode - * (as Baud Rate, Word length, Power mode, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n - * CR2 CLKEN LL_USART_ConfigIrdaMode\n - * CR2 STOP LL_USART_ConfigIrdaMode\n - * CR3 SCEN LL_USART_ConfigIrdaMode\n - * CR3 HDSEL LL_USART_ConfigIrdaMode\n - * CR3 IREN LL_USART_ConfigIrdaMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) -{ - /* In IRDA mode, the following bits must be kept cleared: - - LINEN (if LIN feature is supported), STOP and CLKEN bits in the USART_CR2 register, - - SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.*/ -#if defined(USART_LIN_SUPPORT) - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); -#else - CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); -#endif -#if defined(USART_SMARTCARD_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL)); -#endif - /* set the UART/USART in IRDA mode */ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} -#endif - -/** - * @brief Perform basic configuration of USART for enabling use in Multi processor Mode - * (several USARTs connected in a network, one of the USARTs can be the master, - * its TX output connected to the RX inputs of the other slaves USARTs). - * @note In MultiProcessor mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register (if LIN feature is supported), - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register (if Smartcard feature is supported), - * - IREN bit in the USART_CR3 register (if Irda feature is supported), - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function (if LIN feature is supported) - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function (if Smartcard feature is supported) - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function (if Irda feature is supported) - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Multi processor Mode - * (as Baud Rate, Wake Up Method, Node address, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n - * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n - * CR3 SCEN LL_USART_ConfigMultiProcessMode\n - * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n - * CR3 IREN LL_USART_ConfigMultiProcessMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) -{ - /* In Multi Processor mode, the following bits must be kept cleared: - - LINEN (if LIN feature is supported) and CLKEN bits in the USART_CR2 register, - - IREN (if Irda feature is supported), SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.*/ -#if defined(USART_LIN_SUPPORT) - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); -#else - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -#endif -#if defined(USART_SMARTCARD_SUPPORT) -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); -#endif -#else -#if defined(USART_IRDA_SUPPORT) - CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); -#else - CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL)); -#endif -#endif -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if the USART Parity Error Flag is set or not - * @rmtoll ISR PE LL_USART_IsActiveFlag_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)); -} - -/** - * @brief Check if the USART Framing Error Flag is set or not - * @rmtoll ISR FE LL_USART_IsActiveFlag_FE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)); -} - -/** - * @brief Check if the USART Noise error detected Flag is set or not - * @rmtoll ISR NF LL_USART_IsActiveFlag_NE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)); -} - -/** - * @brief Check if the USART OverRun Error Flag is set or not - * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)); -} - -/** - * @brief Check if the USART IDLE line detected Flag is set or not - * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); -} - -/** - * @brief Check if the USART Read Data Register Not Empty Flag is set or not - * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); -} - -/** - * @brief Check if the USART Transmission Complete Flag is set or not - * @rmtoll ISR TC LL_USART_IsActiveFlag_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); -} - -/** - * @brief Check if the USART Transmit Data Register Empty Flag is set or not - * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); -} - -#if defined(USART_LIN_SUPPORT) -/** - * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)); -} -#endif - -/** - * @brief Check if the USART CTS interrupt Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)); -} - -/** - * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)); -} - -/** - * @brief Check if the USART Receiver Time Out Flag is set or not - * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Check if the USART End Of Block Flag is set or not - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)); -} -#endif - -/** - * @brief Check if the USART Auto-Baud Rate Error Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)); -} - -/** - * @brief Check if the USART Auto-Baud Rate Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)); -} - -/** - * @brief Check if the USART Busy Flag is set or not - * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)); -} - -/** - * @brief Check if the USART Character Match Flag is set or not - * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)); -} - -/** - * @brief Check if the USART Send Break Flag is set or not - * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)); -} - -/** - * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not - * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)); -} - -#if defined(USART_WUSM_SUPPORT) -/** - * @brief Check if the USART Wake Up from stop mode Flag is set or not - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)); -} -#endif - -/** - * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not - * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)); -} - -/** - * @brief Check if the USART Receive Enable Acknowledge Flag is set or not - * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); -} - - -/** - * @brief Clear Parity Error Flag - * @rmtoll ICR PECF LL_USART_ClearFlag_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_PECF); -} - -/** - * @brief Clear Framing Error Flag - * @rmtoll ICR FECF LL_USART_ClearFlag_FE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_FECF); -} - -/** - * @brief Clear Noise detected Flag - * @rmtoll ICR NCF LL_USART_ClearFlag_NE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_NCF); -} - -/** - * @brief Clear OverRun Error Flag - * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_ORECF); -} - -/** - * @brief Clear IDLE line detected Flag - * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); -} - -/** - * @brief Clear Transmission Complete Flag - * @rmtoll ICR TCCF LL_USART_ClearFlag_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_TCCF); -} - - -#if defined(USART_LIN_SUPPORT) -/** - * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); -} -#endif - -/** - * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); -} - -/** - * @brief Clear Receiver Time Out Flag - * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Clear End Of Block Flag - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); -} -#endif - -/** - * @brief Clear Character Match Flag - * @rmtoll ICR CMCF LL_USART_ClearFlag_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_CMCF); -} - -#if defined(USART_WUSM_SUPPORT) -/** - * @brief Clear Wake Up from stop mode Flag - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_WUCF); -} -#endif - -/** - * @} - */ - -/** @defgroup USART_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Enable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Enable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_EnableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Enable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Enable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_EnableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Enable Character Match Interrupt - * @rmtoll CR1 CMIE LL_USART_EnableIT_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Enable Receiver Timeout Interrupt - * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RTOIE); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Enable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_EOBIE); -} -#endif - -#if defined(USART_LIN_SUPPORT) -/** - * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LBDIE); -} -#endif - -/** - * @brief Enable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. - * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -#if defined(USART_WUSM_SUPPORT) -/** - * @brief Enable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_WUFIE); -} -#endif - - -/** - * @brief Disable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Disable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Disable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_DisableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Disable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Disable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_DisableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Disable Character Match Interrupt - * @rmtoll CR1 CMIE LL_USART_DisableIT_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Disable Receiver Timeout Interrupt - * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Disable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); -} -#endif - -#if defined(USART_LIN_SUPPORT) -/** - * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); -} -#endif - -/** - * @brief Disable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. - * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -#if defined(USART_WUSM_SUPPORT) -/** - * @brief Disable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); -} -#endif - - -/** - * @brief Check if the USART IDLE Interrupt source is enabled or disabled. - * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); -} - -/** - * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. - * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); -} - -/** - * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); -} - -/** - * @brief Check if the USART TX Empty Interrupt is enabled or disabled. - * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); -} - -/** - * @brief Check if the USART Parity Error Interrupt is enabled or disabled. - * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); -} - -/** - * @brief Check if the USART Character Match Interrupt is enabled or disabled. - * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); -} - -/** - * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. - * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Check if the USART End Of Block Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)); -} -#endif - -#if defined(USART_LIN_SUPPORT) -/** - * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); -} -#endif - -/** - * @brief Check if the USART Error Interrupt is enabled or disabled. - * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); -} - -/** - * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); -} - -#if defined(USART_WUSM_SUPPORT) -/** - * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); -} -#endif - - -/** - * @} - */ - -/** @defgroup USART_LL_EF_DMA_Management DMA_Management - * @{ - */ - -/** - * @brief Enable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Disable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Check if DMA Mode is enabled for reception - * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); -} - -/** - * @brief Enable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Disable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Check if DMA Mode is enabled for transmission - * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); -} - -/** - * @brief Enable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Disable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Indicate if DMA Disabling on Reception Error is disabled - * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n - * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr - * @param USARTx USART Instance - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT - * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) -{ - register uint32_t data_reg_addr = 0U; - - if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) - { - /* return address of TDR register */ - data_reg_addr = (uint32_t) &(USARTx->TDR); - } - else - { - /* return address of RDR register */ - data_reg_addr = (uint32_t) &(USARTx->RDR); - } - - return data_reg_addr; -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Read Receiver Data register (Receive Data value, 8 bits) - * @rmtoll RDR RDR LL_USART_ReceiveData8 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) -{ - return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); -} - -/** - * @brief Read Receiver Data register (Receive Data value, 9 bits) - * @rmtoll RDR RDR LL_USART_ReceiveData9 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x1FF - */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) -{ - return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) - * @rmtoll TDR TDR LL_USART_TransmitData8 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) -{ - USARTx->TDR = Value; -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) - * @rmtoll TDR TDR LL_USART_TransmitData9 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) -{ - USARTx->TDR = Value & 0x1FFU; -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Execution Execution - * @{ - */ - -/** - * @brief Request an Automatic Baud Rate measurement on next received data frame - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, USART_RQR_ABRRQ); -} - -/** - * @brief Request Break sending - * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, USART_RQR_SBKRQ); -} - -/** - * @brief Put USART in mute mode and set the RWU flag - * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, USART_RQR_MMRQ); -} - -/** - * @brief Request a Receive Data flush - * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, USART_RQR_RXFRQ); -} - -#if defined(USART_SMARTCARD_SUPPORT) -/** - * @brief Request a Transmit data flush - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, USART_RQR_TXFRQ); -} -#endif - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2|| USART3 || USART4 || USART5 || USART6 || USART7 || USART8 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_USART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h deleted file mode 100644 index a137017..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_utils.h +++ /dev/null @@ -1,287 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_utils.h - * @author MCD Application Team - * @brief Header file of UTILS LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL UTILS driver contains a set of generic APIs that can be - used by user: - (+) Device electronic signature - (+) Timing functions - (+) PLL configuration functions - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_LL_UTILS_H -#define __STM32F0xx_LL_UTILS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx.h" - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -/** @defgroup UTILS_LL UTILS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants - * @{ - */ - -/* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY 0xFFFFFFFFU - -/** - * @brief Unique device ID register base address - */ -#define UID_BASE_ADDRESS UID_BASE - -/** - * @brief Flash size data register base address - */ -#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros - * @{ - */ -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures - * @{ - */ -/** - * @brief UTILS PLL structure definition - */ -typedef struct -{ - uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. - This parameter can be a value of @ref RCC_LL_EC_PLL_MUL - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ - -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. - This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ -#else - uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. - This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -} LL_UTILS_PLLInitTypeDef; - -/** - * @brief UTILS System, AHB and APB buses clock configuration structure definition - */ -typedef struct -{ - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAHBPrescaler(). */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB1_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB1Prescaler(). */ -} LL_UTILS_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants - * @{ - */ - -/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation - * @{ - */ -#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions - * @{ - */ - -/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE - * @{ - */ - -/** - * @brief Get Word0 of the unique device identifier (UID based on 96 bits) - * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format - */ -__STATIC_INLINE uint32_t LL_GetUID_Word0(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); -} - -/** - * @brief Get Word1 of the unique device identifier (UID based on 96 bits) - * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) - */ -__STATIC_INLINE uint32_t LL_GetUID_Word1(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); -} - -/** - * @brief Get Word2 of the unique device identifier (UID based on 96 bits) - * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word2(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); -} - -/** - * @brief Get Flash memory size - * @note This bitfield indicates the size of the device Flash memory expressed in - * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. - * @retval FLASH_SIZE[15:0]: Flash memory size - */ -__STATIC_INLINE uint32_t LL_GetFlashSize(void) -{ - return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); -} - - -/** - * @} - */ - -/** @defgroup UTILS_LL_EF_DELAY DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source of the time base. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks - * @retval None - */ -__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) -{ - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} - -void LL_Init1msTick(uint32_t HCLKFrequency); -void LL_mDelay(uint32_t Delay); - -/** - * @} - */ - -/** @defgroup UTILS_EF_SYSTEM SYSTEM - * @{ - */ - -void LL_SetSystemCoreClock(uint32_t HCLKFrequency); -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -#if defined(RCC_CFGR_SW_HSI48) -ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -#endif /*RCC_CFGR_SW_HSI48*/ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_LL_UTILS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c deleted file mode 100644 index 3bcafc4..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c +++ /dev/null @@ -1,467 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs categories: - (+) HAL Initialization and de-initialization functions - (+) HAL Control functions - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup HAL_Private_Constants HAL Private Constants - * @{ - */ -/** - * @brief STM32F0xx HAL Driver version number V1.7.0 - */ -#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ -#define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ - |(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\ - |(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\ - |(__STM32F0xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK (0x00000FFFU) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup HAL_Private_Macros HAL Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ -__IO uint32_t uwTick; -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout - is needed and the backup domain when enabled. - (+) de-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __Weak - to make override possible in case of other implementations in user file. - -@endverbatim - * @{ - */ - -/** - * @brief This function configures the Flash prefetch, - * Configures time base source, NVIC and Low level hardware - * @note This function is called at the beginning of program after reset and before - * the clock configuration - * @note The time base configuration is based on HSI clock when exiting from Reset. - * Once done, time base tick start incrementing. - * In the default implementation,Systick is used as source of time base. - * The tick variable is incremented each 1ms in its ISR. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the source - * of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB_FORCE_RESET(); - __HAL_RCC_AHB_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __Weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000U); - - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during Sleep mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick++; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note ThiS function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(__IO uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a period to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait++; - } - - while((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) - -{ - /* Disable SysTick Interrupt */ - CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief This method returns the HAL revision - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32F0xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE) >> 16U); -} - -/** - * @brief Returns the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Returns first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Returns second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Returns third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c deleted file mode 100644 index 36d755a..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c +++ /dev/null @@ -1,2186 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_adc.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) - * peripheral: - * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Channels configuration on regular group - * ++ Analog Watchdog configuration - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management - * Other functions (extended functions) are available in file - * "stm32f0xx_hal_adc_ex.c". - * - @verbatim - ============================================================================== - ##### ADC peripheral features ##### - ============================================================================== - [..] - (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution - - (+) Interrupt generation at the end of regular conversion and in case of - analog watchdog or overrun events. - - (+) Single and continuous conversion modes. - - (+) Scan mode for conversion of several channels sequentially. - - (+) Data alignment with in-built data coherency. - - (+) Programmable sampling time (common for all channels) - - (+) ADC conversion of regular group. - - (+) External trigger (timer or EXTI) with configurable polarity - - (+) DMA request generation for transfer of conversions data of regular group. - - (+) ADC calibration - - (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at - slower speed. - - (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to - Vdda or to an external voltage reference). - - - ##### How to use this driver ##### - ============================================================================== - [..] - - *** Configuration of top level parameters related to ADC *** - ============================================================ - [..] - - (#) Enable the ADC interface - (++) As prerequisite, ADC clock must be configured at RCC top level. - Caution: On STM32F0, ADC clock frequency max is 14MHz (refer - to device datasheet). - Therefore, ADC clock prescaler must be configured in - function of ADC clock source frequency to remain below - this maximum frequency. - - (++) Two clock settings are mandatory: - (+++) ADC clock (core clock, also possibly conversion clock). - - (+++) ADC clock (conversions clock). - Two possible clock sources: synchronous clock derived from APB clock - or asynchronous clock derived from ADC dedicated HSI RC oscillator - 14MHz. - If asynchronous clock is selected, parameter "HSI14State" must be set either: - - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control - the HSI14 oscillator enable/disable (if not used to supply the main - system clock): feature used if ADC mode LowPowerAutoPowerOff is - enabled. - - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator - always enabled: can be used to supply the main system clock. - - (+++) Example: - Into HAL_ADC_MspInit() (recommended code location) or with - other device clock parameters configuration: - (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) - - HI14 enable or let under control of ADC: (optional: if asynchronous clock selected) - (+++) RCC_OscInitTypeDef RCC_OscInitStructure; - (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; - (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; - (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) - (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); - - (++) ADC clock source and clock prescaler are configured at ADC level with - parameter "ClockPrescaler" using function HAL_ADC_Init(). - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_ENABLE() - (++) Configure these ADC pins in analog mode - using function HAL_GPIO_Init() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Configure the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding ADC interruption vector - ADCx_IRQHandler(). - - (#) Optionally, in case of usage of DMA: - (++) Configure the DMA (DMA channel, mode normal or circular, ...) - using function HAL_DMA_Init(). - (++) Configure the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding DMA interruption vector - DMAx_Channelx_IRQHandler(). - - *** Configuration of ADC, group regular, channels parameters *** - ================================================================ - [..] - - (#) Configure the ADC parameters (resolution, data alignment, ...) - and regular group parameters (conversion trigger, sequencer, ...) - using function HAL_ADC_Init(). - - (#) Configure the channels for regular group parameters (channel number, - channel rank into sequencer, ..., into regular group) - using function HAL_ADC_ConfigChannel(). - - (#) Optionally, configure the analog watchdog parameters (channels - monitored, thresholds, ...) - using function HAL_ADC_AnalogWDGConfig(). - - *** Execution of ADC conversions *** - ==================================== - [..] - - (#) Optionally, perform an automatic ADC calibration to improve the - conversion accuracy - using function HAL_ADCEx_Calibration_Start(). - - (#) ADC driver can be used among three modes: polling, interruption, - transfer by DMA. - - (++) ADC conversion by polling: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start() - (+++) Wait for ADC conversion completion - using function HAL_ADC_PollForConversion() - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop() - - (++) ADC conversion by interruption: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_IT() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() - (this function must be implemented in user program) - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_IT() - - (++) ADC conversion with transfer by DMA: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_DMA() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() - (these functions must be implemented in user program) - (+++) Conversion results are automatically transferred by DMA into - destination variable address. - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_DMA() - - [..] - - (@) Callback functions must be implemented in user program: - (+@) HAL_ADC_ErrorCallback() - (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) - (+@) HAL_ADC_ConvCpltCallback() - (+@) HAL_ADC_ConvHalfCpltCallback - - *** Deinitialization of ADC *** - ============================================================ - [..] - - (#) Disable the ADC interface - (++) ADC clock can be hard reset and disabled at RCC top level. - (++) Hard reset of ADC peripherals - using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). - (++) ADC clock disable - using the equivalent macro/functions as configuration step. - (+++) Example: - Into HAL_ADC_MspDeInit() (recommended code location) or with - other device clock parameters configuration: - (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; - (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) - (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); - - (#) ADC pins configuration - (++) Disable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_DISABLE() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Disable the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - - (#) Optionally, in case of usage of DMA: - (++) Deinitialize the DMA - using function HAL_DMA_Init(). - (++) Disable the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - - [..] - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ - - /* Fixed timeout values for ADC calibration, enable settling time, disable */ - /* settling time. */ - /* Values defined to be higher than worst cases: low clock frequency, */ - /* maximum prescaler. */ - /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ - /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ - /* Unit: ms */ - #define ADC_ENABLE_TIMEOUT ( 2U) - #define ADC_DISABLE_TIMEOUT ( 2U) - #define ADC_STOP_CONVERSION_TIMEOUT ( 2U) - - /* Delay for ADC stabilization time. */ - /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ - /* Unit: us */ - #define ADC_STAB_DELAY_US ( 1U) - - /* Delay for temperature sensor stabilization time. */ - /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ - /* Unit: us */ - #define ADC_TEMPSENSOR_DELAY_US ( 10U) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ -static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); -static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); -static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC -@endverbatim - * @{ - */ - -/** - * @brief Initializes the ADC peripheral and regular group according to - * parameters specified in structure "ADC_InitTypeDef". - * @note As prerequisite, ADC clock must be configured at RCC top level - * depending on both possible clock sources: APB clock of HSI clock. - * See commented example code below that can be copied and uncommented - * into HAL_ADC_MspInit(). - * @note Possibility to update parameters on the fly: - * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when - * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC - * MSP has to be modified again, HAL_ADC_DeInit() must be called - * before HAL_ADC_Init(). - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments - * of structure "ADC_InitTypeDef". - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR1 = 0U; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); - assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); - - /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ - /* at RCC top level depending on both possible clock sources: */ - /* APB clock or HSI clock. */ - /* Refer to header of this file for more details on clock enabling procedure*/ - - /* Actions performed only if ADC is coming from state reset: */ - /* - Initialization of ADC MSP */ - /* - ADC voltage regulator enable */ - if (hadc->State == HAL_ADC_STATE_RESET) - { - /* Initialize ADC error code */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Allocate lock resource and initialize it */ - hadc->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); - } - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - /* and if there is no conversion on going on regular group (ADC can be */ - /* enabled anyway, in case of call of this function to update a parameter */ - /* on the fly). */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && - (tmp_hal_status == HAL_OK) && - (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - ADC clock mode */ - /* - ADC clock prescaler */ - /* - ADC resolution */ - if (ADC_IS_ENABLE(hadc) == RESET) - { - /* Some parameters of this register are not reset, since they are set */ - /* by other functions and must be kept in case of usage of this */ - /* function on the fly (update of a parameter of ADC_InitTypeDef */ - /* without needing to reconfigure all other ADC groups/channels */ - /* parameters): */ - /* - internal measurement paths: Vbat, temperature sensor, Vref */ - /* (set into HAL_ADC_ConfigChannel() ) */ - - /* Configuration of ADC resolution */ - MODIFY_REG(hadc->Instance->CFGR1, - ADC_CFGR1_RES , - hadc->Init.Resolution ); - - /* Configuration of ADC clock mode: clock source AHB or HSI with */ - /* selectable prescaler */ - MODIFY_REG(hadc->Instance->CFGR2 , - ADC_CFGR2_CKMODE , - hadc->Init.ClockPrescaler ); - } - - /* Configuration of ADC: */ - /* - discontinuous mode */ - /* - LowPowerAutoWait mode */ - /* - LowPowerAutoPowerOff mode */ - /* - continuous conversion mode */ - /* - overrun */ - /* - external trigger to start conversion */ - /* - external trigger polarity */ - /* - data alignment */ - /* - resolution */ - /* - scan direction */ - /* - DMA continuous request */ - hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | - ADC_CFGR1_AUTOFF | - ADC_CFGR1_AUTDLY | - ADC_CFGR1_CONT | - ADC_CFGR1_OVRMOD | - ADC_CFGR1_EXTSEL | - ADC_CFGR1_EXTEN | - ADC_CFGR1_ALIGN | - ADC_CFGR1_SCANDIR | - ADC_CFGR1_DMACFG ); - - tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) | - ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) | - ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) | - ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | - hadc->Init.DataAlign | - ADC_SCANDIR(hadc->Init.ScanConvMode) | - ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); - - /* Enable discontinuous mode only if continuous mode is disabled */ - if (hadc->Init.DiscontinuousConvMode == ENABLE) - { - if (hadc->Init.ContinuousConvMode == DISABLE) - { - /* Enable the selected ADC group regular discontinuous mode */ - tmpCFGR1 |= ADC_CFGR1_DISCEN; - } - else - { - /* ADC regular group discontinuous was intended to be enabled, */ - /* but ADC regular group modes continuous and sequencer discontinuous */ - /* cannot be enabled simultaneously. */ - - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | - hadc->Init.ExternalTrigConvEdge ); - } - - /* Update ADC configuration register with previous settings */ - hadc->Instance->CFGR1 |= tmpCFGR1; - - /* Channel sampling time configuration */ - /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ - /* (obsolete): sampling time set in this function if parameter */ - /* "SamplingTimeCommon" has been set to a valid sampling time. */ - /* Otherwise, sampling time is set into ADC channel initialization */ - /* structure with parameter "SamplingTime" (obsolete). */ - if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) - { - /* Channel sampling time configuration */ - /* Clear the old sample time */ - hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); - - /* Set the new sample time */ - hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); - } - - /* Check back that ADC registers have effectively been configured to */ - /* ensure of no potential problem of ADC core IP clocking. */ - /* Check through register CFGR1 (excluding analog watchdog configuration: */ - /* set into separate dedicated function, and bits of ADC resolution set */ - /* out of temporary variable 'tmpCFGR1'). */ - if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) - == tmpCFGR1) - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set the ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @brief Deinitialize the ADC peripheral registers to their default reset - * values, with deinitialization of the ADC MSP. - * @note For devices with several ADCs: reset of ADC common registers is done - * only if all ADCs sharing the same common group are disabled. - * If this is not the case, reset of these common parameters reset is - * bypassed without error reporting: it can be the intended behaviour in - * case of reset of a single ADC while the other ADCs sharing the same - * common group is still running. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - - /* Stop potential conversion on going, on regular group */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status != HAL_ERROR) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - } - - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (tmp_hal_status != HAL_ERROR) - { - - /* ========== Reset ADC registers ========== */ - /* Reset register IER */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | - ADC_IT_EOS | ADC_IT_EOC | - ADC_IT_EOSMP | ADC_IT_RDY ) ); - - /* Reset register ISR */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_OVR | - ADC_FLAG_EOS | ADC_FLAG_EOC | - ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); - - /* Reset register CR */ - /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ - /* "read-set": no direct reset applicable. */ - - /* Reset register CFGR1 */ - hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN | - ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | - ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | - ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); - - /* Reset register CFGR2 */ - /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ - /* already done above. */ - hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; - - /* Reset register SMPR */ - hadc->Instance->SMPR &= ~ADC_SMPR_SMP; - - /* Reset register TR1 */ - hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); - - /* Reset register CHSELR */ - hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 | - ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 | - ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 | - ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 | - ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ); - - /* Reset register DR */ - /* bits in access mode read only, no direct reset applicable*/ - - /* Reset register CCR */ - ADC->CCR &= ~(ADC_CCR_ALL); - - /* ========== Hard reset ADC peripheral ========== */ - /* Performs a global reset of the entire ADC peripheral: ADC state is */ - /* forced to a similar state after device power-on. */ - /* If needed, copy-paste and uncomment the following reset code into */ - /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ - /* */ - /* __HAL_RCC_ADC1_FORCE_RESET() */ - /* __HAL_RCC_ADC1_RELEASE_RESET() */ - - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @brief Initializes the ADC MSP. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitializes the ADC MSP. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspDeInit must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular group. - (+) Stop conversion of regular group. - (+) Poll for conversion complete on regular group. - (+) Poll for conversion event. - (+) Get result of regular channel conversion. - (+) Start conversion of regular group and enable interruptions. - (+) Stop conversion of regular group and disable interruptions. - (+) Handle ADC interrupt request - (+) Start conversion of regular group and enable DMA transfer. - (+) Stop conversion of regular group and disable ADC DMA transfer. -@endverbatim - * @{ - */ - -/** - * @brief Enables ADC, starts conversion of regular group. - * Interruptions enabled in this function: None. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ - /* performed automatically by hardware. */ - if (hadc->Init.LowPowerAutoPowerOff != ENABLE) - { - tmp_hal_status = ADC_Enable(hadc); - } - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC */ - /* operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - hadc->Instance->CR |= ADC_CR_ADSTART; - } - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group, disable ADC peripheral. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going, on regular group */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Wait for regular group conversion to be completed. - * @note ADC conversion flags EOS (end of sequence) and EOC (end of - * conversion) are cleared by this function, with an exception: - * if low power feature "LowPowerAutoWait" is enabled, flags are - * not cleared to not interfere with this feature until data register - * is read using function HAL_ADC_GetValue(). - * @note This function cannot be used in a particular setup: ADC configured - * in DMA mode and polling for end of each conversion (ADC init - * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). - * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still - * be performed on the complete sequence (ADC init - * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). - * @param hadc ADC handle - * @param Timeout Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t tmp_Flag_EOC; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* If end of conversion selected to end of sequence */ - if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) - { - tmp_Flag_EOC = ADC_FLAG_EOS; - } - /* If end of conversion selected to end of each conversion */ - else /* ADC_EOC_SINGLE_CONV */ - { - /* Verification that ADC configuration is compliant with polling for */ - /* each conversion: */ - /* Particular case is ADC configured in DMA mode and ADC sequencer with */ - /* several ranks and polling for end of each conversion. */ - /* For code simplicity sake, this particular case is generalized to */ - /* ADC configured in DMA mode and and polling for end of each conversion. */ - if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - else - { - tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); - } - } - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Wait until End of Conversion flag is raised */ - while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) - { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - - /* Clear end of conversion flag of regular group if low power feature */ - /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ - /* until data register is read using function HAL_ADC_GetValue(). */ - if (hadc->Init.LowPowerAutoWait == DISABLE) - { - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Poll for conversion event. - * @param hadc ADC handle - * @param EventType the ADC event type. - * This parameter can be one of the following values: - * @arg ADC_AWD_EVENT: ADC Analog watchdog event - * @arg ADC_OVR_EVENT: ADC Overrun event - * @param Timeout Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) -{ - uint32_t tickstart=0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EVENT_TYPE(EventType)); - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Check selected event flag */ - while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - - switch(EventType) - { - /* Analog watchdog (level out of window) event */ - case ADC_AWD_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - break; - - /* Overrun event */ - default: /* Case ADC_OVR_EVENT */ - /* If overrun is set to overwrite previous data, overrun event is not */ - /* considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - } - - /* Clear ADC Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - break; - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Enables ADC, starts conversion of regular group with interruption. - * Interruptions enabled in this function: - * - EOC (end of conversion of regular group) or EOS (end of - * sequence of regular group) depending on ADC initialization - * parameter "EOCSelection" - * - overrun (if available) - * Each of these interruptions has its dedicated callback function. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ - /* performed automatically by hardware. */ - if (hadc->Init.LowPowerAutoPowerOff != ENABLE) - { - tmp_hal_status = ADC_Enable(hadc); - } - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC */ - /* operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Enable ADC end of conversion interrupt */ - /* Enable ADC overrun interrupt */ - switch(hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - break; - } - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - hadc->Instance->CR |= ADC_CR_ADSTART; - } - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @brief Stop ADC conversion of regular group, disable interruption of - * end-of-conversion, disable ADC peripheral. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going, on regular group */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC end of conversion interrupt for regular group */ - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Enables ADC, starts conversion of regular group and transfers result - * through DMA. - * Interruptions enabled in this function: - * - DMA transfer complete - * - DMA half transfer - * - overrun - * Each of these interruptions has its dedicated callback function. - * @param hadc ADC handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from ADC peripheral to memory. - * @retval None - */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ - /* performed automatically by hardware. */ - if (hadc->Init.LowPowerAutoPowerOff != ENABLE) - { - tmp_hal_status = ADC_Enable(hadc); - } - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC */ - /* operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Enable ADC DMA mode */ - hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; - - /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - hadc->Instance->CR |= ADC_CR_ADSTART; - } - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable - * ADC peripheral. - * Each of these interruptions has its dedicated callback function. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going, on regular group */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ - hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN; - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* while DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ - /* in memory a potential failing status. */ - if (tmp_hal_status == HAL_OK) - { - tmp_hal_status = ADC_Disable(hadc); - } - else - { - ADC_Disable(hadc); - } - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Get ADC regular group conversion result. - * @note Reading register DR automatically clears ADC flag EOC - * (ADC group regular end of unitary conversion). - * @note This function does not clear ADC flag EOS - * (ADC group regular end of sequence conversion). - * Occurrence of flag EOS rising: - * - If sequencer is composed of 1 rank, flag EOS is equivalent - * to flag EOC. - * - If sequencer is composed of several ranks, during the scan - * sequence flag EOC only is raised, at the end of the scan sequence - * both flags EOC and EOS are raised. - * To clear this flag, either use function: - * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADC_PollForConversion() - * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc ADC handle - * @retval ADC group regular conversion data - */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Note: EOC flag is not cleared here by software because automatically */ - /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ - return hadc->Instance->DR; -} - -/** - * @brief Handles ADC interrupt request. - * @param hadc ADC handle - * @retval None - */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - - /* ========== Check End of Conversion flag for regular group ========== */ - if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || - (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) - { - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - } - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) - { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - - /* Conversion complete callback */ - /* Note: into callback, to determine if conversion has been triggered */ - /* from EOC or EOS, possibility to use: */ - /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ - HAL_ADC_ConvCpltCallback(hadc); - - - /* Clear regular group conversion flag */ - /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ - /* conversion flags clear induces the release of the preserved data.*/ - /* Therefore, if the preserved data value is needed, it must be */ - /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); - } - - /* ========== Check Analog watchdog flags ========== */ - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Level out of window callback */ - HAL_ADC_LevelOutOfWindowCallback(hadc); - - /* Clear ADC Analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - - } - - - /* ========== Check Overrun flag ========== */ - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) - { - /* If overrun is set to overwrite previous data (default setting), */ - /* overrun event is not considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - /* Exception for usage with DMA overrun event always considered as an */ - /* error. */ - if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || - HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) - { - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - - /* Clear ADC overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - - /* Error callback */ - HAL_ADC_ErrorCallback(hadc); - } - - /* Clear the Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - -} - - -/** - * @brief Conversion complete callback in non blocking mode - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Conversion DMA half-transfer callback in non blocking mode - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog callback in non blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. - */ -} - -/** - * @brief ADC error callback in non blocking mode - * (ADC conversion with interruption or transfer by DMA) - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ErrorCallback must be implemented in the user file. - */ -} - - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on regular group - (+) Configure the analog watchdog - -@endverbatim - * @{ - */ - -/** - * @brief Configures the the selected channel to be linked to the regular - * group. - * @note In case of usage of internal measurement channels: - * VrefInt/Vbat/TempSensor. - * Sampling time constraints must be respected (sampling time can be - * adjusted in function of ADC clock frequency and sampling time - * setting). - * Refer to device datasheet for timings values, parameters TS_vrefint, - * TS_vbat, TS_temp (values rough order: 5us to 17us). - * These internal paths can be be disabled using function - * HAL_ADC_DeInit(). - * @note Possibility to update parameters on the fly: - * This function initializes channel into regular group, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting - * the ADC. - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_ChannelConfTypeDef". - * @param hadc ADC handle - * @param sConfig Structure of ADC channel for regular group. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - __IO uint32_t wait_loop_index = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_RANK(sConfig->Rank)); - - if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) - { - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Channel number */ - /* - Channel sampling time */ - /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Configure channel: depending on rank setting, add it or remove it from */ - /* ADC conversion sequencer. */ - if (sConfig->Rank != ADC_RANK_NONE) - { - /* Regular sequence configuration */ - /* Set the channel selection register from the selected channel */ - hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); - - /* Channel sampling time configuration */ - /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ - /* (obsolete): sampling time set in this function with */ - /* parameter "SamplingTime" (obsolete) only if not already set into */ - /* ADC initialization structure with parameter "SamplingTimeCommon". */ - if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) - { - /* Modify sampling time if needed (not needed in case of reoccurrence */ - /* for several channels programmed consecutively into the sequencer) */ - if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) - { - /* Channel sampling time configuration */ - /* Clear the old sample time */ - hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); - - /* Set the new sample time */ - hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); - } - } - - /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ - /* internal measurement paths enable: If internal channel selected, */ - /* enable dedicated internal buffers and path. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit() or removing the channel from sequencer with */ - /* channel configuration parameter "Rank". */ - if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) - { - /* If Channel_16 is selected, enable Temp. sensor measurement path. */ - /* If Channel_17 is selected, enable VREFINT measurement path. */ - /* If Channel_18 is selected, enable VBAT measurement path. */ - ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); - - /* If Temp. sensor is selected, wait for stabilization delay */ - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - while(wait_loop_index != 0U) - { - wait_loop_index--; - } - } - } - } - else - { - /* Regular sequence configuration */ - /* Reset the channel selection register from the selected channel */ - hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); - - /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ - /* internal measurement paths disable: If internal channel selected, */ - /* disable dedicated internal buffers and path. */ - if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) - { - /* If Channel_16 is selected, disable Temp. sensor measurement path. */ - /* If Channel_17 is selected, disable VREFINT measurement path. */ - /* If Channel_18 is selected, disable VBAT measurement path. */ - ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); - } - } - - } - - /* If a conversion is on going on regular group, no update on regular */ - /* channel could be done on neither of the channel configuration structure */ - /* parameters. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @brief Configures the analog watchdog. - * @note Possibility to update parameters on the fly: - * This function initializes the selected analog watchdog, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting - * the ADC. - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_AnalogWDGConfTypeDef". - * @param hadc ADC handle - * @param AnalogWDGConfig Structure of ADC analog watchdog configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - - /* Verify if threshold is within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); - - if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) - { - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Analog watchdog channels */ - /* - Analog watchdog thresholds */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Configuration of analog watchdog: */ - /* - Set the analog watchdog enable mode: one or overall group of */ - /* channels. */ - /* - Set the Analog watchdog channel (is not used if watchdog */ - /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ - hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | - ADC_CFGR1_AWDEN | - ADC_CFGR1_AWDCH ); - - hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | - ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); - - /* Shift the offset in function of the selected ADC resolution: Thresholds*/ - /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - - /* Set the high and low thresholds */ - hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); - hadc->Instance->TR |= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | - tmpAWDLowThresholdShifted ); - - /* Clear the ADC Analog watchdog flag (in case of left enabled by */ - /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ - /* or HAL_ADC_PollForEvent(). */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD); - - /* Configure ADC Analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) - { - /* Enable the ADC Analog watchdog interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); - } - else - { - /* Disable the ADC Analog watchdog interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); - } - - } - /* If a conversion is on going on regular group, no update could be done */ - /* on neither of the AWD configuration structure parameters. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @} - */ - - -/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions to get in run-time the status of the - peripheral. - (+) Check the ADC state - (+) Check the ADC error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the ADC state - * @note ADC state machine is managed by bitfields, ADC status must be - * compared with states bits. - * For example: - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " - * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " - * @param hadc ADC handle - * @retval HAL state - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Return ADC state */ - return hadc->State; -} - -/** - * @brief Return the ADC error code - * @param hadc ADC handle - * @retval ADC Error Code - */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) -{ - return hadc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @brief Enable the selected ADC. - * @note Prerequisite condition to use this function: ADC must be disabled - * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @note If low power mode AutoPowerOff is enabled, power-on/off phases are - * performed automatically by hardware. - * In this mode, this function is useless and must not be called because - * flag ADC_FLAG_RDY is not usable. - * Therefore, this function must be called under condition of - * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". - * @param hadc ADC handle - * @retval HAL status. - */ -static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) -{ - uint32_t tickstart = 0U; - __IO uint32_t wait_loop_index = 0U; - - /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ - /* enabling phase not yet completed: flag ADC ready not yet set). */ - /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ - /* causes: ADC clock not running, ...). */ - if (ADC_IS_ENABLE(hadc) == RESET) - { - /* Check if conditions to enable the ADC are fulfilled */ - if (ADC_ENABLING_CONDITIONS(hadc) == RESET) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - - /* Enable the ADC peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(wait_loop_index != 0U) - { - wait_loop_index--; - } - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Wait for ADC effectively enabled */ - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief Disable the selected ADC. - * @note Prerequisite condition to use this function: ADC conversions must be - * stopped. - * @param hadc ADC handle - * @retval HAL status. - */ -static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) -{ - uint32_t tickstart = 0U; - - /* Verification if ADC is not already disabled: */ - /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ - /* disabled. */ - if (ADC_IS_ENABLE(hadc) != RESET) - { - /* Check if conditions to disable the ADC are fulfilled */ - if (ADC_DISABLING_CONDITIONS(hadc) != RESET) - { - /* Disable the ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - - /* Wait for ADC effectively disabled */ - /* Get tick count */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) - { - if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - - -/** - * @brief Stop ADC conversion. - * @note Prerequisite condition to use this function: ADC conversions must be - * stopped to disable the ADC. - * @param hadc ADC handle - * @retval HAL status. - */ -static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Verification if ADC is not already stopped on regular group to bypass */ - /* this function if not needed. */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) - { - - /* Stop potential conversion on going on regular group */ - /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ - if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && - HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) - { - /* Stop conversions on regular group */ - hadc->Instance->CR |= ADC_CR_ADSTP; - } - - /* Wait for conversion effectively stopped */ - /* Get tick count */ - tickstart = HAL_GetTick(); - - while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) - { - if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - - } - - /* Return HAL status */ - return HAL_OK; -} - - -/** - * @brief DMA transfer complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) - { - /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) - { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ - if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); - } - else - { - /* Call DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } - -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Half conversion callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); -} - -/** - * @brief DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - - /* Set ADC error code to DMA error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - - /* Error callback */ - HAL_ADC_ErrorCallback(hadc); -} - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c deleted file mode 100644 index a59dd88..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_adc_ex.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) - * peripheral: - * + Operation functions - * ++ Calibration (ADC automatic self-calibration) - * Other functions (generic functions) are available in file - * "stm32f0xx_hal_adc.c". - * - @verbatim - [..] - (@) Sections "ADC peripheral features" and "How to use this driver" are - available in file of generic functions "stm32l1xx_hal_adc.c". - [..] - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup ADCEx ADCEx - * @brief ADC HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup ADCEx_Private_Constants ADCEx Private Constants - * @{ - */ - -/* Fixed timeout values for ADC calibration, enable settling time, disable */ - /* settling time. */ - /* Values defined to be higher than worst cases: low clock frequency, */ - /* maximum prescaler. */ - /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ - /* prescaler 4. */ - /* Unit: ms */ - #define ADC_DISABLE_TIMEOUT 2 - #define ADC_CALIBRATION_TIMEOUT 2U -/** - * @} - */ - -/* Private macros -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions - * @{ - */ - -/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions - * @brief Extended Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Perform the ADC calibration. -@endverbatim - * @{ - */ - -/** - * @brief Perform an ADC automatic self-calibration - * Calibration prerequisite: ADC must be disabled (execute this - * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). - * @note Calibration factor can be read after calibration, using function - * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tickstart = 0U; - uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */ - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Calibration prerequisite: ADC must be disabled. */ - if (ADC_IS_ENABLE(hadc) == RESET) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Disable ADC DMA transfer request during calibration */ - /* Note: Specificity of this STM32 serie: Calibration factor is */ - /* available in data register and also transfered by DMA. */ - /* To not insert ADC calibration factor among ADC conversion data */ - /* in array variable, DMA transfer must be disabled during */ - /* calibration. */ - backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); - CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); - - /* Start ADC calibration */ - hadc->Instance->CR |= ADC_CR_ADCAL; - - tickstart = HAL_GetTick(); - - /* Wait for calibration completion */ - while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) - { - if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - - /* Restore ADC DMA transfer request after calibration */ - SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c deleted file mode 100644 index 5d27d0b..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c +++ /dev/null @@ -1,357 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M0 exceptions are managed by CMSIS functions. - (#) Enable and Configure the priority of the selected IRQ Channels. - The priority can be 0..3. - - -@- Lower priority values gives higher priority. - -@- Priority Order: - (#@) Lowest priority. - (#@) Lowest hardware priority (IRQn position). - - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() - - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - - -@- Negative value of IRQn_Type are not allowed. - - - [..] - *** How to configure Systick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x03). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined - inside the stm32f0xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn External interrupt number . - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) - * @param PreemptPriority The preemption priority for the IRQn channel. - * This parameter can be a value between 0 and 3. - * A lower priority value indicates a higher priority - * @param SubPriority the subpriority level for the IRQ channel. - * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because - * no subpriority supported in Cortex M0 based products. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - NVIC_SetPriority(IRQn,PreemptPriority); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK) functionalities. - - -@endverbatim - * @{ - */ - - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) -{ - /* Get priority for Cortex-M system or device specific interrupts */ - return NVIC_GetPriority(IRQn); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c deleted file mode 100644 index 5c98f40..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c +++ /dev/null @@ -1,905 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is - necessary). Please refer to Reference manual for connection between peripherals - and DMA requests . - - (#) For a given Channel, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, - using HAL_DMA_Init() function. - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA HAL driver. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Channel priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0U; - - /* Check the DMA handle allocation */ - if(NULL == hdma) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Get the CR register value */ - tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ - DMA_CCR_DIR)); - - /* Prepare the DMA Channel configuration */ - tmp |= hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - - /* Initialize DmaBaseAddress and ChannelIndex parameters used - by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ - DMA_CalcBaseAndBitshift(hdma); - - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA peripheral - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - /* Check the DMA handle allocation */ - if(NULL == hdma) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Channelx */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0U; - - /* Reset DMA Channel Number of Data to Transfer register */ - hdma->Instance->CNDTR = 0U; - - /* Reset DMA Channel peripheral address register */ - hdma->Instance->CPAR = 0U; - - /* Reset DMA Channel memory address register */ - hdma->Instance->CMAR = 0U; - -/* Get DMA Base Address */ - DMA_CalcBaseAndBitshift(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - hdma->Instance->CCR |= DMA_CCR_EN; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete, & transfer error interrupts */ - /* Half transfer interrupt is optional: enable it only if associated callback is available */ - if(NULL != hdma->XferHalfCpltCallback ) - { - hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - } - else - { - hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); - hdma->Instance->CCR &= ~DMA_IT_HT; - } - - /* Enable the Peripheral */ - hdma->Instance->CCR |= DMA_CCR_EN; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - - return status; -} - -/** - * @brief Abort the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - /* Disable DMA IT */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - - /* Disable the channel */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); - - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Abort the DMA Transfer in Interrupt mode. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; - } - else - { - - /* Disable DMA IT */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - - /* Disable the channel */ - hdma->Instance->CCR &= ~DMA_CCR_EN; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - } - return status; -} - -/** - * @brief Polling for transfer complete. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CompleteLevel Specifies the DMA level complete. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0U; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode */ - if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if(HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Transfer Complete flag */ - temp = DMA_FLAG_TC1 << hdma->ChannelIndex; - } - else - { - /* Half Transfer Complete flag */ - temp = DMA_FLAG_HT1 << hdma->ChannelIndex; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) - { - if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - } - - if(HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY; - } - else - { - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Handle DMA interrupt request. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t flag_it = hdma->DmaBaseAddress->ISR; - uint32_t source_it = hdma->Instance->CCR; - - /* Half Transfer Complete Interrupt management ******************************/ - if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the half transfer interrupt */ - hdma->Instance->CCR &= ~DMA_IT_HT; - } - - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; - - /* DMA peripheral state is not updated in Half Transfer */ - /* State is updated only in Transfer Complete case */ - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - - /* Transfer Complete Interrupt management ***********************************/ - else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) - { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the transfer complete & transfer error interrupts */ - /* if the DMA mode is not CIRCULAR */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - - /* Transfer Error Interrupt management ***************************************/ - else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Then, disable all DMA interrupts */ - hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } -} - -/** - * @brief Register callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback pointer to private callback function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Returns the DMA state. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - return hdma->State; -} - -/** - * @brief Return the DMA error code - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Set the DMA Transfer parameters. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); - - /* Configure DMA Channel data length */ - hdma->Instance->CNDTR = DataLength; - - /* Memory to Peripheral */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Channel destination address */ - hdma->Instance->CPAR = DstAddress; - - /* Configure DMA Channel source address */ - hdma->Instance->CMAR = SrcAddress; - } - /* Peripheral to Memory */ - else - { - /* Configure DMA Channel source address */ - hdma->Instance->CPAR = SrcAddress; - - /* Configure DMA Channel destination address */ - hdma->Instance->CMAR = DstAddress; - } -} - -/** - * @brief set the DMA base address and channel index depending on DMA instance - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) -{ -#if defined (DMA2) - /* calculation of the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA2; - } -#else - /* calculation of the channel index */ - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; -#endif -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @} - */ - - /** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c deleted file mode 100644 index b7d8d1d..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c +++ /dev/null @@ -1,706 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) Option Bytes programming - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32F0xx devices. - - (#) FLASH Memory I/O Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface - (++) Erase function: Erase page, erase all pages - (++) Program functions: half word, word and doubleword - (#) FLASH Option Bytes Programming functions: this group includes all needed - functions to manage the Option Bytes: - (++) Lock and Unlock the Option Bytes - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user Option Bytes - (++) Launch the Option Bytes loader - (++) Erase Option Bytes - (++) Program the data Option Bytes - (++) Get the Write protection. - (++) Get the user option bytes. - - (#) Interrupts and flags management functions : this group - includes all needed functions to: - (++) Handle FLASH interrupts - (++) Wait for last FLASH operation according to its status - (++) Get error flag status - - [..] In addition to these function, this driver includes a set of macros allowing - to handle the following operations: - - (+) Set/Get the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro ---------------------------- ---------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); -static void FLASH_SetErrorCode(void); -extern void FLASH_PageErase(uint32_t PageAddress); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim -@endverbatim - * @{ - */ - -/** - * @brief Program halfword, word or double word at a specified address - * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @note FLASH should be previously erased before new programmation (only exception to this - * is when 0x0000 is programmed) - * - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address Specifie the address to be programmed. - * @param Data Specifie the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint8_t index = 0U; - uint8_t nbiterations = 0U; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - /* Program halfword (16-bit) at a specified address. */ - nbiterations = 1U; - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - /* Program word (32-bit = 2*16-bit) at a specified address. */ - nbiterations = 2U; - } - else - { - /* Program double word (64-bit = 4*16-bit) at a specified address. */ - nbiterations = 4U; - } - - for (index = 0U; index < nbiterations; index++) - { - FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /* In case of error, stop programation procedure */ - if (status != HAL_OK) - { - break; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program halfword, word or double word at a specified address with interrupt enabled. - * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address Specifie the address to be programmed. - * @param Data Specifie the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - pFlash.Address = Address; - pFlash.Data = Data; - - if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; - /* Program halfword (16-bit) at a specified address. */ - pFlash.DataRemaining = 1U; - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; - /* Program word (32-bit : 2*16-bit) at a specified address. */ - pFlash.DataRemaining = 2U; - } - else - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; - /* Program double word (64-bit : 4*16-bit) at a specified address. */ - pFlash.DataRemaining = 4U; - } - - /* Program halfword (16-bit) at a specified address. */ - FLASH_Program_HalfWord(Address, (uint16_t)Data); - - return status; -} - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t addresstmp = 0U; - - /* Check FLASH operation error flags */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) - { - /* Return the faulty address */ - addresstmp = pFlash.Address; - /* Reset address */ - pFlash.Address = 0xFFFFFFFFU; - - /* Save the Error code */ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(addresstmp); - - /* Stop the procedure ongoing */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - /* Process can continue only if no error detected */ - if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still pages to erase */ - if(pFlash.DataRemaining != 0U) - { - addresstmp = pFlash.Address; - /*Indicate user which sector has been erased */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - - /*Increment sector number*/ - addresstmp = pFlash.Address + FLASH_PAGE_SIZE; - pFlash.Address = addresstmp; - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - - FLASH_PageErase(addresstmp); - } - else - { - /* No more pages to Erase, user callback can be called. */ - /* Reset Sector and stop Erase pages procedure */ - pFlash.Address = addresstmp = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - } - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { - /* Operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - - /* MassErase ended. Return the selected bank */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); - - /* Stop Mass Erase procedure*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - else - { - /* Nb of 16-bit data to program can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0U) - { - /* Increment address to 16-bit */ - pFlash.Address += 2; - addresstmp = pFlash.Address; - - /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16U); - - /* Operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); - } - else - { - /* Program ended. Return the selected address */ - /* FLASH EOP interrupt user callback */ - if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); - } - else - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); - } - - /* Reset Address and stop Program procedure */ - pFlash.Address = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - } - } - - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Operation is completed, disable the PG, PER and MER Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); - - /* Disable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which has been erased - * (if 0xFFFFFFFF, it means that all the selected pages have been erased) - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Mass Erase: No return value expected - * - Pages Erase: Address of the page which returned an error - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK)) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_KEY1); - WRITE_REG(FLASH->KEYR, FLASH_KEY2); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - SET_BIT(FLASH->CR, FLASH_CR_LOCK); - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) - { - /* Authorizes the Option Byte register programming */ - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @note This function will reset automatically the MCU. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to launch the option byte loading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions - * @brief Peripheral errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode The returned value can be: - * @ref FLASH_Error_Codes - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Program a half-word (16-bit) at a specified address. - * @param Address specify the address to be programmed. - * @param Data specify the data to be programmed. - * @retval None - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Proceed to program the new data */ - SET_BIT(FLASH->CR, FLASH_CR_PG); - - /* Write data in the address */ - *(__IO uint16_t*)Address = Data; -} - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operation timeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { - if (Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* There is no error flag set */ - return HAL_OK; -} - - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - uint32_t flags = 0U; - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - flags |= FLASH_FLAG_WRPERR; - } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; - flags |= FLASH_FLAG_PGERR; - } - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(flags); -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c deleted file mode 100644 index 7984891..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c +++ /dev/null @@ -1,1000 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + Extended Initialization/de-initialization functions - * + Extended I/O operation functions - * + Extended Peripheral Control functions - * - @verbatim - ============================================================================== - ##### Flash peripheral extended features ##### - ============================================================================== - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32F0xxx devices. It includes - - (++) Set/Reset the write protection - (++) Program the user Option Bytes - (++) Get the Read protection Level - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @addtogroup FLASH - * @{ - */ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants - * @{ - */ -#define FLASH_POSITION_IWDGSW_BIT 8U -#define FLASH_POSITION_OB_USERDATA0_BIT 16U -#define FLASH_POSITION_OB_USERDATA1_BIT 24U -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -/* Erase operations */ -static void FLASH_MassErase(void); -void FLASH_PageErase(uint32_t PageAddress); - -/* Option bytes control */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); -static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); -static uint32_t FLASH_OB_GetWRP(void); -static uint32_t FLASH_OB_GetRDP(void); -static uint8_t FLASH_OB_GetUser(void); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions - * @brief FLASH Memory Erasing functions - * -@verbatim - ============================================================================== - ##### FLASH Erasing Programming functions ##### - ============================================================================== - - [..] The FLASH Memory Erasing functions, includes the following functions: - (+) @ref HAL_FLASHEx_Erase: return only when erase has been done - (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback - is called with parameter 0xFFFFFFFF - - [..] Any operation of erase should follow these steps: - (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and - program memory access. - (#) Call the desired function to erase page. - (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation). - -@endverbatim - * @{ - */ - - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError pointer to variable that - * contains the configuration information on faulty page in case of error - * (0xFFFFFFFF means that all the pages have been correctly erased) - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t address = 0U; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass Erase requested for Bank1 */ - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Mass erase to be done*/ - FLASH_MassErase(); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - } - } - else - { - /* Page Erase is requested */ - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - - /* Page Erase requested on address located on bank1 */ - /* Wait for last operation to be completed */ - if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFFU; - - /* Erase page by page to be done*/ - for(address = pEraseInit->PageAddress; - address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); - address += FLASH_PAGE_SIZE) - { - FLASH_PageErase(address); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = address; - break; - } - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* If procedure already ongoing, reject the next one */ - if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; - FLASH_MassErase(); - } - else - { - /* Erase by page to be done*/ - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - - pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; - pFlash.DataRemaining = pEraseInit->NbPages; - pFlash.Address = pEraseInit->PageAddress; - - /*Erase 1st page and wait for IT*/ - FLASH_PageErase(pEraseInit->PageAddress); - } - - return status; -} - -/** - * @} - */ - -/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - option bytes operations. - -@endverbatim - * @{ - */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) -{ - uint8_t rdptmp = OB_RDP_LEVEL_0; - HAL_StatusTypeDef status = HAL_ERROR; - - /* Get the actual read protection Option Byte value */ - rdptmp = FLASH_OB_GetRDP(); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* If the previous operation is completed, proceed to erase the option bytes */ - SET_BIT(FLASH->CR, FLASH_CR_OPTER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the OPTER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); - - if(status == HAL_OK) - { - /* Restore the last read protection Option Byte value */ - status = FLASH_OB_RDP_LevelConfig(rdptmp); - } - } - - /* Return the erase status */ - return status; -} - -/** - * @brief Program option bytes - * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) - { - /* Enable of Write protection on the selected page */ - status = FLASH_OB_EnableWRP(pOBInit->WRPPage); - } - else - { - /* Disable of Write protection on the selected page */ - status = FLASH_OB_DisableWRP(pOBInit->WRPPage); - } - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* USER configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { - status = FLASH_OB_UserConfig(pOBInit->USERConfig); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* DATA configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) - { - status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; - - /*Get WRP*/ - pOBInit->WRPPage = FLASH_OB_GetWRP(); - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); -} - -/** - * @brief Get the Option byte user data - * @param DATAAdress Address of the option byte DATA - * This parameter can be one of the following values: - * @arg @ref OB_DATA_ADDRESS_DATA0 - * @arg @ref OB_DATA_ADDRESS_DATA1 - * @retval Value programmed in USER data - */ -uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) -{ - uint32_t value = 0U; - - if (DATAAdress == OB_DATA_ADDRESS_DATA0) - { - /* Get value programmed in OB USER Data0 */ - value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; - } - else - { - /* Get value programmed in OB USER Data1 */ - value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; - } - - return value; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ - -/** - * @brief Full erase of FLASH memory Bank - * - * @retval None - */ -static void FLASH_MassErase(void) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Only bank1 will be erased*/ - SET_BIT(FLASH->CR, FLASH_CR_MER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @brief Enable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WriteProtectPage specifies the page(s) to be write protected. - * The value of this parameter depend on device used within the same series - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFFU; -#if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFFU; -#endif /* OB_WRP1_WRP1 */ -#if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFFU; -#endif /* OB_WRP2_WRP2 */ -#if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFFU; -#endif /* OB_WRP3_WRP3 */ - - /* Check the parameters */ - assert_param(IS_OB_WRP(WriteProtectPage)); - - /* Get current write protected pages and the new pages to be protected ******/ - WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); - -#if defined(OB_WRP_PAGES0TO15MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); -#elif defined(OB_WRP_PAGES0TO31MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#endif /* OB_WRP_PAGES0TO31MASK */ - -#if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); -#elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); -#endif /* OB_WRP_PAGES32TO63MASK */ - -#if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); -#endif /* OB_WRP_PAGES32TO47MASK */ - -#if defined(OB_WRP_PAGES48TO63MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); -#endif /* OB_WRP_PAGES48TO63MASK */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* To be able to write again option byte, need to perform a option byte erase */ - status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) - { - /* Enable write protection */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(OB_WRP0_WRP0) - if(WRP0_Data != 0xFFU) - { - OB->WRP0 &= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP0_WRP0 */ - -#if defined(OB_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFFU)) - { - OB->WRP1 &= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP1_WRP1 */ - -#if defined(OB_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFFU)) - { - OB->WRP2 &= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP2_WRP2 */ - -#if defined(OB_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFFU)) - { - OB->WRP3 &= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP3_WRP3 */ - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - - return status; -} - -/** - * @brief Disable the write protection of the desired pages - * @note An option byte erase is done automatically in this function. - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WriteProtectPage specifies the page(s) to be write unprotected. - * The value of this parameter depend on device used within the same series - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFFU; -#if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFFU; -#endif /* OB_WRP1_WRP1 */ -#if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFFU; -#endif /* OB_WRP2_WRP2 */ -#if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFFU; -#endif /* OB_WRP3_WRP3 */ - - /* Check the parameters */ - assert_param(IS_OB_WRP(WriteProtectPage)); - - /* Get current write protected pages and the new pages to be unprotected ******/ - WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); - -#if defined(OB_WRP_PAGES0TO15MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); -#elif defined(OB_WRP_PAGES0TO31MASK) - WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#endif /* OB_WRP_PAGES0TO31MASK */ - -#if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); -#elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); -#endif /* OB_WRP_PAGES32TO63MASK */ - -#if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); -#endif /* OB_WRP_PAGES32TO47MASK */ - -#if defined(OB_WRP_PAGES48TO63MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); -#elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); -#endif /* OB_WRP_PAGES48TO63MASK */ - - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* To be able to write again option byte, need to perform a option byte erase */ - status = HAL_FLASHEx_OBErase(); - if (status == HAL_OK) - { - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(OB_WRP0_WRP0) - if(WRP0_Data != 0xFFU) - { - OB->WRP0 |= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP0_WRP0 */ - -#if defined(OB_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFFU)) - { - OB->WRP1 |= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP1_WRP1 */ - -#if defined(OB_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFFU)) - { - OB->WRP2 |= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP2_WRP2 */ - -#if defined(OB_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFFU)) - { - OB->WRP3 |= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - } -#endif /* OB_WRP3_WRP3 */ - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - return status; -} - -/** - * @brief Set the read protection level. - * @param ReadProtectLevel specifies the read protection level. - * This parameter can be one of the following values: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - * @arg @ref OB_RDP_LEVEL_2 Full chip protection - * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* If the previous operation is completed, proceed to erase the option bytes */ - SET_BIT(FLASH->CR, FLASH_CR_OPTER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the OPTER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); - - if(status == HAL_OK) - { - /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - - WRITE_REG(OB->RDP, ReadProtectLevel); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - } - - return status; -} - -/** - * @brief Program the FLASH User Option Byte. - * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), - * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). - * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); - assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); - assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); - assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); - assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); - assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); -#if defined(FLASH_OBR_BOOT_SEL) - assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET))); - assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET))); -#endif /* FLASH_OBR_BOOT_SEL */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(FLASH_OBR_BOOT_SEL) - OB->USER = UserConfig; -#else - OB->USER = (UserConfig | 0x88U); -#endif - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface - * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes - * (system reset will occur) - * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param Address specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data specifies the data to be programmed. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Enables the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval The FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (uint32_t)(READ_REG(FLASH->WRPR)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @retval FLASH RDP level - * This parameter can be one of the following values: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - * @arg @ref OB_RDP_LEVEL_2 Full chip protection - */ -static uint32_t FLASH_OB_GetRDP(void) -{ - uint32_t tmp_reg = 0U; - - /* Read RDP level bits */ - tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); - - if (tmp_reg == FLASH_OBR_RDPRT1) - { - return OB_RDP_LEVEL_1; - } - else if (tmp_reg == FLASH_OBR_RDPRT2) - { - return OB_RDP_LEVEL_2; - } - else - { - return OB_RDP_LEVEL_0; - } -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), - * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). - * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). - */ -static uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Erase the specified FLASH memory page - * @param PageAddress FLASH page to erase - * The value of this parameter depend on device used within the same series - * - * @retval None - */ -void FLASH_PageErase(uint32_t PageAddress) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Proceed to erase the page */ - SET_BIT(FLASH->CR, FLASH_CR_PER); - WRITE_REG(FLASH->AR, PageAddress); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c deleted file mode 100644 index 97a64d1..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c +++ /dev/null @@ -1,543 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually - configured by software in several modes: - (++) Input mode - (++) Analog mode - (++) Output mode - (++) Alternate function mode - (++) External interrupt/event lines - - (+) During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - (+) The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral alternate function (AF) connected - to an IO pin at a time. In this way, there can be no conflict between peripherals - sharing the same IO pin. - - (+) All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - (+) The external interrupt/event controller consists of up to 28 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also - recommended to use it to unconfigure pin which was used as an external interrupt - or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG - registers. - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PF0 and PF1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup GPIO_Private_Defines GPIO Private Defines - * @{ - */ -#define GPIO_MODE (0x00000003U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) - -#define GPIO_NUMBER (16U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t temp = 0x00U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != RESET) - { - /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); - - if(iocurrent) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); - GPIOx->AFR[position >> 3U] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2U)); - SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - GPIOx->MODER = temp; - - /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - SET_BIT(temp, GPIO_Init->Speed << (position * 2U)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; - SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); - GPIOx->OTYPER = temp; - } - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2U)); - SET_BIT(temp, (GPIO_Init->Pull) << (position * 2U)); - GPIOx->PUPDR = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); - SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - SET_BIT(temp, iocurrent); - } - EXTI->IMR = temp; - - temp = EXTI->EMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - SET_BIT(temp, iocurrent); - } - EXTI->EMR = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->RTSR = temp; - - temp = EXTI->FTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->FTSR = temp; - } - } - - position++; - } -} - -/** - * @brief De-initialize the GPIOx peripheral registers to their default reset values. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t tmp = 0x00U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != RESET) - { - /* Get current io position */ - iocurrent = GPIO_Pin & (1U << position); - - if (iocurrent) - { - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO Direction in Input Floting Mode */ - CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2U)); - - /* Configure the default Alternate Function in current IO */ - CLEAR_BIT(GPIOx->AFR[position >> 3U], 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - - /* Configure the default value for IO Speed */ - CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - - /* Configure the default value IO Output Type */ - CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; - - /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ - CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2U)); - - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2U]; - tmp &= ((0x0FU) << (4U * (position & 0x03U))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) - { - tmp = (0x0FU) << (4U * (position & 0x03U)); - CLEAR_BIT(SYSCFG->EXTICR[position >> 2U], tmp); - - /* Clear EXTI line configuration */ - CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); - } - } - - position++; - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Read the specified input port pin. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; - } - -/** - * @brief Set or clear the selected data port bit. - * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if (PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } -} - -/** - * @brief Toggle the specified GPIO pin. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the pin to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** -* @brief Locks GPIO Pins configuration registers. -* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, -* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. -* @note The configuration of the locked GPIO pins can no longer be modified -* until the next reset. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @param GPIO_Pin specifies the port bits to be locked. -* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). -* @retval None -*/ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - SET_BIT(tmp, GPIO_Pin); - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Handle EXTI interrupt request. - * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callback. - * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c deleted file mode 100644 index 1319f11..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c +++ /dev/null @@ -1,4868 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c.c - * @author MCD Application Team - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx channel - - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, - Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - - *** Interrupt mode IO sequential operation *** - ============================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and with a final stop condition in both cases - - (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup I2C_Private_Define I2C Private Define - * @{ - */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ - -#define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ - - -/* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) - -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) - -/* Private define Sequential Transfer Options default/reset value */ -#define I2C_NO_OPTION_FRAME (0xFFFF0000U) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions to handle DMA transfer */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - -/* Private functions to handle IT transfer */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); - -/* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); - -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - -/* Private functions to flush TXDR register */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); - -/* Private functions to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if (hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2C_MspInit(hi2c); - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Disable Own Address1 before set the Own Address1 configuration */ - hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Addressing Master mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ - hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Disable Own Address2 before set the Own Address2 configuration */ - hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; - - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Initialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* If 10bit addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Wait until DIR flag is reset Receiver mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Store Last receive data if any */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - do - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - do - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - __IO uint32_t I2C_Trials = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials++ == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - } - while (I2C_Trials < Trials); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If size > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_READ; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Enable the Address Match interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Disable the Address Match interrupt */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - if (hi2c->Mode == HAL_I2C_MODE_MASTER) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Set State at HAL_I2C_STATE_ABORT */ - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - /* Get current IT Flags and IT sources value */ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if (hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C Bus error interrupt occurred ------------------------------------*/ - if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* Call the Error Callback in case of Error detected */ - if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c, hi2c->ErrorCode); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** -* @brief Return the I2C error code. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - if (hi2c->XferCount > 0U) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - - if ((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) - { - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, ITFlags); - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if (hi2c->XferCount > 0U) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - } - else - { - if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) - { - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - } - - /* Check if STOPF is set */ - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - uint32_t xfermode = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - /* Disable TC interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if (hi2c->XferCount != 0U) - { - /* Recover Slave address */ - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - /* So clear Flag NACKF only */ - if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TC flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief I2C Address complete process callback. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint8_t transferdirection = 0U; - uint16_t slaveaddrcode = 0U; - uint16_t ownadd1code = 0U; - uint16_t ownadd2code = 0U; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(ITFlags); - - /* In case of Listen state, need to inform upper layer of address match code event */ - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - transferdirection = I2C_GET_DIR(hi2c); - slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); - ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); - ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - - /* If 10bits addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) - { - slaveaddrcode = ownadd1code; - hi2c->AddrEventCount++; - if (hi2c->AddrEventCount == 2U) - { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0U; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - else - { - slaveaddrcode = ownadd2code; - - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* else 7 bits addressing mode is selected */ - else - { - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* Else clear address flag only */ - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } -} - -/** - * @brief I2C Master sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Slave sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Rx complete callback to inform upper layer of the end of receive process */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Master complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if ((ITFlags & I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set acknowledge error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } -} - -/** - * @brief I2C Slave complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If a DMA is ongoing, Update handle size context */ - if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) - { - hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); - } - - /* All data are not transferred, so set error code accordingly */ - if (hi2c->XferCount != 0U) - { - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - } - else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } - /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Rx Complete callback */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Tx Complete callback */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Listen complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Reset handle parameters */ - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Disable all Interrupts*/ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); -} - -/** - * @brief I2C interrupts error process. - * @param hi2c I2C handle. - * @param ErrorCode Error code to handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) -{ - /* Reset handle parameters */ - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0U; - - /* Set new error code */ - hi2c->ErrorCode |= ErrorCode; - - /* Disable Interrupts */ - if ((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Disable all interrupts, except interrupts related to LISTEN state */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* keep HAL_I2C_STATE_LISTEN if set */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = I2C_Slave_ISR_IT; - } - else - { - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* If state is an abort treatment on goind, don't change state */ - /* This change will be do later */ - if (hi2c->State != HAL_I2C_STATE_ABORT) - { - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; - } - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - } - - /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - else if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief I2C Tx data register flush process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - { - hi2c->Instance->TXDR = 0x00U; - } - - /* Flush TX register if not empty */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } -} - -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C master receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); -} - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief This function handles I2C Communication Timeout. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Wait until STOP Flag is reset */ - /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c I2C handle. - * @param DevAddress Specifies the slave address to be programmed. - * @param Size Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_RELOAD_MODE Enable Reload mode . - * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. - * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. - * @param Request New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. - * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). - * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. - * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. - * @retval None - */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_TRANSFER_MODE(Mode)); - assert_param(IS_TRANSFER_REQUEST(Request)); - - /* Get the CR2 register value */ - tmpreg = hi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - - /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; -} - -/** - * @brief Manage the enabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } - else - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Disable TC and TXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Disable TC and RXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Disable ADDR, NACK and STOP interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_I2C_DISABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c deleted file mode 100644 index 3e139be..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c +++ /dev/null @@ -1,347 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_i2c_ex.c - * @author MCD Application Team - * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C Extended peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### I2C peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32F0xx - devices contains the following additional features - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure Noise Filter and Wake Up Feature - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of I2C Wake Up Mode using the functions : - (++) HAL_I2CEx_EnableWakeUp() - (++) HAL_I2CEx_DisableWakeUp() - (#) Configure the enable or disable of fast mode plus driving capability using the functions : - (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisableFastModePlus() - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2CEx - * @brief I2C Extended HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - (+) Configure Wake Up Feature - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Analog noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter New state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure I2C Digital noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8U; - - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#if defined(I2C_CR1_WUPEN) - -/** - * @brief Enable I2C wakeup from stop mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 |= I2C_CR1_WUPEN; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable I2C wakeup from stop mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#endif - -/** - * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @retval None - */ -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Enable fast mode plus driving capability for selected pin */ - SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be disabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @retval None - */ -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Disable fast mode plus driving capability for selected pin */ - CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c deleted file mode 100644 index 98e94da..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c +++ /dev/null @@ -1,470 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/de-initialization function - * + Peripheral Control function - * - @verbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers when present). - * @note If the HSE divided by 32 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - PWR->CR |= (uint32_t)PWR_CR_DBP; -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers when present). - * @note If the HSE divided by 32 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - PWR->CR &= ~((uint32_t)PWR_CR_DBP); -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** WakeUp pin configuration *** - ================================ - [..] - (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. - (++)WakeUp Pin 1 on PA.00. - (++)WakeUp Pin 2 on PC.13. - (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) - (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) - (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) - (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) - (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) - (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) - - *** Low Power modes configuration *** - ===================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) - function with: - (++) Main regulator ON. - (++) Low Power regulator ON. - (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction - (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction - (+) Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, - when programmed in wakeup mode (the peripheral must be - programmed in wakeup mode and the corresponding interrupt vector - must be enabled in the NVIC) - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. - The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers and Standby circuitry. - The voltage regulator is OFF. - - (+) Entry: - (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop and Standby modes - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. - - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to - configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. - - (+) Comparator auto-wakeup (AWU) from the Stop mode - - (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: - (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) - to be sensitive to to the selected edges (falling, rising or falling - and rising) (Interrupt or Event modes) using the EXTI_Init() function. - (+++) Configure the comparator to generate the event. -@endverbatim - * @{ - */ - -/** - * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. - * This parameter can be value of : - * @ref PWREx_WakeUp_Pins - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Enable the EWUPx pin */ - SET_BIT(PWR->CSR, WakeUpPinx); -} - -/** - * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. - * This parameter can be values of : - * @ref PWREx_WakeUp_Pins - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Disable the EWUPx pin */ - CLEAR_BIT(PWR->CSR, WakeUpPinx); -} - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator Specifies the regulator state in SLEEP mode. - * On STM32F0 devices, this parameter is a dummy value and it is ignored - * as regulator can't be modified in this mode. Parameter is kept for platform - * compatibility. - * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. - * When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters STOP mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator Specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON - * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - - /* Clear PDDS and LPDS bits */ - tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); - - /* Set LPDS bit according to Regulator value */ - tmpreg |= Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC alternate function pins if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - WKUP pins if enabled. - * STM32F0x8 devices, the Stop mode is available, but it is - * aningless to distinguish between voltage regulator in Low power - * mode and voltage regulator in Run mode because the regulator - * not used and the core is supplied directly from an external source. - * Consequently, the Standby mode is not available on those devices. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select STANDBY mode */ - PWR->CR |= (uint32_t)PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - - -/** - * @brief Enables CORTEX M4 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - -/** - * @brief Disables CORTEX M4 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c deleted file mode 100644 index 25174c6..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c +++ /dev/null @@ -1,290 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Extended Initialization and de-initialization functions - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWREx HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup PWREx_Private_Constants PWREx Private Constants - * @{ - */ -#define PVD_MODE_IT (0x00010000U) -#define PVD_MODE_EVT (0x00020000U) -#define PVD_RISING_EDGE (0x00000001U) -#define PVD_FALLING_EDGE (0x00000002U) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions - * @brief Extended Peripheral Control functions - * -@verbatim - - =============================================================================== - ##### Peripheral extended control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions. - (+) The PVD is stopped in Standby mode. - -@- PVD is not available on STM32F030x4/x6/x8 - - *** VDDIO2 Monitor Configuration *** - ==================================== - [..] - (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it - to VREFInt Voltage - (+) This monitor is internally connected to the EXTI line31 - and can generate an interrupt if enabled. This is done through - HAL_PWREx_EnableVddio2Monitor() function. - -@- VDDIO2 is available on STM32F07x/09x/04x - -@endverbatim - * @{ - */ - -#if defined (STM32F031x6) || defined (STM32F051x8) || \ - defined (STM32F071xB) || defined (STM32F091xC) || \ - defined (STM32F042x6) || defined (STM32F072xB) -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - PWR->CR |= (uint32_t)PWR_CR_PVDE; -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - PWR->CR &= ~((uint32_t)PWR_CR_PVDE); -} - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */ - /* defined (STM32F071xB) || defined (STM32F091xC) || */ - /* defined (STM32F042x6) || defined (STM32F072xB) */ - -#if defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) -/** - * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection. - * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint, - an interrupt is generated Irq line 1. - NVIS has to be enable by user. - * @retval None - */ -void HAL_PWREx_EnableVddio2Monitor(void) -{ - __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); - __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE(); -} - -/** - * @brief Disable the Vddio2 Monitor. - * @retval None - */ -void HAL_PWREx_DisableVddio2Monitor(void) -{ - __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); - __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE(); - -} - -/** - * @brief This function handles the PWR Vddio2 monitor interrupt request. - * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). - * @retval None - */ -void HAL_PWREx_Vddio2Monitor_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) - { - /* PWR Vddio2 monitor interrupt user callback */ - HAL_PWREx_Vddio2MonitorCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR Vddio2 Monitor interrupt callback - * @retval None - */ -__weak void HAL_PWREx_Vddio2MonitorCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file - */ -} - -#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ - defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ - defined (STM32F091xC) || defined (STM32F098xx) */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c deleted file mode 100644 index 1293139..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c +++ /dev/null @@ -1,1332 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, - and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; - all peripherals mapped on these buses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB buses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals whose clocks are not - derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) - - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC -* @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, - AHB and APB1). - - [..] Internal/external clock and PLL configuration - (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - The HSI clock can be used also to clock the USART and I2C peripherals. - - (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock - the ADC peripheral. - - (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: - (++) The first output is used to generate the high speed system clock (up to 48 MHz) - (++) The second output is used to generate the clock for the USB FS (48 MHz) - (++) The third output may be used to generate the clock for the TIM, I2C and USART - peripherals (up to 48 MHz) - - (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M0 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL - clock (divided by 2) output on pin (such as PA8 pin). - - [..] System, AHB and APB buses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these buses. You can use - "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: - (++) The FLASH program/erase clock which is always HSI 8MHz clock. - (++) The USB 48 MHz clock which is derived from the PLL VCO clock. - (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. - (++) The I2C clock which can be derived as well from HSI 8MHz clock. - (++) The ADC clock which is derived from PLL output. - (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC - (HSE divided by a programmable prescaler). The System clock (SYSCLK) - frequency must be higher or equal to the RTC clock frequency. - (++) IWDG clock which is always the LSI clock. - - (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, - Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. - - (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and - prefetch is disabled. - @endverbatim - * @{ - */ - -/* - Additional consideration on the SYSCLK based on Latency settings: - +-----------------------------------------------+ - | Latency | SYSCLK clock frequency (MHz) | - |---------------|-------------------------------| - |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | - |---------------|-------------------------------| - |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | - +-----------------------------------------------+ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB, APB1 prescaler set to 1. - * - CSS and MCO1 OFF - * - All interrupts disabled - * @note This function does not modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None - */ -void HAL_RCC_DeInit(void) -{ - /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); - - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ - CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO); - - /* Reset HSEON, CSSON, PLLON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Reset CFGR2 register */ - CLEAR_REG(RCC->CFGR2); - - /* Reset CFGR3 register */ - CLEAR_REG(RCC->CFGR3); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Require to disable power clock if necessary */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*----------------------------- HSI14 Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); - - /* Check the HSI14 State */ - if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) - { - /* Disable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_DISABLE(); - - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI14_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ - __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); - } - else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) - { - /* Enable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_ENABLE(); - - /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ - __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); - } - else - { - /* Disable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_DISABLE(); - - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI14_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - -#if defined(RCC_HSI48_SUPPORT) - /*----------------------------- HSI48 Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); - - /* When the HSI48 is used as system clock it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) - { - return HAL_ERROR; - } - } - else - { - /* Check the HSI48 State */ - if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - { - /* Enable the Internal High Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal High Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } -#endif /* RCC_HSI48_SUPPORT */ - - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, predivider and multiplication factor. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PREDIV, - RCC_OscInitStruct->PLL.PLLMUL); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB buses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency - * The value of this parameter depend on device used within the same series - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The HSI is used (enabled by hardware) as system clock source after - * start-up from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after start-up delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) of the device. */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } -#if defined(RCC_CFGR_SWS_HSI48) - /* HSI48 is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - /* Check the HSI48 ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) - { - return HAL_ERROR; - } - } -#endif /* RCC_CFGR_SWS_HSI48 */ - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#if defined(RCC_CFGR_SWS_HSI48) - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#endif /* RCC_CFGR_SWS_HSI48 */ - else - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * - @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - - @endverbatim - * @{ - */ - -#if defined(RCC_CFGR_MCOPRE) -/** - * @brief Selects the clock source to output on MCO pin. - * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected - * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - @if STM32F042x6 - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F048xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F071xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F072xB - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F078xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F091xC - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elseif STM32F098xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F030x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F030xC - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F031x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F038xx - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F070x6 - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @elif STM32F070xB - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock - @endif - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param RCC_MCODiv specifies the MCO DIV. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock - * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock - * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock - * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock - * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock - * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock - * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock - * @retval None - */ -#else -/** - * @brief Selects the clock source to output on MCO pin. - * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock - * @param RCC_MCODiv specifies the MCO DIV. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @retval None - */ -#endif -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef gpio; - - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* Configure the MCO1 pin in alternate function mode */ - gpio.Mode = GPIO_MODE_AF_PP; - gpio.Speed = GPIO_SPEED_FREQ_HIGH; - gpio.Pull = GPIO_NOPULL; - gpio.Pin = MCO1_PIN; - gpio.Alternate = GPIO_AF0_MCO; - - /* MCO1 Clock Enable */ - MCO1_CLK_ENABLE(); - - HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - - /* Configure the MCO clock source */ - __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON) ; -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ; -} - -/** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) - * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based - * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the - * PLL factor. - * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, - 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; - const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, - 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; - - uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; - uint32_t sysclockfreq = 0U; - - tmpreg = RCC->CFGR; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - { - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ - { - pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; - if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ - pllclk = (HSE_VALUE / prediv) * pllmul; - } -#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) - else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) - { - /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ - pllclk = (HSI48_VALUE / prediv) * pllmul; - } -#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ - else - { -#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) - /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ - pllclk = (HSI_VALUE / prediv) * pllmul; -#else - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (uint32_t)((HSI_VALUE >> 1U) * pllmul); -#endif - } - sysclockfreq = pllclk; - break; - } -#if defined(RCC_CFGR_SWS_HSI48) - case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ - { - sysclockfreq = HSI48_VALUE; - break; - } -#endif /* RCC_CFGR_SWS_HSI48 */ - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - default: /* HSI used as system clock */ - { - sysclockfreq = HSI_VALUE; - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ - | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14; -#if defined(RCC_HSI48_SUPPORT) - RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; -#endif /* RCC_HSI48_SUPPORT */ - - - /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); - - /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - /* Get the HSI14 configuration -----------------------------------------------*/ - if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) - { - RCC_OscInitStruct->HSI14State = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSI14State = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER); - -#if defined(RCC_HSI48_SUPPORT) - /* Get the HSI48 configuration if any-----------------------------------------*/ - RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); -#endif /* RCC_HSI48_SUPPORT */ - - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); - RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * contains the current clock configuration. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(pFLatency != NULL); - - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval none - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c deleted file mode 100644 index d1d1137..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c +++ /dev/null @@ -1,980 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * + Extended Clock Recovery System Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/** @defgroup RCCEx RCCEx - * @brief RCC Extension HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#if defined(CRS) -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -/* Bit position in register */ -#define CRS_CFGR_FELIM_BITNUMBER 16 -#define CRS_CR_TRIM_BITNUMBER 8 -#define CRS_ISR_FECAP_BITNUMBER 16 -/** - * @} - */ -#endif /* CRS */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) are set to their reset values. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals clocks - * (USART, RTC, I2C, CEC and USB). - * - * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t temp_reg = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*---------------------------- RTC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - FlagStatus pwrclkchanged = RESET; - - /* As soon as function is called to change RTC clock source, activation of the - power domain is done. */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = temp_reg; - - /* Wait for LSERDY if LSE was enabled */ - if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - - /* Require to disable power clock if necessary */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*------------------------------- USART1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - } - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - /*----------------------------- USART2 Configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - } -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - /*----------------------------- USART3 Configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - } -#endif /* STM32F091xC || STM32F098xx */ - - /*------------------------------ I2C1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - } - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) - /*------------------------------ USB Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) - { - /* Check the parameters */ - assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); - - /* Configure the USB clock source */ - __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - /*------------------------------ CEC clock Configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) - { - /* Check the parameters */ - assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - - /* Configure the CEC clock source */ - __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); - } -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - - return HAL_OK; -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals clocks - * (USART, RTC, I2C, CEC and USB). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - /* Set all possible values for the extended clock type parameter------------*/ - /* Common part first */ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; - /* Get the RTC configuration --------------------------------------------*/ - PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); - /* Get the USART1 clock configuration --------------------------------------------*/ - PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - /* Get the I2C1 clock source -----------------------------------------------*/ - PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; - /* Get the USART2 clock source ---------------------------------------------*/ - PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F091xC) || defined(STM32F098xx) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; - /* Get the USART3 clock source ---------------------------------------------*/ - PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); -#endif /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; - /* Get the USB clock source ---------------------------------------------*/ - PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ - -#if defined(STM32F042x6) || defined(STM32F048xx)\ - || defined(STM32F051x8) || defined(STM32F058xx)\ - || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ - || defined(STM32F091xC) || defined(STM32F098xx) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; - /* Get the CEC clock source ------------------------------------------------*/ - PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -} - -/** - * @brief Returns the peripheral clock frequency - * @note Returns 0 if peripheral clock is unknown - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - @if STM32F042x6 - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F048xx - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F051x8 - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F058xx - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F070x6 - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - @if STM32F070xB - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - @endif - @if STM32F071xB - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F072xB - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F078xx - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F091xC - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - @if STM32F098xx - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock - @endif - * @retval Frequency in Hz (0: means that no available frequency for the peripheral) - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - /* frequency == 0 : means that no available frequency for the peripheral */ - uint32_t frequency = 0U; - - uint32_t srcclk = 0U; -#if defined(USB) - uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U; -#endif /* USB */ - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - switch (PeriphClk) - { - case RCC_PERIPHCLK_RTC: - { - /* Get the current RTC source */ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - - /* Check if LSE is ready and if RTC clock selection is LSE */ - if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if RTC clock selection is LSI */ - else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ - else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - { - frequency = HSE_VALUE / 32U; - } - break; - } - case RCC_PERIPHCLK_USART1: - { - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); - - /* Check if USART1 clock selection is PCLK1 */ - if (srcclk == RCC_USART1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - /* Check if HSI is ready and if USART1 clock selection is HSI */ - else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if USART1 clock selection is SYSCLK */ - else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - /* Check if LSE is ready and if USART1 clock selection is LSE */ - else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#if defined(RCC_CFGR3_USART2SW) - case RCC_PERIPHCLK_USART2: - { - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); - - /* Check if USART2 clock selection is PCLK1 */ - if (srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - /* Check if HSI is ready and if USART2 clock selection is HSI */ - else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if USART2 clock selection is SYSCLK */ - else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - /* Check if LSE is ready and if USART2 clock selection is LSE */ - else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#endif /* RCC_CFGR3_USART2SW */ -#if defined(RCC_CFGR3_USART3SW) - case RCC_PERIPHCLK_USART3: - { - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); - - /* Check if USART3 clock selection is PCLK1 */ - if (srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - /* Check if HSI is ready and if USART3 clock selection is HSI */ - else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if USART3 clock selection is SYSCLK */ - else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - /* Check if LSE is ready and if USART3 clock selection is LSE */ - else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#endif /* RCC_CFGR3_USART3SW */ - case RCC_PERIPHCLK_I2C1: - { - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - - /* Check if HSI is ready and if I2C1 clock selection is HSI */ - if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if I2C1 clock selection is SYSCLK */ - else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - break; - } -#if defined(USB) - case RCC_PERIPHCLK_USB: - { - /* Get the current USB source */ - srcclk = __HAL_RCC_GET_USB_SOURCE(); - - /* Check if PLL is ready and if USB clock selection is PLL */ - if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) - { - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U; - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - { - /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */ - frequency = (HSE_VALUE/predivfactor) * pllmull; - } -#if defined(RCC_CR2_HSI48ON) - else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) - { - /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */ - frequency = (HSI48_VALUE / predivfactor) * pllmull; - } -#endif /* RCC_CR2_HSI48ON */ - else - { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB) - /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ - frequency = (HSI_VALUE / predivfactor) * pllmull; -#else - /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */ - frequency = (HSI_VALUE >> 1U) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ - } - } -#if defined(RCC_CR2_HSI48ON) - /* Check if HSI48 is ready and if USB clock selection is HSI48 */ - else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY))) - { - frequency = HSI48_VALUE; - } -#endif /* RCC_CR2_HSI48ON */ - break; - } -#endif /* USB */ -#if defined(CEC) - case RCC_PERIPHCLK_CEC: - { - /* Get the current CEC source */ - srcclk = __HAL_RCC_GET_CEC_SOURCE(); - - /* Check if HSI is ready and if CEC clock selection is HSI */ - if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Check if LSE is ready and if CEC clock selection is LSE */ - else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - break; - } -#endif /* CEC */ - default: - { - break; - } - } - return(frequency); -} - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions - * @brief Extended Clock Recovery System Control functions - * -@verbatim - =============================================================================== - ##### Extended Clock Recovery System Control functions ##### - =============================================================================== - [..] - For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: - - (#) In System clock config, HSI48 needs to be enabled - - (#) Enable CRS clock in IP MSP init which will use CRS functions - - (#) Call CRS functions as follows: - (##) Prepare synchronization configuration necessary for HSI48 calibration - (+++) Default values can be set for frequency Error Measurement (reload and error limit) - and also HSI48 oscillator smooth trimming. - (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and synchronization frequencies values - (##) Call function @ref HAL_RCCEx_CRSConfig which - (+++) Reset CRS registers to their default values. - (+++) Configure CRS registers with synchronization configuration - (+++) Enable automatic calibration and frequency error counter feature - Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the - periodic USB SOF will not be generated by the host. No SYNC signal will therefore be - provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock - precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs - should be used as SYNC signal. - - (##) A polling function is provided to wait for complete synchronization - (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() - (+++) According to CRS status, user can decide to adjust again the calibration or continue - application if synchronization is OK - - (#) User can retrieve information related to synchronization in calling function - @ref HAL_RCCEx_CRSGetSynchronizationInfo() - - (#) Regarding synchronization status and synchronization information, user can try a new calibration - in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency - is higher (and that the TRIM value should be decremented). - - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go - through CRS Handler (RCC_IRQn/RCC_IRQHandler) - (++) Call function @ref HAL_RCCEx_CRSConfig() - (++) Enable RCC_IRQn (thanks to NVIC functions) - (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from - HAL_RCCEx_CRS_IRQHandler(): - (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() - (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() - (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() - (+++) @ref HAL_RCCEx_CRS_ErrorCallback() - - (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). - This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) - -@endverbatim - * @{ - */ - -/** - * @brief Start automatic synchronization for polling mode - * @param pInit Pointer on RCC_CRSInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) -{ - uint32_t value = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); - assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); - assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); - assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); - assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); - assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); - - /* CONFIGURATION */ - - /* Before configuration, reset CRS registers to their default values*/ - __HAL_RCC_CRS_FORCE_RESET(); - __HAL_RCC_CRS_RELEASE_RESET(); - - /* Set the SYNCDIV[2:0] bits according to Prescaler value */ - /* Set the SYNCSRC[1:0] bits according to Source value */ - /* Set the SYNCSPOL bit according to Polarity value */ - value = (pInit->Prescaler | pInit->Source | pInit->Polarity); - /* Set the RELOAD[15:0] bits according to ReloadValue value */ - value |= pInit->ReloadValue; - /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); - WRITE_REG(CRS->CFGR, value); - - /* Adjust HSI48 oscillator smooth trimming */ - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER)); - - /* START AUTOMATIC SYNCHRONIZATION*/ - - /* Enable Automatic trimming & Frequency error counter */ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); -} - -/** - * @brief Generate the software synchronization event - * @retval None - */ -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Return synchronization info - * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) -{ - /* Check the parameter */ - assert_param(pSynchroInfo != NULL); - - /* Get the reload value */ - pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - - /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); - - /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); - - /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** -* @brief Wait for CRS Synchronization status. -* @param Timeout Duration of the timeout -* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization -* frequency. -* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. -* @retval Combination of Synchronization status -* This parameter can be a combination of the following values: -* @arg @ref RCC_CRS_TIMEOUT -* @arg @ref RCC_CRS_SYNCOK -* @arg @ref RCC_CRS_SYNCWARN -* @arg @ref RCC_CRS_SYNCERR -* @arg @ref RCC_CRS_SYNCMISS -* @arg @ref RCC_CRS_TRIMOVF -*/ -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) -{ - uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0U; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait for CRS flag or timeout detection */ - do - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - crsstatus = RCC_CRS_TIMEOUT; - } - } - /* Check CRS SYNCOK flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) - { - /* CRS SYNC event OK */ - crsstatus |= RCC_CRS_SYNCOK; - - /* Clear CRS SYNC event OK bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); - } - - /* Check CRS SYNCWARN flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) - { - /* CRS SYNC warning */ - crsstatus |= RCC_CRS_SYNCWARN; - - /* Clear CRS SYNCWARN bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); - } - - /* Check CRS TRIM overflow flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_TRIMOVF; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); - } - - /* Check CRS Error flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_SYNCERR; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); - } - - /* Check CRS SYNC Missed flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) - { - /* CRS SYNC Missed */ - crsstatus |= RCC_CRS_SYNCMISS; - - /* Clear CRS SYNC Missed bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); - } - - /* Check CRS Expected SYNC flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) - { - /* frequency error counter reached a zero value */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); - } - } while(RCC_CRS_NONE == crsstatus); - - return crsstatus; -} - -/** - * @brief Handle the Clock Recovery System interrupt request. - * @retval None - */ -void HAL_RCCEx_CRS_IRQHandler(void) -{ - uint32_t crserror = RCC_CRS_NONE; - /* Get current IT flags and IT sources values */ - uint32_t itflags = READ_REG(CRS->ISR); - uint32_t itsources = READ_REG(CRS->CR); - - /* Check CRS SYNCOK flag */ - if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) - { - /* Clear CRS SYNC event OK flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); - - /* user callback */ - HAL_RCCEx_CRS_SyncOkCallback(); - } - /* Check CRS SYNCWARN flag */ - else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) - { - /* Clear CRS SYNCWARN flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); - - /* user callback */ - HAL_RCCEx_CRS_SyncWarnCallback(); - } - /* Check CRS Expected SYNC flag */ - else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) - { - /* frequency error counter reached a zero value */ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); - - /* user callback */ - HAL_RCCEx_CRS_ExpectedSyncCallback(); - } - /* Check CRS Error flags */ - else - { - if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) - { - if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) - { - crserror |= RCC_CRS_SYNCERR; - } - if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) - { - crserror |= RCC_CRS_SYNCMISS; - } - if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) - { - crserror |= RCC_CRS_TRIMOVF; - } - - /* Clear CRS Error flags */ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - - /* user error callback */ - HAL_RCCEx_CRS_ErrorCallback(crserror); - } - } -} - -/** - * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncOkCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. - * This parameter can be a combination of the following values: - * @arg @ref RCC_CRS_SYNCERR - * @arg @ref RCC_CRS_SYNCMISS - * @arg @ref RCC_CRS_TRIMOVF - * @retval none - */ -__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(Error); - - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file - */ -} - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c deleted file mode 100644 index 545012b..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c +++ /dev/null @@ -1,5495 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending from feature used : - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup TIM_Private_Functions TIM_Private_Functions - * @{ - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * -@verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * -@verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. - (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * -@verbatim - ============================================================================== - ##### Time Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * -@verbatim - ============================================================================== - ##### Time One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim TIM OnePulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * -@verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) -{ - uint32_t tmpsmcr = 0U; - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - - /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim TIM Encoder handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_ALL: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); - - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - default: - break; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - HAL_TIM_PeriodElapsedCallback(htim); - } - } - /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - HAL_TIMEx_BreakCallback(htim); - } - } - /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - HAL_TIM_TriggerCallback(htim); - } - } - /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - HAL_TIMEx_CommutationCallback(htim); - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) -{ - __HAL_LOCK(htim); - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - } - break; - - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if(OutputChannel != InputChannel) - { - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Ouput compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - } - break; - default: - break; - } - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ -return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0U ) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength); - } - break; - default: - break; - } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ -return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0U ) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength); - } - break; - default: - break; - } - - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) -{ - uint32_t tmpsmcr = 0U; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - /* Reset the SMS and TS Bits */ - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - } - break; - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - } - break; - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - } - break; - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - } - break; - case TIM_CLOCKSOURCE_ITR0: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); - } - break; - case TIM_CLOCKSOURCE_ITR1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - case TIM_CLOCKSOURCE_ITR2: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2 = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) - { - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1 : TIM Channel 1 selected - * @arg TIM_CHANNEL_2 : TIM Channel 2 selected - * @arg TIM_CHANNEL_3 : TIM Channel 3 selected - * @arg TIM_CHANNEL_4 : TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0U; - - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ - -} -/** - * @brief Output Compare callback in non blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} -/** - * @brief Input Capture callback in non blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base state - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC state - * @param htim TIM Ouput Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM state - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture state - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode state - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode state - * @param htim TIM Encoder handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup TIM_Private_Functions TIM_Private_Functions - * @{ - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_ErrorCallback(htim); -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_PWM_PulseFinishedCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_IC_CaptureCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_PeriodElapsedCallback(htim); -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_TriggerCallback(htim); -} - -/** - * @brief Time Base configuration - * @param TIMx TIM periheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1 = 0U; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Time Ouput Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4U); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8U); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0U; - uint32_t tmpccer = 0U; - uint32_t tmpcr2 = 0U; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12U); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0U; - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4U); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12U); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0U; - uint32_t tmpccer = 0U; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0 : Internal Trigger 0 - * @arg TIM_TS_ITR1 : Internal Trigger 1 - * @arg TIM_TS_ITR2 : Internal Trigger 2 - * @arg TIM_TS_ITR3 : Internal Trigger 3 - * @arg TIM_TS_TI1F_ED : TI1 Edge Detector - * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2 - * @arg TIM_TS_ETRF : External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) -{ - uint32_t tmpsmcr = 0U; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0U; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1 : TIM Channel 1 - * @arg TIM_CHANNEL_2 : TIM Channel 2 - * @arg TIM_CHANNEL_3 : TIM Channel 3 - * @arg TIM_CHANNEL_4 : TIM Channel 4 - * @param ChannelState specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); -} - - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c deleted file mode 100644 index 729fd89..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c +++ /dev/null @@ -1,2012 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal bread and dead time configuration - * + Time Master and Slave synchronization configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending from feature used : - (++) Complementary Output Compare : HAL_TIM_OC_MspInit() - (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() - (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_hal.h" - -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions - * @{ - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Hall Sensor interface - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: -{ - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0U ) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complemetary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; - } - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - -@endverbatim - * @{ - */ -/** - * @brief Configure the TIM commutation event sequence. - * @note: this function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note: this function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation Interrupt Request */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note: this function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the MMS Bits */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; - - /* Reset the MSM Bit */ - htim->Instance->SMCR &= ~TIM_SMCR_MSM; - /* Set or Reset the MSM Bit */ - htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM14 Remapping input capabilities. - * @param htim TIM handle. - * @param Remap specifies the TIM remapping source. - * This parameter can be one of the following values: - * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO - * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock - * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 - * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - __HAL_LOCK(htim); - - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - /* Set the Timer remapping configuration */ - htim->Instance->OR = Remap; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group8 - * @{ - */ -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined (STM32F098xx) -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @retval None - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - uint32_t tmpsmcr = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Check input state */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} -#endif /* STM32F051x8 || STM32F058xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions - * @brief Extension Callbacks functions - * -@verbatim - ============================================================================== - ##### Extension Callbacks functions ##### - ============================================================================== - [..] - This section provides Extension TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_CommutationCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIMEx_CommutationCallback(htim); -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions - * @brief Extension Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extension Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface state - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup TIMEx_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp = 0U; - - tmp = TIM_CCER_CC1NE << Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << Channel); -} - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c deleted file mode 100644 index 348611f..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c +++ /dev/null @@ -1,412 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_dma.c - * @author MCD Application Team - * @brief DMA LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_dma.h" -#include "stm32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (DMA1) || defined (DMA2) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup DMA_LL_Private_Macros - * @{ - */ -#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ - ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ - ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) - -#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ - ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) - -#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ - ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) - -#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ - ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) - -#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ - ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ - ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) - -#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ - ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ - ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) - -#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) -#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ - ((__VALUE__) == LL_DMA_REQUEST_1) || \ - ((__VALUE__) == LL_DMA_REQUEST_2) || \ - ((__VALUE__) == LL_DMA_REQUEST_3) || \ - ((__VALUE__) == LL_DMA_REQUEST_4) || \ - ((__VALUE__) == LL_DMA_REQUEST_5) || \ - ((__VALUE__) == LL_DMA_REQUEST_6) || \ - ((__VALUE__) == LL_DMA_REQUEST_7) || \ - ((__VALUE__) == LL_DMA_REQUEST_8) || \ - ((__VALUE__) == LL_DMA_REQUEST_9) || \ - ((__VALUE__) == LL_DMA_REQUEST_10) || \ - ((__VALUE__) == LL_DMA_REQUEST_11) || \ - ((__VALUE__) == LL_DMA_REQUEST_12) || \ - ((__VALUE__) == LL_DMA_REQUEST_13) || \ - ((__VALUE__) == LL_DMA_REQUEST_14) || \ - ((__VALUE__) == LL_DMA_REQUEST_15)) -#endif - -#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ - ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ - ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ - ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) - -#if defined (DMA2) -#if defined (DMA2_Channel6) && defined (DMA2_Channel7) -#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ - (((INSTANCE) == DMA2) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7)))) -#else -#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ - (((INSTANCE) == DMA2) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5)))) -#endif -#else -#if defined(DMA1_Channel6) && defined(DMA1_Channel7) -#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7)))) -#elif defined (DMA1_Channel6) -#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6)))) -#else -#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5)))) -#endif /* DMA1_Channel6 && DMA1_Channel7 */ -#endif -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_LL_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the DMA registers to their default reset values. - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 (*) - * @arg @ref LL_DMA_CHANNEL_7 (*) - * - * (*) value not defined in all devices - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA registers are de-initialized - * - ERROR: DMA registers are not de-initialized - */ -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) -{ - DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; - ErrorStatus status = SUCCESS; - - /* Check the DMA Instance DMAx and Channel parameters*/ - assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); - - tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); - - /* Disable the selected DMAx_Channely */ - CLEAR_BIT(tmp->CCR, DMA_CCR_EN); - - /* Reset DMAx_Channely control register */ - LL_DMA_WriteReg(tmp, CCR, 0U); - - /* Reset DMAx_Channely remaining bytes register */ - LL_DMA_WriteReg(tmp, CNDTR, 0U); - - /* Reset DMAx_Channely peripheral address register */ - LL_DMA_WriteReg(tmp, CPAR, 0U); - - /* Reset DMAx_Channely memory address register */ - LL_DMA_WriteReg(tmp, CMAR, 0U); - -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) - /* Reset Request register field for DMAx Channel */ - LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); -#endif - - if (Channel == LL_DMA_CHANNEL_1) - { - /* Reset interrupt pending bits for DMAx Channel1 */ - LL_DMA_ClearFlag_GI1(DMAx); - } - else if (Channel == LL_DMA_CHANNEL_2) - { - /* Reset interrupt pending bits for DMAx Channel2 */ - LL_DMA_ClearFlag_GI2(DMAx); - } - else if (Channel == LL_DMA_CHANNEL_3) - { - /* Reset interrupt pending bits for DMAx Channel3 */ - LL_DMA_ClearFlag_GI3(DMAx); - } - else if (Channel == LL_DMA_CHANNEL_4) - { - /* Reset interrupt pending bits for DMAx Channel4 */ - LL_DMA_ClearFlag_GI4(DMAx); - } - else if (Channel == LL_DMA_CHANNEL_5) - { - /* Reset interrupt pending bits for DMAx Channel5 */ - LL_DMA_ClearFlag_GI5(DMAx); - } - -#if defined(DMA1_Channel6) - else if (Channel == LL_DMA_CHANNEL_6) - { - /* Reset interrupt pending bits for DMAx Channel6 */ - LL_DMA_ClearFlag_GI6(DMAx); - } -#endif -#if defined(DMA1_Channel7) - else if (Channel == LL_DMA_CHANNEL_7) - { - /* Reset interrupt pending bits for DMAx Channel7 */ - LL_DMA_ClearFlag_GI7(DMAx); - } -#endif - else - { - status = ERROR; - } - - return status; -} - -/** - * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. - * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : - * @arg @ref __LL_DMA_GET_INSTANCE - * @arg @ref __LL_DMA_GET_CHANNEL - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 (*) - * @arg @ref LL_DMA_CHANNEL_7 (*) - * - * (*) value not defined in all devices - * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA registers are initialized - * - ERROR: Not applicable - */ -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Check the DMA Instance DMAx and Channel parameters*/ - assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); - - /* Check the DMA parameters from DMA_InitStruct */ - assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); - assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); - assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); - assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); - assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); - assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); - assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) - assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); -#endif - assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); - - /*---------------------------- DMAx CCR Configuration ------------------------ - * Configure DMAx_Channely: data transfer direction, data transfer mode, - * peripheral and memory increment mode, - * data size alignment and priority level with parameters : - * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits - * - Mode: DMA_CCR_CIRC bit - * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit - * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit - * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits - * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits - * - Priority: DMA_CCR_PL[1:0] bits - */ - LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ - DMA_InitStruct->Mode | \ - DMA_InitStruct->PeriphOrM2MSrcIncMode | \ - DMA_InitStruct->MemoryOrM2MDstIncMode | \ - DMA_InitStruct->PeriphOrM2MSrcDataSize | \ - DMA_InitStruct->MemoryOrM2MDstDataSize | \ - DMA_InitStruct->Priority); - - /*-------------------------- DMAx CMAR Configuration ------------------------- - * Configure the memory or destination base address with parameter : - * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits - */ - LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); - - /*-------------------------- DMAx CPAR Configuration ------------------------- - * Configure the peripheral or source base address with parameter : - * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits - */ - LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); - - /*--------------------------- DMAx CNDTR Configuration ----------------------- - * Configure the peripheral base address with parameter : - * - NbData: DMA_CNDTR_NDT[15:0] bits - */ - LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); - -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) - /*--------------------------- DMAx CSELR Configuration ----------------------- - * Configure the DMA request for DMA instance on Channel x with parameter : - * - PeriphRequest: DMA_CSELR[31:0] bits - */ - LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); -#endif - - return SUCCESS; -} - -/** - * @brief Set each @ref LL_DMA_InitTypeDef field to default value. - * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval None - */ -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; - DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; - DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; - DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; - DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; - DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; - DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; - DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct->NbData = 0x00000000U; -#if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) - DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; -#endif - DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c deleted file mode 100644 index 6b943be..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c +++ /dev/null @@ -1,238 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_exti.c - * @author MCD Application Team - * @brief EXTI LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_exti.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Private_Macros - * @{ - */ - -#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) - -#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ - || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ - || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) - - -#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the EXTI registers to their default reset values. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are de-initialized - * - ERROR: not applicable - */ -uint32_t LL_EXTI_DeInit(void) -{ - /* Interrupt mask register set to default reset values */ -#if defined(STM32F030x6) || defined(STM32F031x6) ||defined(STM32F038xx) - LL_EXTI_WriteReg(IMR, 0x0FF40000U); -#elif defined(STM32F070x6) || defined(STM32F042x6) || defined(STM32F048xx) - LL_EXTI_WriteReg(IMR, 0x7FF40000U); -#elif defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) - LL_EXTI_WriteReg(IMR, 0x0F940000U); -#else - LL_EXTI_WriteReg(IMR, 0x7F840000U); -#endif - /* Event mask register set to default reset values */ - LL_EXTI_WriteReg(EMR, 0x00000000U); - /* Rising Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(RTSR, 0x00000000U); - /* Falling Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(FTSR, 0x00000000U); - /* Software interrupt event register set to default reset values */ - LL_EXTI_WriteReg(SWIER, 0x00000000U); - /* Pending register clear */ - LL_EXTI_WriteReg(PR, 0x007BFFFFU); - - return SUCCESS; -} - -/** - * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. - * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are initialized - * - ERROR: not applicable - */ -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - ErrorStatus status = SUCCESS; - /* Check the parameters */ - assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); - assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); - - /* ENABLE LineCommand */ - if (EXTI_InitStruct->LineCommand != DISABLE) - { - assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); - - /* Configure EXTI Lines in range from 0 to 31 */ - if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) - { - switch (EXTI_InitStruct->Mode) - { - case LL_EXTI_MODE_IT: - /* First Disable Event on provided Lines */ - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable IT on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_EVENT: - /* First Disable IT on provided Lines */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Event on provided Lines */ - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_IT_EVENT: - /* Directly Enable IT & Event on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) - { - switch (EXTI_InitStruct->Trigger) - { - case LL_EXTI_TRIGGER_RISING: - /* First Disable Falling Trigger on provided Lines */ - LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Rising Trigger on provided Lines */ - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_FALLING: - /* First Disable Rising Trigger on provided Lines */ - LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Falling Trigger on provided Lines */ - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_RISING_FALLING: - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - } - } - } - /* DISABLE LineCommand */ - else - { - /* De-configure EXTI Lines in range from 0 to 31 */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - } - return status; -} - -/** - * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. - * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval None - */ -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; - EXTI_InitStruct->LineCommand = DISABLE; - EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; - EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (EXTI) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c deleted file mode 100644 index b1a6bdb..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c +++ /dev/null @@ -1,279 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_gpio.c - * @author MCD Application Team - * @brief GPIO LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_gpio.h" -#include "stm32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) - -/** @addtogroup GPIO_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Private_Macros - * @{ - */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) - -#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ - ((__VALUE__) == LL_GPIO_MODE_ANALOG)) - -#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ - ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) - -#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) - -#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ - ((__VALUE__) == LL_GPIO_PULL_UP) ||\ - ((__VALUE__) == LL_GPIO_PULL_DOWN)) - -#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ - ((__VALUE__) == LL_GPIO_AF_1 ) ||\ - ((__VALUE__) == LL_GPIO_AF_2 ) ||\ - ((__VALUE__) == LL_GPIO_AF_3 ) ||\ - ((__VALUE__) == LL_GPIO_AF_4 ) ||\ - ((__VALUE__) == LL_GPIO_AF_5 ) ||\ - ((__VALUE__) == LL_GPIO_AF_6 ) ||\ - ((__VALUE__) == LL_GPIO_AF_7 )) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize GPIO registers (Registers restored to their default values). - * @param GPIOx GPIO Port - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are de-initialized - * - ERROR: Wrong GPIO Port - */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Force and Release reset on clock of GPIOx Port */ - if (GPIOx == GPIOA) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); - } - else if (GPIOx == GPIOB) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); - } - else if (GPIOx == GPIOC) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); - } -#if defined(GPIOD) - else if (GPIOx == GPIOD) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); - } -#endif /* GPIOD */ -#if defined(GPIOE) - else if (GPIOx == GPIOE) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); - } -#endif /* GPIOE */ -#if defined(GPIOF) - else if (GPIOx == GPIOF) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); - } -#endif /* GPIOF */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. - * @param GPIOx GPIO Port - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * that contains the configuration information for the specified GPIO peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content - * - ERROR: Not applicable - */ -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t pinpos = 0x00000000U; - uint32_t currentpin = 0x00000000U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); - assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); - assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); - - /* ------------------------- Configure the port pins ---------------- */ - /* Initialize pinpos on first pin set */ - /* pinpos = 0; useless as already done in default initialization */ - - /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) - { - /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); - - if (currentpin) - { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Speed mode parameters */ - assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); - - /* Speed mode configuration */ - LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); - } - - /* Pull-up Pull down resistor configuration*/ - LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); - - if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) - { - /* Check Alternate parameter */ - assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); - - /* Speed mode configuration */ - if (currentpin < LL_GPIO_PIN_8) - { - LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - else - { - LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - } - } - pinpos++; - } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } - return (SUCCESS); -} - -/** - * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; - GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; - GPIO_InitStruct->Alternate = LL_GPIO_AF_0; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c deleted file mode 100644 index fc2fe50..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c +++ /dev/null @@ -1,599 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_rcc.c - * @author MCD Application Team - * @brief RCC LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_rcc.h" -#ifdef USE_FULL_ASSERT - #include "stm32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_LL_Private_Macros - * @{ - */ -#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) -#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) -#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) -#else -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) -#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ - -#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) - -#if defined(USB) -#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) -#endif /* USB */ - -#if defined(CEC) -#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) -#endif /* CEC */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_LL_Private_Functions RCC Private functions - * @{ - */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_PLL_GetFreqDomain_SYS(void); -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_LL_EF_Init - * @{ - */ - -/** - * @brief Reset the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB and APB1 prescaler set to 1. - * - CSS, MCO OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RCC registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_RCC_DeInit(void) -{ - uint32_t vl_mask = 0U; - - /* Set HSION bit */ - LL_RCC_HSI_Enable(); - - /* Set HSITRIM bits to the reset value*/ - LL_RCC_HSI_SetCalibTrimming(0x10U); - - /* Reset SW, HPRE, PPRE and MCOSEL bits */ - vl_mask = 0xFFFFFFFFU; - CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL)); - LL_RCC_WriteReg(CFGR, vl_mask); - - /* Reset HSEON, CSSON, PLLON bits */ - vl_mask = 0xFFFFFFFFU; - CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); - LL_RCC_WriteReg(CR, vl_mask); - - /* Reset HSEBYP bit */ - LL_RCC_HSE_DisableBypass(); - - /* Reset CFGR register */ - LL_RCC_WriteReg(CFGR, 0x00000000U); - -#if defined(RCC_HSI48_SUPPORT) - /* Reset CR2 register */ - LL_RCC_WriteReg(CR2, 0x00000000U); - - /* Disable HSI48 */ - LL_RCC_HSI48_Disable(); - -#endif /*RCC_HSI48_SUPPORT*/ - /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/ - LL_RCC_HSI14_SetCalibTrimming(0x10U); - LL_RCC_HSI14_Disable(); - LL_RCC_HSI14_EnableADCControl(); - - /* Reset CFGR2 register */ - LL_RCC_WriteReg(CFGR2, 0x00000000U); - - /* Reset CFGR3 register */ - LL_RCC_WriteReg(CFGR3, 0x00000000U); - - /* Clear pending flags */ -#if defined(RCC_HSI48_SUPPORT) - vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC); -#else - vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC); -#endif /* RCC_HSI48_SUPPORT */ - SET_BIT(RCC->CIR, vl_mask); - - /* Disable all interrupts */ - LL_RCC_WriteReg(CIR, 0x00000000U); - - return SUCCESS; -} - -/** - * @} - */ - -/** @addtogroup RCC_LL_EF_Get_Freq - * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks - * and different peripheral clocks available on the device. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) - * @note If SYSCLK source is PLL, function returns values based on - * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. - * @note (**) HSI_VALUE is a defined constant but the real value may vary - * depending on the variations in voltage and temperature. - * @note (***) HSE_VALUE is a defined constant, user has to ensure that - * HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * @note The result of this function could be incorrect when using fractional - * value for HSE crystal. - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * @{ - */ - -/** - * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks - * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function - * must be called to update structure fields. Otherwise, any - * configuration based on this function will be incorrect. - * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies - * @retval None - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) -{ - /* Get SYSCLK frequency */ - RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); - - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); - - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); -} - -/** - * @brief Return USARTx clock frequency - * @param USARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE (*) - * - * (*) value not defined in all devices. - * @retval USART clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready - */ -uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) -{ - uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); -#if defined(RCC_CFGR3_USART1SW) - if (USARTxSource == LL_RCC_USART1_CLKSOURCE) - { - /* USART1CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } -#endif /* RCC_CFGR3_USART1SW */ - -#if defined(RCC_CFGR3_USART2SW) - if (USARTxSource == LL_RCC_USART2_CLKSOURCE) - { - /* USART2CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } -#endif /* RCC_CFGR3_USART2SW */ - -#if defined(RCC_CFGR3_USART3SW) - if (USARTxSource == LL_RCC_USART3_CLKSOURCE) - { - /* USART3CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - -#endif /* RCC_CFGR3_USART3SW */ - return usart_frequency; -} - -/** - * @brief Return I2Cx clock frequency - * @param I2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @retval I2C clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready - */ -uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) -{ - uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); - - /* I2C1 CLK clock frequency */ - if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) - { - switch (LL_RCC_GetI2CClockSource(I2CxSource)) - { - case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ - i2c_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ - default: - if (LL_RCC_HSI_IsReady()) - { - i2c_frequency = HSI_VALUE; - } - break; - } - } - - return i2c_frequency; -} - -#if defined(USB) -/** - * @brief Return USBx clock frequency - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval USB clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected - */ -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) -{ - uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); - - /* USBCLK clock frequency */ - switch (LL_RCC_GetUSBClockSource(USBxSource)) - { - case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady()) - { - usb_frequency = RCC_PLL_GetFreqDomain_SYS(); - } - break; - -#if defined(RCC_CFGR3_USBSW_HSI48) - case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ - default: - if (LL_RCC_HSI48_IsReady()) - { - usb_frequency = HSI48_VALUE; - } - break; -#else - case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ - default: - usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - break; -#endif /* RCC_CFGR3_USBSW_HSI48 */ - } - - return usb_frequency; -} -#endif /* USB */ - -#if defined(CEC) -/** - * @brief Return CECx clock frequency - * @param CECxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE - * @retval CEC clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready - */ -uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) -{ - uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); - - /* CECCLK clock frequency */ - switch (LL_RCC_GetCECClockSource(CECxSource)) - { - case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ - if (LL_RCC_HSI_IsReady()) - { - cec_frequency = HSI_VALUE / 244U; - } - break; - - case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ - default: - if (LL_RCC_LSE_IsReady()) - { - cec_frequency = LSE_VALUE; - } - break; - } - - return cec_frequency; -} -#endif /* CEC */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup RCC_LL_Private_Functions - * @{ - */ - -/** - * @brief Return SYSTEM clock frequency - * @retval SYSTEM clock frequency (in Hz) - */ -uint32_t RCC_GetSystemClockFreq(void) -{ - uint32_t frequency = 0U; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (LL_RCC_GetSysClkSource()) - { - case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - frequency = HSI_VALUE; - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ - frequency = HSE_VALUE; - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ - frequency = RCC_PLL_GetFreqDomain_SYS(); - break; - -#if defined(RCC_HSI48_SUPPORT) - case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */ - frequency = HSI48_VALUE; - break; -#endif /* RCC_HSI48_SUPPORT */ - - default: - frequency = HSI_VALUE; - break; - } - - return frequency; -} - -/** - * @brief Return HCLK clock frequency - * @param SYSCLK_Frequency SYSCLK clock frequency - * @retval HCLK clock frequency (in Hz) - */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) -{ - /* HCLK clock frequency */ - return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); -} - -/** - * @brief Return PCLK1 clock frequency - * @param HCLK_Frequency HCLK clock frequency - * @retval PCLK1 clock frequency (in Hz) - */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) -{ - /* PCLK1 clock frequency */ - return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); -} -/** - * @brief Return PLL clock frequency used for system domain - * @retval PLL clock frequency (in Hz) - */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ - - /* Get PLL source */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE; -#else - case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE / 2U; -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ - break; - -#if defined(RCC_HSI48_SUPPORT) - case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */ - pllinputfreq = HSI48_VALUE; - break; -#endif /* RCC_HSI48_SUPPORT */ - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - pllinputfreq = HSI_VALUE; -#else - pllinputfreq = HSI_VALUE / 2U; -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ - break; - } -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); -#else - return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); -#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usart.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usart.c deleted file mode 100644 index 6ea0b69..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usart.c +++ /dev/null @@ -1,529 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_usart.c - * @author MCD Application Team - * @brief USART LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_usart.h" -#include "stm32f0xx_ll_rcc.h" -#include "stm32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) || defined (USART7) || defined (USART8) - -/** @addtogroup USART_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Constants - * @{ - */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Macros - * @{ - */ - -/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available - * divided by the smallest oversampling used on the USART (i.e. 8) */ -#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U) - -/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ -#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) - -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - -#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) - -#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) - -#if defined(USART_7BITS_SUPPORT) -#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) -#else -#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) -#endif - -#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) - -#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) - -#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) - -#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) - -#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) - -#if defined(USART_SMARTCARD_SUPPORT) -#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) -#else -#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) -#endif - -#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USART_LL_Exported_Functions - * @{ - */ - -/** @addtogroup USART_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize USART registers (Registers restored to their default values). - * @param USARTx USART Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers are de-initialized - * - ERROR: USART registers are not de-initialized - */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - - if (USARTx == USART1) - { - /* Force reset of USART clock */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1); - - /* Release reset of USART clock */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1); - } -#if defined(USART2) - else if (USARTx == USART2) - { - /* Force reset of USART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); - - /* Release reset of USART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); - } -#endif /* USART2 */ -#if defined(USART3) - else if (USARTx == USART3) - { - /* Force reset of USART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); - - /* Release reset of USART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); - } -#endif /* USART3 */ -#if defined(USART4) - else if (USARTx == USART4) - { - /* Force reset of USART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4); - - /* Release reset of USART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4); - } -#endif /* USART4 */ -#if defined(USART5) - else if (USARTx == USART5) - { - /* Force reset of USART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5); - - /* Release reset of USART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5); - } -#endif /* USART5 */ -#if defined(USART6) - else if (USARTx == USART6) - { - /* Force reset of USART clock */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART6); - - /* Release reset of USART clock */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART6); - } -#endif /* USART6 */ -#if defined(USART7) - else if (USARTx == USART7) - { - /* Force reset of USART clock */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART7); - - /* Release reset of USART clock */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART7); - } -#endif /* USART7 */ -#if defined(USART8) - else if (USARTx == USART8) - { - /* Force reset of USART clock */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART8); - - /* Release reset of USART clock */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART8); - } -#endif /* USART8 */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize USART registers according to the specified - * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). - * @param USARTx USART Instance - * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers are initialized according to USART_InitStruct content - * - ERROR: Problem occurred during USART Registers initialization - */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) -{ - ErrorStatus status = ERROR; - uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; -#if defined(STM32F030x8) || defined(STM32F030xC) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) - LL_RCC_ClocksTypeDef RCC_Clocks; -#endif - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); - assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); - assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); - assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); - assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); - assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); - assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); - - /* USART needs to be in disabled state, in order to be able to configure some bits in - CRx registers */ - if (LL_USART_IsEnabled(USARTx) == 0U) - { - /*---------------------------- USART CR1 Configuration --------------------- - * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: - * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value - * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value - * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value - * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. - */ - MODIFY_REG(USARTx->CR1, - (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), - (USART_InitStruct->DataWidth | USART_InitStruct->Parity | - USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); - - /*---------------------------- USART CR2 Configuration --------------------- - * Configure USARTx CR2 (Stop bits) with parameters: - * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. - * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). - */ - LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); - - /*---------------------------- USART CR3 Configuration --------------------- - * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. - */ - LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); - - /*---------------------------- USART BRR Configuration --------------------- - * Retrieve Clock frequency used for USART Peripheral - */ - if (USARTx == USART1) - { - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); - } -#if defined(USART2) - else if (USARTx == USART2) - { -#if defined (RCC_CFGR3_USART2SW) - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); -#else - /* USART2 clock is PCLK */ - LL_RCC_GetSystemClocksFreq(&RCC_Clocks); - periphclk = RCC_Clocks.PCLK1_Frequency; -#endif - } -#endif /* USART2 */ -#if defined(USART3) - else if (USARTx == USART3) - { -#if defined (RCC_CFGR3_USART3SW) - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE); -#else - /* USART3 clock is PCLK */ - LL_RCC_GetSystemClocksFreq(&RCC_Clocks); - periphclk = RCC_Clocks.PCLK1_Frequency; -#endif - } -#endif /* USART3 */ -#if defined(USART4) - else if (USARTx == USART4) - { - /* USART4 clock is PCLK */ - LL_RCC_GetSystemClocksFreq(&RCC_Clocks); - periphclk = RCC_Clocks.PCLK1_Frequency; - } -#endif /* USART4 */ -#if defined(USART5) - else if (USARTx == USART5) - { - /* USART5 clock is PCLK */ - LL_RCC_GetSystemClocksFreq(&RCC_Clocks); - periphclk = RCC_Clocks.PCLK1_Frequency; - } -#endif /* USART5 */ -#if defined(USART6) - else if (USARTx == USART6) - { - /* USART6 clock is PCLK */ - LL_RCC_GetSystemClocksFreq(&RCC_Clocks); - periphclk = RCC_Clocks.PCLK1_Frequency; - } -#endif /* USART6 */ -#if defined(USART7) - else if (USARTx == USART7) - { - /* USART7 clock is PCLK */ - LL_RCC_GetSystemClocksFreq(&RCC_Clocks); - periphclk = RCC_Clocks.PCLK1_Frequency; - } -#endif /* USART7 */ -#if defined(USART8) - else if (USARTx == USART8) - { - /* USART8 clock is PCLK */ - LL_RCC_GetSystemClocksFreq(&RCC_Clocks); - periphclk = RCC_Clocks.PCLK1_Frequency; - } -#endif /* USART8 */ - else - { - /* Nothing to do, as error code is already assigned to ERROR value */ - } - - /* Configure the USART Baud Rate : - - valid baud rate value (different from 0) is required - - Peripheral clock as returned by RCC service, should be valid (different from 0). - */ - if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) - && (USART_InitStruct->BaudRate != 0U)) - { - status = SUCCESS; - LL_USART_SetBaudRate(USARTx, - periphclk, - USART_InitStruct->OverSampling, - USART_InitStruct->BaudRate); - - /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); - } - } - /* Endif (=> USART not in Disabled state => return ERROR) */ - - return (status); -} - -/** - * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) -{ - /* Set USART_InitStruct fields to default values */ - USART_InitStruct->BaudRate = 9600U; - USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; - USART_InitStruct->StopBits = LL_USART_STOPBITS_1; - USART_InitStruct->Parity = LL_USART_PARITY_NONE ; - USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; - USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; - USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; -} - -/** - * @brief Initialize USART Clock related settings according to the - * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param USARTx USART Instance - * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure - * that contains the Clock configuration information for the specified USART peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content - * - ERROR: Problem occurred during USART Registers initialization - */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check USART Instance and Clock signal output parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); - - /* USART needs to be in disabled state, in order to be able to configure some bits in - CRx registers */ - if (LL_USART_IsEnabled(USARTx) == 0U) - { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); - - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } - } - /* Else (USART not in Disabled state => return ERROR */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - /* Set LL_USART_ClockInitStruct fields with default values */ - USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2|| USART3 || USART4 || USART5 || USART6 || USART7 || USART8 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c deleted file mode 100644 index c48809e..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c +++ /dev/null @@ -1,620 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_ll_utils.c - * @author MCD Application Team - * @brief UTILS LL module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f0xx_ll_rcc.h" -#include "stm32f0xx_ll_utils.h" -#include "stm32f0xx_ll_system.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F0xx_LL_Driver - * @{ - */ - -/** @addtogroup UTILS_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Constants - * @{ - */ - -/* Defines used for PLL range */ -#define UTILS_PLL_OUTPUT_MIN 16000000U /*!< Frequency min for PLL output, in Hz */ -#define UTILS_PLL_OUTPUT_MAX 48000000U /*!< Frequency max for PLL output, in Hz */ - -/* Defines used for HSE range */ -#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ -#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ - -/* Defines used for FLASH latency according to SYSCLK Frequency */ -#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Macros - * @{ - */ -#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) - -#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_16)) - -#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ - || ((__VALUE__) == LL_RCC_PLL_MUL_16)) - -#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ - ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) - -#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((UTILS_PLL_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)) - - -#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ - || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) - -#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Functions UTILS Private functions - * @{ - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -#if defined(FLASH_ACR_LATENCY) -static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); -#endif /* FLASH_ACR_LATENCY */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -static ErrorStatus UTILS_PLL_IsBusy(void); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Exported_Functions - * @{ - */ - -/** @addtogroup UTILS_LL_EF_DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param HCLKFrequency HCLK frequency in Hz - * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq - * @retval None - */ -void LL_Init1msTick(uint32_t HCLKFrequency) -{ - /* Use frequency provided in argument */ - LL_InitTick(HCLKFrequency, 1000U); -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on SysTick counter flag - * @note When a RTOS is used, it is recommended to avoid using blocking delay - * and use rather osDelay service. - * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which - * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -void LL_mDelay(uint32_t Delay) -{ - __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ - /* Add this code to indicate that local variable is not used */ - ((void)tmp); - - /* Add a period to guaranty minimum wait */ - if (Delay < LL_MAX_DELAY) - { - Delay++; - } - - while (Delay) - { - if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) - { - Delay--; - } - } -} - -/** - * @} - */ - -/** @addtogroup UTILS_EF_SYSTEM - * @brief System Configuration functions - * - @verbatim - =============================================================================== - ##### System Configuration functions ##### - =============================================================================== - [..] - System, AHB and APB buses clocks configuration - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 48000000 Hz. - @endverbatim - @internal - Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: - (++) +-----------------------------------------------+ - (++) | Latency | SYSCLK clock frequency (MHz) | - (++) |---------------|-------------------------------| - (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | - (++) |---------------|-------------------------------| - (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | - (++) +-----------------------------------------------+ - @endinternal - * @{ - */ - -/** - * @brief This function sets directly SystemCoreClock CMSIS variable. - * @note Variable can be calculated also through SystemCoreClockUpdate function. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @retval None - */ -void LL_SetSystemCoreClock(uint32_t HCLKFrequency) -{ - /* HCLK clock frequency */ - SystemCoreClock = HCLKFrequency; -} - -/** - * @brief This function configures system clock with HSI as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) - * - PREDIV: Set to 2 for few devices - * - PLLMUL: The application software must set correctly the PLL multiplication factor to - * be in the range 16-48MHz - * @note FLASH latency can be modified through this function. - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - /* Check PREDIV value */ - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); -#else - /* Force PREDIV value to 2 */ - UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); - - /* Enable HSI if not enabled */ - if (LL_RCC_HSI_IsReady() != 1U) - { - LL_RCC_HSI_Enable(); - while (LL_RCC_HSI_IsReady() != 1U) - { - /* Wait for HSI ready */ - } - } - - /* Configure PLL */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -#if defined(RCC_CFGR_SW_HSI48) -/** - * @brief This function configures system clock with HSI48 as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = ((HSI48 frequency / PREDIV) * PLLMUL) - * - PLLMUL: The application software must set correctly the PLL multiplication factor to - * be in the range 16-48MHz - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Check PREDIV value */ - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); - - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSI48_VALUE, UTILS_PLLInitStruct); - - /* Enable HSI48 if not enabled */ - if (LL_RCC_HSI48_IsReady() != 1U) - { - LL_RCC_HSI48_Enable(); - while (LL_RCC_HSI48_IsReady() != 1U) - { - /* Wait for HSI48 ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -#endif /*RCC_CFGR_SW_HSI48*/ -/** - * @brief This function configures system clock with HSE as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = ((HSE frequency / PREDIV) * PLLMUL) - * - PLLMUL: The application software must set correctly the PLL multiplication factor to - * be in the range 16-48MHz - * @note FLASH latency can be modified through this function. - * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000 - * @param HSEBypass This parameter can be one of the following values: - * @arg @ref LL_UTILS_HSEBYPASS_ON - * @arg @ref LL_UTILS_HSEBYPASS_OFF - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); - assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Check PREDIV value */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); -#else - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); - - /* Enable HSE if not enabled */ - if (LL_RCC_HSE_IsReady() != 1U) - { - /* Check if need to enable HSE bypass feature or not */ - if (HSEBypass == LL_UTILS_HSEBYPASS_ON) - { - LL_RCC_HSE_EnableBypass(); - } - else - { - LL_RCC_HSE_DisableBypass(); - } - - /* Enable HSE */ - LL_RCC_HSE_Enable(); - while (LL_RCC_HSE_IsReady() != 1U) - { - /* Wait for HSE ready */ - } - } - - /* Configure PLL */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UTILS_LL_Private_Functions - * @{ - */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param Frequency SYSCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -#if defined(FLASH_ACR_LATENCY) -static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if (Frequency == 0U) - { - status = ERROR; - } - else - { - if (Frequency > UTILS_LATENCY1_FREQ) - { - /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} -#endif /* FLASH_ACR_LATENCY */ - -/** - * @brief Function to check that PLL can be modified - * @param PLL_InputFrequency PLL input frequency (in Hz) - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @retval PLL output frequency (in Hz) - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) -{ - uint32_t pllfreq = 0U; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); - - /* Check different PLL parameters according to RM */ - /* The application software must set correctly the PLL multiplication factor to - be in the range 16-48MHz */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); - - return pllfreq; -} - -/** - * @brief Function to check that PLL can be modified - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PLL modification can be done - * - ERROR: PLL is busy - */ -static ErrorStatus UTILS_PLL_IsBusy(void) -{ - ErrorStatus status = SUCCESS; - - /* Check if PLL is busy*/ - if (LL_RCC_PLL_IsReady() != 0U) - { - /* PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief Function to enable PLL and switch system clock to PLL - * @param SYSCLK_Frequency SYSCLK frequency - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: No problem to switch system to PLL - * - ERROR: Problem to switch system to PLL - */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t sysclk_frequency_current = 0U; - - assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); - assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); - - /* Calculate current SYSCLK frequency */ - sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); - - /* Increasing the number of wait states because of higher CPU frequency */ - if (sysclk_frequency_current < SYSCLK_Frequency) - { - /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); - } - - /* Update system clock configuration */ - if (status == SUCCESS) - { - /* Enable PLL */ - LL_RCC_PLL_Enable(); - while (LL_RCC_PLL_IsReady() != 1U) - { - /* Wait for PLL ready */ - } - - /* Sysclk activation on the main PLL */ - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) - { - /* Wait for system clock switch to PLL */ - } - - /* Set APB1 & APB2 prescaler*/ - LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (sysclk_frequency_current > SYSCLK_Frequency) - { - /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); - } - - /* Update SystemCoreClock variable */ - if (status == SUCCESS) - { - LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/stm32f0xx_hal_conf.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/stm32f0xx_hal_conf.h deleted file mode 100644 index 36b2ef0..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/stm32f0xx_hal_conf.h +++ /dev/null @@ -1,323 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_CONF_H -#define __STM32F0xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_TSC_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_UART_MODULE_ENABLED */ -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -/*#define HAL_PCD_MODULE_ENABLED */ -/*#define HAL_EXTI_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - * Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator for ADC (HSI14) value. - */ -#if !defined (HSI14_VALUE) -#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI14_VALUE */ - -/** - * @brief Internal High Speed oscillator for USB (HSI48) value. - */ -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)40000) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSI) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ - /* Warning: Must be set to higher priority for HAL_Delay() */ - /* and HAL_GetTick() usage under interrupt context */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 -#define INSTRUCTION_CACHE_ENABLE 0 -#define DATA_CACHE_ENABLE 0 -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f0xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f0xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f0xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f0xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f0xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f0xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f0xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f0xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32f0xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f0xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f0xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f0xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f0xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f0xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f0xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f0xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f0xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f0xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f0xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f0xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f0xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f0xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f0xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32f0xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f0xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f0xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f0xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/system_stm32f0xx.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/system_stm32f0xx.c deleted file mode 100644 index 36b4652..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/lib/system_stm32f0xx.c +++ /dev/null @@ -1,333 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f0xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f0xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. This file configures the system clock as follows: - *============================================================================= - * Supported STM32F0xx device - *----------------------------------------------------------------------------- - * System Clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx_system - * @{ - */ - -/** @addtogroup STM32F0xx_System_Private_Includes - * @{ - */ - -#include "stm32f0xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Defines - * @{ - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI48_VALUE */ -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock there is no need to - call the 2 first functions listed above, since SystemCoreClock variable is - updated automatically. - */ -uint32_t SystemCoreClock = 8000000; - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001U; - -#if defined (STM32F051x8) || defined (STM32F058x8) - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ - RCC->CFGR &= (uint32_t)0xF8FFB80CU; -#else - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ - RCC->CFGR &= (uint32_t)0x08FFB80CU; -#endif /* STM32F051x8 or STM32F058x8 */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - RCC->CFGR &= (uint32_t)0xFFC0FFFFU; - - /* Reset PREDIV[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; - -#if defined (STM32F072xB) || defined (STM32F078xx) - /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; -#elif defined (STM32F071xB) - /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; -#elif defined (STM32F091xC) || defined (STM32F098xx) - /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; -#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) - /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; -#elif defined (STM32F051x8) || defined (STM32F058xx) - /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; -#elif defined (STM32F042x6) || defined (STM32F048xx) - /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; -#elif defined (STM32F070x6) || defined (STM32F070xB) - /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; - /* Set default USB clock to PLLCLK, since there is no HSI48 */ - RCC->CFGR3 |= (uint32_t)0x00000080U; -#else - #warning "No target selected" -#endif - - /* Reset HSI14 bit */ - RCC->CR2 &= (uint32_t)0xFFFFFFFEU; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000U; - -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - { - /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ - SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) - else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) - { - /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ - SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ - else - { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ - || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ - || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ - SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; -#else - /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || - STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || - STM32F091xC || STM32F098xx || STM32F030xC */ - } - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/main.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/main.c deleted file mode 100644 index 02ca6b9..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/main.c +++ /dev/null @@ -1,237 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/main.c -* \brief Demo program application source file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include /* C standard input/output */ -#include "microtbx.h" /* MicroTBX library */ -#include "timer.h" /* Timer driver */ -#include "led.h" /* LED driver */ -#include "analogfloat.h" /* Floating analog input driver */ -#include "stm32f0xx.h" /* STM32 CPU and HAL header */ - - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -static void Init(void); -static void SystemClock_Config(void); -static void CustomAssertionHandler(const char * const file, uint32_t line); -static uint32_t CustomSeedInitHandler(void); - - -/************************************************************************************//** -** \brief This is the entry point for the software application and is called -** by the reset interrupt vector after the C-startup routines executed. -** \return Program exit code. -** -****************************************************************************************/ -int main(void) -{ - uint32_t lastLedToggleTime = 0; - uint32_t numbers[8]; - size_t idx; - - /* Initialize the microcontroller. */ - Init(); - - /* Generate some random numbers and print them on the terminal (57600 bps). */ - for (idx = 0; idx < (sizeof(numbers)/sizeof(numbers[0])); idx++) - { - /* Get a new random number. */ - numbers[idx] = TbxRandomNumberGet(); - /* Print the value. */ - printf("Random number %u: %u.\n", idx+1, (unsigned int)numbers[idx]); - } - - /* Start the infinite program loop. */ - while (1) - { - /* Toggle the LED every 500 ms. */ - if ((TimerGet() - lastLedToggleTime) >= 500u) - { - LedToggle(); - lastLedToggleTime += 500; - } - } - /* Set program exit code. Note that the program should never get here. */ - return 0; -} /*** end of main ***/ - - -/************************************************************************************//** -** \brief Initializes the microcontroller. -** \return none. -** -****************************************************************************************/ -static void Init(void) -{ - /* Register the application specific assertion handler. */ - TbxAssertSetHandler(CustomAssertionHandler); - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - /* Configure the system clock. */ - SystemClock_Config(); - /* Initialize the timer driver. */ - TimerInit(); - /* Initialize the LED driver. */ - LedInit(); - /* Initialize the floating analog input driver. */ - AnalogFloatInit(); - /* Register the application specific seed initialization handler. It makes use of the - * analog float module and therefore needs to be called after the analog float - * module was initialized. - */ - TbxRandomSetSeedInitHandler(CustomSeedInitHandler); -} /*** end of Init ***/ - - -/************************************************************************************//** -** \brief System Clock Configuration. This code was created by CubeMX and configures -** the system clock. -** \return none. -** -****************************************************************************************/ -static void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - - /* Initializes the CPU, AHB and APB busses clocks. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - /* Clock configuration incorrect or hardware failure. Hang the system to prevent - * damage. - */ - TBX_ASSERT(TBX_FALSE); - } - - /* Initializes the CPU, AHB and APB busses clocks. */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | - RCC_CLOCKTYPE_PCLK1; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - /* Set the flash latency. */ - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) - { - /* Flash latency configuration incorrect or hardware failure. Hang the system to - * prevent damage. - */ - TBX_ASSERT(TBX_FALSE); - } -} /*** end of SystemClock_Config ***/ - - -/************************************************************************************//** -** \brief Triggers the run-time assertion. The default implementation is to enter an -** infinite loop, which halts the program and can be used for debugging -** purposes. Inspecting the values of the file and line parameters gives a -** clear indication where the run-time assertion occurred. Note that an -** alternative application specific assertion handler can be configured with -** function TbxAssertSetHandler(). -** \param file The filename of the source file where the assertion occurred in. -** \param line The line number inside the file where the assertion occurred. -** -****************************************************************************************/ -static void CustomAssertionHandler(const char * const file, uint32_t line) -{ - TBX_UNUSED_ARG(file); - TBX_UNUSED_ARG(line); - - /* Hang the program by entering an infinite loop. The values for file and line can - * then be inspected with the debugger to locate the source of the run-time assertion. - */ - for (;;) - { - ; - } -} /*** end of CustomAssertionHandler ***/ - - -/************************************************************************************//** -** \brief Handler function that gets called by the random number generator. This -** module requires a seed, which this function should obtain. The actual value -** is not really important as long as it is a value that is different every -** time the software program runs, so after each reset event. -** \details This example implementation set the seed based on the value of a floating -** analog input. Such a floating analog input will pick up noise, so the -** analog to digital conversion results always vary slightly. Other options -** would be to: -** * Increment a 32-bit value in EEPROM or a non-volatile register, if -** supported by the microcontroller, each time this function is called. -** Keep in mind though that these data storage options have a limited amount -** of write cycles. A better option might be to use external FRAM. -** * If the system was access to an external file system such as an SD-card, -** you could increment a 32-bit value in a file each time this function is -** called. -** \return The 32-bit value that the random number generator module uses as a seed to -** initialize itself. -** -****************************************************************************************/ -static uint32_t CustomSeedInitHandler(void) -{ - /* Create a 32-bit seed value by combining two reads of the floating analog pin. */ - return (AnalogFloatGet() << 16u) | AnalogFloatGet(); -} /*** end of CustomSeedInitHandler ***/ - - -/************************************************************************************//** -** \brief Initializes the Global MSP. This function is called from HAL_Init() -** function to perform system level initialization (GPIOs, clock, DMA, -** interrupt). -** \return none. -** -****************************************************************************************/ -void HAL_MspInit(void) -{ - /* SYSCFG clock enable. */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* SVC_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SVC_IRQn, 0, 0); - /* PendSV_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); -} /*** end of HAL_MspInit ***/ - - -/*********************************** end of main.c *************************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/makefile b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/makefile deleted file mode 100644 index 912a782..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/makefile +++ /dev/null @@ -1,174 +0,0 @@ -#**************************************************************************************** -#| Description: Makefile for GNU ARM Embedded toolchain. -#| File Name: makefile -#| -#|--------------------------------------------------------------------------------------- -#| C O P Y R I G H T -#|--------------------------------------------------------------------------------------- -#| Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -#| -#|--------------------------------------------------------------------------------------- -#| L I C E N S E -#|--------------------------------------------------------------------------------------- -#| Permission is hereby granted, free of charge, to any person obtaining a copy -#| of this software and associated documentation files (the "Software"), to deal -#| in the Software without restriction, including without limitation the rights -#| to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -#| copies of the Software, and to permit persons to whom the Software is -#| furnished to do so, subject to the following conditions: -#| -#| The above copyright notice and this permission notice shall be included in all -#| copies or substantial portions of the Software. -#| -#| THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -#| IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -#| FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -#| AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -#| LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -#| OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -#| SOFTWARE. -#| -#**************************************************************************************** -SHELL = sh - -#|--------------------------------------------------------------------------------------| -#| Configure project name | -#|--------------------------------------------------------------------------------------| -PROJ_NAME=microtbx_demo - - -#|--------------------------------------------------------------------------------------| -#| Configure tool path | -#|--------------------------------------------------------------------------------------| -TOOL_PATH=/opt/gcc-arm-none-eabi-8-2018-q4-major/bin/ - - -#|--------------------------------------------------------------------------------------| -#| Collect project files | -#|--------------------------------------------------------------------------------------| -# Recursive wildcard function implementation. Example usages: -# $(call rwildcard, , *.c *.h) -# --> Returns all *.c and *.h files in the current directory and below -# $(call rwildcard, /lib/, *.c) -# --> Returns all *.c files in the /lib directory and below -rwildcard = $(strip $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d))) - -# Collect all application files in the current directory and its subdirectories -PROJ_FILES = $(call rwildcard, , *.c *.h *.s) -# Collect MicroTBX sources -PROJ_FILES += $(wildcard ../../source/*.c) -PROJ_FILES += $(wildcard ../../source/*.h) -# Collect MicroTBX port and compiler specific sources -PROJ_FILES += $(wildcard ../../source/port/ARM_CORTEXM/*.c) -PROJ_FILES += $(wildcard ../../source/port/ARM_CORTEXM/*.h) -PROJ_FILES += $(wildcard ../../source/port/ARM_CORTEXM/GCC/*.c) -PROJ_FILES += $(wildcard ../../source/port/ARM_CORTEXM/GCC/*.h) -PROJ_FILES += $(wildcard ../../source/port/ARM_CORTEXM/GCC/*.s) - - -#|--------------------------------------------------------------------------------------| -#| Toolchain binaries | -#|--------------------------------------------------------------------------------------| -RM = rm -CC = $(TOOL_PATH)arm-none-eabi-gcc -LN = $(TOOL_PATH)arm-none-eabi-gcc -OC = $(TOOL_PATH)arm-none-eabi-objcopy -OD = $(TOOL_PATH)arm-none-eabi-objdump -AS = $(TOOL_PATH)arm-none-eabi-gcc -SZ = $(TOOL_PATH)arm-none-eabi-size - - -#|--------------------------------------------------------------------------------------| -#| Filter project files -#|--------------------------------------------------------------------------------------| -PROJ_ASRCS = $(filter %.s,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) -PROJ_CSRCS = $(filter %.c,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) -PROJ_CHDRS = $(filter %.h,$(foreach file,$(PROJ_FILES),$(notdir $(file)))) - - -#|--------------------------------------------------------------------------------------| -#| Set important path variables | -#|--------------------------------------------------------------------------------------| -VPATH = $(foreach path,$(sort $(foreach file,$(PROJ_FILES),$(dir $(file)))) $(subst \,/,$(OBJ_PATH)),$(path) :) -OBJ_PATH = obj -BIN_PATH = bin -INC_PATH = $(patsubst %/,%,$(patsubst %,-I%,$(sort $(foreach file,$(filter %.h,$(PROJ_FILES)),$(dir $(file)))))) -LIB_PATH = - - -#|--------------------------------------------------------------------------------------| -#| Options for toolchain binaries | -#|--------------------------------------------------------------------------------------| -STDFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft -STDFLAGS += -fdata-sections -ffunction-sections -Wall -g3 -OPTFLAGS = -O0 -CFLAGS = $(STDFLAGS) $(OPTFLAGS) -CFLAGS += -DSTM32F091xC -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -CFLAGS += $(INC_PATH) -AFLAGS = $(CFLAGS) -LFLAGS = $(STDFLAGS) $(OPTFLAGS) -LFLAGS += -Wl,-script="STM32F091RC_FLASH.ld" -Wl,-Map=$(BIN_PATH)/$(PROJ_NAME).map -LFLAGS += -specs=nano.specs -Wl,--gc-sections $(LIB_PATH) -OFLAGS = -O srec -ODFLAGS = -x -SZFLAGS = -B -d -RMFLAGS = -f - - -#|--------------------------------------------------------------------------------------| -#| Specify library files | -#|--------------------------------------------------------------------------------------| -LIBS = - - -#|--------------------------------------------------------------------------------------| -#| Define targets | -#|--------------------------------------------------------------------------------------| -AOBJS = $(patsubst %.s,%.o,$(PROJ_ASRCS)) -COBJS = $(patsubst %.c,%.o,$(PROJ_CSRCS)) - - -#|--------------------------------------------------------------------------------------| -#| Make ALL | -#|--------------------------------------------------------------------------------------| -.PHONY: all -all: $(BIN_PATH)/$(PROJ_NAME).srec - -$(BIN_PATH)/$(PROJ_NAME).srec : $(BIN_PATH)/$(PROJ_NAME).elf - @$(OC) $< $(OFLAGS) $@ - @$(OD) $(ODFLAGS) $< > $(BIN_PATH)/$(PROJ_NAME).map - @echo +++ Summary of memory consumption: - @$(SZ) $(SZFLAGS) $< - @echo +++ Build complete [$(notdir $@)] - -$(BIN_PATH)/$(PROJ_NAME).elf : $(AOBJS) $(COBJS) - @echo +++ Linking [$(notdir $@)] - @$(LN) $(LFLAGS) -o $@ $(patsubst %.o,$(OBJ_PATH)/%.o,$(^F)) $(LIBS) - - -#|--------------------------------------------------------------------------------------| -#| Compile and assemble | -#|--------------------------------------------------------------------------------------| -$(AOBJS): %.o: %.s $(PROJ_CHDRS) - @echo +++ Assembling [$(notdir $<)] - @$(AS) $(AFLAGS) -c $< -o $(OBJ_PATH)/$(@F) - -$(COBJS): %.o: %.c $(PROJ_CHDRS) - @echo +++ Compiling [$(notdir $<)] - @$(CC) $(CFLAGS) -c $< -o $(OBJ_PATH)/$(@F) - - -#|--------------------------------------------------------------------------------------| -#| Make CLEAN | -#|--------------------------------------------------------------------------------------| -.PHONY: clean -clean: - @echo +++ Cleaning build environment - @$(RM) $(RMFLAGS) $(foreach file,$(AOBJS),$(OBJ_PATH)/$(file)) - @$(RM) $(RMFLAGS) $(foreach file,$(COBJS),$(OBJ_PATH)/$(file)) - @$(RM) $(RMFLAGS) $(patsubst %.o,%.lst,$(foreach file,$(AOBJS),$(OBJ_PATH)/$(file))) - @$(RM) $(RMFLAGS) $(patsubst %.o,%.lst,$(foreach file,$(COBJS),$(OBJ_PATH)/$(file))) - @$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).elf $(BIN_PATH)/$(PROJ_NAME).map - @$(RM) $(RMFLAGS) $(BIN_PATH)/$(PROJ_NAME).srec - @echo +++ Clean complete - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/obj/.gitignore b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/obj/.gitignore deleted file mode 100644 index 5e7d273..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/obj/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -# Ignore everything in this directory -* -# Except this file -!.gitignore diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/startup_stm32f091xc.s b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/startup_stm32f091xc.s deleted file mode 100644 index e93ee99..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/startup_stm32f091xc.s +++ /dev/null @@ -1,303 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f091xc.s - * @author MCD Application Team - * @brief STM32F091xC devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_CRS_IRQHandler /* RCC and CRS */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word TSC_IRQHandler /* TSC */ - .word DMA1_Ch1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler /* DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 */ - .word DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler /* DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 */ - .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ - .word TIM7_IRQHandler /* TIM7 */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_8_IRQHandler /* USART3, USART4, USART5, USART6, USART7, USART8 */ - .word CEC_CAN_IRQHandler /* CEC and CAN */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_VDDIO2_IRQHandler - .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_CRS_IRQHandler - .thumb_set RCC_CRS_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak TSC_IRQHandler - .thumb_set TSC_IRQHandler,Default_Handler - - .weak DMA1_Ch1_IRQHandler - .thumb_set DMA1_Ch1_IRQHandler,Default_Handler - - .weak DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler - .thumb_set DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler,Default_Handler - - .weak DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler - .thumb_set DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler,Default_Handler - - .weak ADC1_COMP_IRQHandler - .thumb_set ADC1_COMP_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM15_IRQHandler - .thumb_set TIM15_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak I2C2_IRQHandler - .thumb_set I2C2_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_8_IRQHandler - .thumb_set USART3_8_IRQHandler,Default_Handler - - .weak CEC_CAN_IRQHandler - .thumb_set CEC_CAN_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/tbx_conf.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/tbx_conf.h deleted file mode 100644 index a87c6b1..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/tbx_conf.h +++ /dev/null @@ -1,58 +0,0 @@ -/************************************************************************************//** -* \file tbx_conf.h -* \brief MicroTBX configuration header file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ -#ifndef TBX_CONF_H -#define TBX_CONF_H - -#ifdef __cplusplus -extern "C" { -#endif -/**************************************************************************************** -* A S S E R T I O N S M O D U L E C O N F I G U R A T I O N -****************************************************************************************/ -/** \brief Enable/disable run-time assertions. */ -#define TBX_CONF_ASSERTIONS_ENABLE (1U) - - -/**************************************************************************************** -* H E A P M O D U L E C O N F I G U R A T I O N -****************************************************************************************/ -/** \brief Configure the size of the heap in bytes. */ -#define TBX_CONF_HEAP_SIZE (2048U) - - -#ifdef __cplusplus -} -#endif - -#endif /* TBX_CONF_H */ -/*********************************** end of tbx_conf.h *********************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.c b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.c deleted file mode 100644 index df724c2..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.c +++ /dev/null @@ -1,84 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/timer.c -* \brief Timer driver source file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ - -/**************************************************************************************** -* Include files -****************************************************************************************/ -#include "microtbx.h" /* MicroTBX library */ -#include "timer.h" /* Timer driver */ -#include "stm32f0xx.h" /* STM32 CPU and HAL header */ - - -/************************************************************************************//** -** \brief Initializes the timer. -** \return none. -** -****************************************************************************************/ -void TimerInit(void) -{ - /* Configure the Systick interrupt time for 1 millisecond. */ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - /* Configure the Systick. */ - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - /* SysTick_IRQn interrupt configuration. */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); -} /*** end of TimerInit ***/ - - -/************************************************************************************//** -** \brief Obtains the counter value of the millisecond timer. -** \return Current value of the millisecond timer. -** -****************************************************************************************/ -uint32_t TimerGet(void) -{ - /* Read and return the tick counter value. */ - return HAL_GetTick(); -} /*** end of TimerGet ***/ - - -/************************************************************************************//** -** \brief Interrupt service routine of the timer. -** \return none. -** -****************************************************************************************/ -void SysTick_Handler(void) -{ - /* Increment the tick counter. */ - HAL_IncTick(); - /* Invoke the system tick handler. */ - HAL_SYSTICK_IRQHandler(); -} /*** end of SysTick_Handler ***/ - - -/*********************************** end of timer.c ************************************/ diff --git a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.h b/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.h deleted file mode 100644 index 53e9831..0000000 --- a/demos/ARM_CORTEXM_ST_Nucleo_F091RC_GCC/timer.h +++ /dev/null @@ -1,43 +0,0 @@ -/************************************************************************************//** -* \file demos/ARMCM0_STM32F0_Nucleo_F091RC_GCC/timer.h -* \brief Timer driver header file. -* \internal -*---------------------------------------------------------------------------------------- -* C O P Y R I G H T -*---------------------------------------------------------------------------------------- -* Copyright (c) 2019 by Feaser www.feaser.com All rights reserved -* -*---------------------------------------------------------------------------------------- -* L I C E N S E -*---------------------------------------------------------------------------------------- -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in all -* copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* \endinternal -****************************************************************************************/ -#ifndef TIMER_H -#define TIMER_H - -/**************************************************************************************** -* Function prototypes -****************************************************************************************/ -void TimerInit(void); -uint32_t TimerGet(void); - -#endif /* TIMER_H */ -/*********************************** end of timer.h ************************************/ diff --git a/source/microtbx.h b/source/microtbx.h index 67f6be9..3c942de 100644 --- a/source/microtbx.h +++ b/source/microtbx.h @@ -73,7 +73,7 @@ extern "C" { #define TBX_VERSION_MINOR (9U) /** \brief Patch number of MicroTBX. */ -#define TBX_VERSION_PATCH (3U) +#define TBX_VERSION_PATCH (4U) /****************************************************************************************