From bbde11e40fd7f4b2ea76101fbb5d8f3c1f6720ba Mon Sep 17 00:00:00 2001
From: Sergio Gasquez <sergio.gasquez@gmail.com>
Date: Wed, 8 Jan 2025 12:07:56 +0100
Subject: [PATCH] feat: Make read_bytes return how many bytes it read from the
 fifo and fix docs/tests

---
 esp-hal/src/uart.rs               | 14 +++++++-------
 hil-test/tests/uart_regression.rs | 11 ++---------
 hil-test/tests/uart_tx_rx.rs      | 10 +++-------
 3 files changed, 12 insertions(+), 23 deletions(-)

diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs
index 33a01b154d..950cd93262 100644
--- a/esp-hal/src/uart.rs
+++ b/esp-hal/src/uart.rs
@@ -79,8 +79,8 @@
 //! let (mut rx, mut tx) = uart1.split();
 //!
 //! // Each component can be used individually to interact with the UART:
-//! tx.write_bytes(&[42u8]).expect("write error!");
-//! let byte = rx.read_byte().expect("read error!");
+//! tx.write_bytes(&[42u8]);
+//! let byte = rx.read_byte();
 //! # }
 //! ```
 //! 
@@ -198,9 +198,8 @@
 //!         let serial = serial.as_mut().unwrap();
 //!
 //!         let mut cnt = 0;
-//!         while let Some(_c) = serial.read_byte() {
-//!             cnt += 1;
-//!         }
+//!         let mut buff = [0u8; 64];
+//!         let cnt = serial.read_bytes(&mut buff);
 //!         writeln!(serial, "Read {} bytes", cnt).ok();
 //!
 //!         let pending_interrupts = serial.interrupts();
@@ -865,10 +864,11 @@ where
         }
     }
 
-    /// Read as many bytes from the UART as the provided buffer can hold.
+    /// Read all available bytes from the RX FIFO into the provided buffer and
+    /// returns the number of read bytes.
     pub fn read_bytes(&mut self, buf: &mut [u8]) -> usize {
         let mut count = 0;
-        while count < buf.len() {
+        while count < buf.len() && self.rx_fifo_count() > 0 {
             buf[count] = self.read_byte();
             count += 1;
         }
diff --git a/hil-test/tests/uart_regression.rs b/hil-test/tests/uart_regression.rs
index 51c5c4a361..305f352927 100644
--- a/hil-test/tests/uart_regression.rs
+++ b/hil-test/tests/uart_regression.rs
@@ -22,21 +22,14 @@ mod tests {
 
         let mut rx = UartRx::new(peripherals.UART1, uart::Config::default(), rx).unwrap();
 
-        // start reception
-        _ = rx.read_byte(); // this will just return WouldBlock
-
         unsafe { tx.set_output_high(false, esp_hal::Internal::conjure()) };
 
         // set up TX and send a byte
         let mut tx = UartTx::new(peripherals.UART0, uart::Config::default(), tx).unwrap();
 
-        tx.flush().unwrap();
+        tx.flush();
         tx.write_bytes(&[0x42]).unwrap();
-        let read = loop {
-            if let Some(byte) = rx.read_byte() {
-                break byte;
-            }
-        };
+        let read = rx.read_byte();
 
         assert_eq!(read, 0x42);
     }
diff --git a/hil-test/tests/uart_tx_rx.rs b/hil-test/tests/uart_tx_rx.rs
index b063e8713b..7a1cb33576 100644
--- a/hil-test/tests/uart_tx_rx.rs
+++ b/hil-test/tests/uart_tx_rx.rs
@@ -37,13 +37,9 @@ mod tests {
     fn test_send_receive(mut ctx: Context) {
         let byte = [0x42];
 
-        ctx.tx.flush().unwrap();
+        ctx.tx.flush();
         ctx.tx.write_bytes(&byte).unwrap();
-        let read = loop {
-            if let Some(byte) = ctx.rx.read_byte() {
-                break byte;
-            }
-        };
+        let read = ctx.rx.read_byte();
 
         assert_eq!(read, 0x42);
     }
@@ -53,7 +49,7 @@ mod tests {
         let bytes = [0x42, 0x43, 0x44];
         let mut buf = [0u8; 3];
 
-        ctx.tx.flush().unwrap();
+        ctx.tx.flush();
         ctx.tx.write_bytes(&bytes).unwrap();
 
         let mut bytes_read = 0;