From 615fcf927fde203084af053cc2480cafa68d0f4f Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Fri, 19 Apr 2024 22:59:58 +0300 Subject: [PATCH] target/riscv/riscv-011.c: fix access to non-existent register `reg` is a number in register cache, as evident by the following call to `reg_cache_set()`. `CSR_DCSR` is `GDB_REGNO_DCSR - 65`. This results in setting cache value for another register, which does not exist, and causes a segfault if all non-existent registers are not allocated a value (`reg->value == NULL`). Change-Id: Iab68a4bb55ce6d4730804e9709e40ab2af8a07c6 Signed-off-by: Evgeniy Naydanov --- src/target/riscv/riscv-011.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 1332c3d1e..80e7b65bd 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -1771,10 +1771,10 @@ static riscv_error_t handle_halt_routine(struct target *target) reg = S0; break; case 31: - reg = CSR_DPC; + reg = GDB_REGNO_DPC; break; case 32: - reg = CSR_DCSR; + reg = GDB_REGNO_DCSR; break; default: assert(0);