diff --git a/src/adc/regs.rs b/src/adc/regs.rs
index 70e1f07c..998c7631 100644
--- a/src/adc/regs.rs
+++ b/src/adc/regs.rs
@@ -293,7 +293,7 @@ impl Default for Fifo {
         Fifo(0)
     }
 }
-#[doc = "Interrupt Force"]
+#[doc = "Interrupt Enable"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/busctrl/regs.rs b/src/busctrl/regs.rs
index e7025543..08006b14 100644
--- a/src/busctrl/regs.rs
+++ b/src/busctrl/regs.rs
@@ -77,18 +77,18 @@ impl Default for BusPriorityAck {
         BusPriorityAck(0)
     }
 }
-#[doc = "Bus fabric performance counter 2"]
+#[doc = "Bus fabric performance counter 0"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Perfctr(pub u32);
 impl Perfctr {
-    #[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"]
+    #[doc = "Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"]
     #[inline(always)]
     pub const fn perfctr(&self) -> u32 {
         let val = (self.0 >> 0usize) & 0x00ff_ffff;
         val as u32
     }
-    #[doc = "Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"]
+    #[doc = "Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"]
     #[inline(always)]
     pub fn set_perfctr(&mut self, val: u32) {
         self.0 = (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize);
@@ -100,21 +100,21 @@ impl Default for Perfctr {
         Perfctr(0)
     }
 }
-#[doc = "Bus fabric performance event select for PERFCTR0"]
+#[doc = "Bus fabric performance event select for PERFCTR1"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Perfsel(pub u32);
 impl Perfsel {
-    #[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
+    #[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
     #[inline(always)]
     pub const fn perfsel(&self) -> super::vals::Perfsel {
         let val = (self.0 >> 0usize) & 0x1f;
-        super::vals::Perfsel(val as u8)
+        super::vals::Perfsel::from_bits(val as u8)
     }
-    #[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
+    #[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
     #[inline(always)]
     pub fn set_perfsel(&mut self, val: super::vals::Perfsel) {
-        self.0 = (self.0 & !(0x1f << 0usize)) | (((val.0 as u32) & 0x1f) << 0usize);
+        self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize);
     }
 }
 impl Default for Perfsel {
diff --git a/src/busctrl/vals.rs b/src/busctrl/vals.rs
index 97956fd1..f88e41e4 100644
--- a/src/busctrl/vals.rs
+++ b/src/busctrl/vals.rs
@@ -1,25 +1,58 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Perfsel(pub u8);
+pub enum Perfsel {
+    APB_CONTESTED = 0,
+    APB = 0x01,
+    FASTPERI_CONTESTED = 0x02,
+    FASTPERI = 0x03,
+    SRAM5_CONTESTED = 0x04,
+    SRAM5 = 0x05,
+    SRAM4_CONTESTED = 0x06,
+    SRAM4 = 0x07,
+    SRAM3_CONTESTED = 0x08,
+    SRAM3 = 0x09,
+    SRAM2_CONTESTED = 0x0a,
+    SRAM2 = 0x0b,
+    SRAM1_CONTESTED = 0x0c,
+    SRAM1 = 0x0d,
+    SRAM0_CONTESTED = 0x0e,
+    SRAM0 = 0x0f,
+    XIP_MAIN_CONTESTED = 0x10,
+    XIP_MAIN = 0x11,
+    ROM_CONTESTED = 0x12,
+    ROM = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    _RESERVED_1f = 0x1f,
+}
 impl Perfsel {
-    pub const APB_CONTESTED: Self = Self(0);
-    pub const APB: Self = Self(0x01);
-    pub const FASTPERI_CONTESTED: Self = Self(0x02);
-    pub const FASTPERI: Self = Self(0x03);
-    pub const SRAM5_CONTESTED: Self = Self(0x04);
-    pub const SRAM5: Self = Self(0x05);
-    pub const SRAM4_CONTESTED: Self = Self(0x06);
-    pub const SRAM4: Self = Self(0x07);
-    pub const SRAM3_CONTESTED: Self = Self(0x08);
-    pub const SRAM3: Self = Self(0x09);
-    pub const SRAM2_CONTESTED: Self = Self(0x0a);
-    pub const SRAM2: Self = Self(0x0b);
-    pub const SRAM1_CONTESTED: Self = Self(0x0c);
-    pub const SRAM1: Self = Self(0x0d);
-    pub const SRAM0_CONTESTED: Self = Self(0x0e);
-    pub const SRAM0: Self = Self(0x0f);
-    pub const XIP_MAIN_CONTESTED: Self = Self(0x10);
-    pub const XIP_MAIN: Self = Self(0x11);
-    pub const ROM_CONTESTED: Self = Self(0x12);
-    pub const ROM: Self = Self(0x13);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Perfsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Perfsel {
+    #[inline(always)]
+    fn from(val: u8) -> Perfsel {
+        Perfsel::from_bits(val)
+    }
+}
+impl From<Perfsel> for u8 {
+    #[inline(always)]
+    fn from(val: Perfsel) -> u8 {
+        Perfsel::to_bits(val)
+    }
 }
diff --git a/src/clocks/regs.rs b/src/clocks/regs.rs
index d3d1508f..b2cc8130 100644
--- a/src/clocks/regs.rs
+++ b/src/clocks/regs.rs
@@ -7,12 +7,12 @@ impl ClkAdcCtrl {
     #[inline(always)]
     pub const fn auxsrc(&self) -> super::vals::ClkAdcCtrlAuxsrc {
         let val = (self.0 >> 5usize) & 0x07;
-        super::vals::ClkAdcCtrlAuxsrc(val as u8)
+        super::vals::ClkAdcCtrlAuxsrc::from_bits(val as u8)
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub fn set_auxsrc(&mut self, val: super::vals::ClkAdcCtrlAuxsrc) {
-        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
     }
     #[doc = "Asynchronously kills the clock generator"]
     #[inline(always)]
@@ -97,12 +97,12 @@ impl ClkGpoutCtrl {
     #[inline(always)]
     pub const fn auxsrc(&self) -> super::vals::ClkGpoutCtrlAuxsrc {
         let val = (self.0 >> 5usize) & 0x0f;
-        super::vals::ClkGpoutCtrlAuxsrc(val as u8)
+        super::vals::ClkGpoutCtrlAuxsrc::from_bits(val as u8)
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub fn set_auxsrc(&mut self, val: super::vals::ClkGpoutCtrlAuxsrc) {
-        self.0 = (self.0 & !(0x0f << 5usize)) | (((val.0 as u32) & 0x0f) << 5usize);
+        self.0 = (self.0 & !(0x0f << 5usize)) | (((val.to_bits() as u32) & 0x0f) << 5usize);
     }
     #[doc = "Asynchronously kills the clock generator"]
     #[inline(always)]
@@ -209,12 +209,12 @@ impl ClkPeriCtrl {
     #[inline(always)]
     pub const fn auxsrc(&self) -> super::vals::ClkPeriCtrlAuxsrc {
         let val = (self.0 >> 5usize) & 0x07;
-        super::vals::ClkPeriCtrlAuxsrc(val as u8)
+        super::vals::ClkPeriCtrlAuxsrc::from_bits(val as u8)
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub fn set_auxsrc(&mut self, val: super::vals::ClkPeriCtrlAuxsrc) {
-        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
     }
     #[doc = "Asynchronously kills the clock generator"]
     #[inline(always)]
@@ -254,23 +254,23 @@ impl ClkRefCtrl {
     #[inline(always)]
     pub const fn src(&self) -> super::vals::ClkRefCtrlSrc {
         let val = (self.0 >> 0usize) & 0x03;
-        super::vals::ClkRefCtrlSrc(val as u8)
+        super::vals::ClkRefCtrlSrc::from_bits(val as u8)
     }
     #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
     #[inline(always)]
     pub fn set_src(&mut self, val: super::vals::ClkRefCtrlSrc) {
-        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub const fn auxsrc(&self) -> super::vals::ClkRefCtrlAuxsrc {
         let val = (self.0 >> 5usize) & 0x03;
-        super::vals::ClkRefCtrlAuxsrc(val as u8)
+        super::vals::ClkRefCtrlAuxsrc::from_bits(val as u8)
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub fn set_auxsrc(&mut self, val: super::vals::ClkRefCtrlAuxsrc) {
-        self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize);
+        self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u32) & 0x03) << 5usize);
     }
 }
 impl Default for ClkRefCtrl {
@@ -311,12 +311,12 @@ impl ClkRtcCtrl {
     #[inline(always)]
     pub const fn auxsrc(&self) -> super::vals::ClkRtcCtrlAuxsrc {
         let val = (self.0 >> 5usize) & 0x07;
-        super::vals::ClkRtcCtrlAuxsrc(val as u8)
+        super::vals::ClkRtcCtrlAuxsrc::from_bits(val as u8)
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub fn set_auxsrc(&mut self, val: super::vals::ClkRtcCtrlAuxsrc) {
-        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
     }
     #[doc = "Asynchronously kills the clock generator"]
     #[inline(always)]
@@ -412,23 +412,23 @@ impl ClkSysCtrl {
     #[inline(always)]
     pub const fn src(&self) -> super::vals::ClkSysCtrlSrc {
         let val = (self.0 >> 0usize) & 0x01;
-        super::vals::ClkSysCtrlSrc(val as u8)
+        super::vals::ClkSysCtrlSrc::from_bits(val as u8)
     }
     #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly"]
     #[inline(always)]
     pub fn set_src(&mut self, val: super::vals::ClkSysCtrlSrc) {
-        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub const fn auxsrc(&self) -> super::vals::ClkSysCtrlAuxsrc {
         let val = (self.0 >> 5usize) & 0x07;
-        super::vals::ClkSysCtrlAuxsrc(val as u8)
+        super::vals::ClkSysCtrlAuxsrc::from_bits(val as u8)
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub fn set_auxsrc(&mut self, val: super::vals::ClkSysCtrlAuxsrc) {
-        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
     }
 }
 impl Default for ClkSysCtrl {
@@ -557,12 +557,12 @@ impl ClkUsbCtrl {
     #[inline(always)]
     pub const fn auxsrc(&self) -> super::vals::ClkUsbCtrlAuxsrc {
         let val = (self.0 >> 5usize) & 0x07;
-        super::vals::ClkUsbCtrlAuxsrc(val as u8)
+        super::vals::ClkUsbCtrlAuxsrc::from_bits(val as u8)
     }
     #[doc = "Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
     pub fn set_auxsrc(&mut self, val: super::vals::ClkUsbCtrlAuxsrc) {
-        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.0 as u32) & 0x07) << 5usize);
+        self.0 = (self.0 & !(0x07 << 5usize)) | (((val.to_bits() as u32) & 0x07) << 5usize);
     }
     #[doc = "Asynchronously kills the clock generator"]
     #[inline(always)]
@@ -1228,11 +1228,11 @@ impl Fc0src {
     #[inline(always)]
     pub const fn fc0_src(&self) -> super::vals::Fc0src {
         let val = (self.0 >> 0usize) & 0xff;
-        super::vals::Fc0src(val as u8)
+        super::vals::Fc0src::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_fc0_src(&mut self, val: super::vals::Fc0src) {
-        self.0 = (self.0 & !(0xff << 0usize)) | (((val.0 as u32) & 0xff) << 0usize);
+        self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize);
     }
 }
 impl Default for Fc0src {
@@ -1341,7 +1341,7 @@ impl Default for Fc0status {
         Fc0status(0)
     }
 }
-#[doc = "Interrupt status after masking & forcing"]
+#[doc = "Interrupt Force"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/clocks/vals.rs b/src/clocks/vals.rs
index e2d337a6..d47fbe3e 100644
--- a/src/clocks/vals.rs
+++ b/src/clocks/vals.rs
@@ -1,114 +1,582 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkAdcCtrlAuxsrc(pub u8);
+pub enum ClkAdcCtrlAuxsrc {
+    CLKSRC_PLL_USB = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    ROSC_CLKSRC_PH = 0x02,
+    XOSC_CLKSRC = 0x03,
+    CLKSRC_GPIN0 = 0x04,
+    CLKSRC_GPIN1 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
 impl ClkAdcCtrlAuxsrc {
-    pub const CLKSRC_PLL_USB: Self = Self(0);
-    pub const CLKSRC_PLL_SYS: Self = Self(0x01);
-    pub const ROSC_CLKSRC_PH: Self = Self(0x02);
-    pub const XOSC_CLKSRC: Self = Self(0x03);
-    pub const CLKSRC_GPIN0: Self = Self(0x04);
-    pub const CLKSRC_GPIN1: Self = Self(0x05);
-}
-#[repr(transparent)]
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkAdcCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkAdcCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkAdcCtrlAuxsrc {
+        ClkAdcCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkAdcCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkAdcCtrlAuxsrc) -> u8 {
+        ClkAdcCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkGpoutCtrlAuxsrc(pub u8);
+pub enum ClkGpoutCtrlAuxsrc {
+    CLKSRC_PLL_SYS = 0,
+    CLKSRC_GPIN0 = 0x01,
+    CLKSRC_GPIN1 = 0x02,
+    CLKSRC_PLL_USB = 0x03,
+    ROSC_CLKSRC = 0x04,
+    XOSC_CLKSRC = 0x05,
+    CLK_SYS = 0x06,
+    CLK_USB = 0x07,
+    CLK_ADC = 0x08,
+    CLK_RTC = 0x09,
+    CLK_REF = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+}
 impl ClkGpoutCtrlAuxsrc {
-    pub const CLKSRC_PLL_SYS: Self = Self(0);
-    pub const CLKSRC_GPIN0: Self = Self(0x01);
-    pub const CLKSRC_GPIN1: Self = Self(0x02);
-    pub const CLKSRC_PLL_USB: Self = Self(0x03);
-    pub const ROSC_CLKSRC: Self = Self(0x04);
-    pub const XOSC_CLKSRC: Self = Self(0x05);
-    pub const CLK_SYS: Self = Self(0x06);
-    pub const CLK_USB: Self = Self(0x07);
-    pub const CLK_ADC: Self = Self(0x08);
-    pub const CLK_RTC: Self = Self(0x09);
-    pub const CLK_REF: Self = Self(0x0a);
-}
-#[repr(transparent)]
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkGpoutCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkGpoutCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkGpoutCtrlAuxsrc {
+        ClkGpoutCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkGpoutCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkGpoutCtrlAuxsrc) -> u8 {
+        ClkGpoutCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkPeriCtrlAuxsrc(pub u8);
+pub enum ClkPeriCtrlAuxsrc {
+    CLK_SYS = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    CLKSRC_PLL_USB = 0x02,
+    ROSC_CLKSRC_PH = 0x03,
+    XOSC_CLKSRC = 0x04,
+    CLKSRC_GPIN0 = 0x05,
+    CLKSRC_GPIN1 = 0x06,
+    _RESERVED_7 = 0x07,
+}
 impl ClkPeriCtrlAuxsrc {
-    pub const CLK_SYS: Self = Self(0);
-    pub const CLKSRC_PLL_SYS: Self = Self(0x01);
-    pub const CLKSRC_PLL_USB: Self = Self(0x02);
-    pub const ROSC_CLKSRC_PH: Self = Self(0x03);
-    pub const XOSC_CLKSRC: Self = Self(0x04);
-    pub const CLKSRC_GPIN0: Self = Self(0x05);
-    pub const CLKSRC_GPIN1: Self = Self(0x06);
-}
-#[repr(transparent)]
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkPeriCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkPeriCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkPeriCtrlAuxsrc {
+        ClkPeriCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkPeriCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkPeriCtrlAuxsrc) -> u8 {
+        ClkPeriCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkRefCtrlAuxsrc(pub u8);
+pub enum ClkRefCtrlAuxsrc {
+    CLKSRC_PLL_USB = 0,
+    CLKSRC_GPIN0 = 0x01,
+    CLKSRC_GPIN1 = 0x02,
+    _RESERVED_3 = 0x03,
+}
 impl ClkRefCtrlAuxsrc {
-    pub const CLKSRC_PLL_USB: Self = Self(0);
-    pub const CLKSRC_GPIN0: Self = Self(0x01);
-    pub const CLKSRC_GPIN1: Self = Self(0x02);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkRefCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkRefCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkRefCtrlAuxsrc {
+        ClkRefCtrlAuxsrc::from_bits(val)
+    }
 }
-#[repr(transparent)]
+impl From<ClkRefCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkRefCtrlAuxsrc) -> u8 {
+        ClkRefCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkRefCtrlSrc(pub u8);
+pub enum ClkRefCtrlSrc {
+    ROSC_CLKSRC_PH = 0,
+    CLKSRC_CLK_REF_AUX = 0x01,
+    XOSC_CLKSRC = 0x02,
+    _RESERVED_3 = 0x03,
+}
 impl ClkRefCtrlSrc {
-    pub const ROSC_CLKSRC_PH: Self = Self(0);
-    pub const CLKSRC_CLK_REF_AUX: Self = Self(0x01);
-    pub const XOSC_CLKSRC: Self = Self(0x02);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkRefCtrlSrc {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkRefCtrlSrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkRefCtrlSrc {
+        ClkRefCtrlSrc::from_bits(val)
+    }
+}
+impl From<ClkRefCtrlSrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkRefCtrlSrc) -> u8 {
+        ClkRefCtrlSrc::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkRtcCtrlAuxsrc(pub u8);
+pub enum ClkRtcCtrlAuxsrc {
+    CLKSRC_PLL_USB = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    ROSC_CLKSRC_PH = 0x02,
+    XOSC_CLKSRC = 0x03,
+    CLKSRC_GPIN0 = 0x04,
+    CLKSRC_GPIN1 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
 impl ClkRtcCtrlAuxsrc {
-    pub const CLKSRC_PLL_USB: Self = Self(0);
-    pub const CLKSRC_PLL_SYS: Self = Self(0x01);
-    pub const ROSC_CLKSRC_PH: Self = Self(0x02);
-    pub const XOSC_CLKSRC: Self = Self(0x03);
-    pub const CLKSRC_GPIN0: Self = Self(0x04);
-    pub const CLKSRC_GPIN1: Self = Self(0x05);
-}
-#[repr(transparent)]
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkRtcCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkRtcCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkRtcCtrlAuxsrc {
+        ClkRtcCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkRtcCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkRtcCtrlAuxsrc) -> u8 {
+        ClkRtcCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkSysCtrlAuxsrc(pub u8);
+pub enum ClkSysCtrlAuxsrc {
+    CLKSRC_PLL_SYS = 0,
+    CLKSRC_PLL_USB = 0x01,
+    ROSC_CLKSRC = 0x02,
+    XOSC_CLKSRC = 0x03,
+    CLKSRC_GPIN0 = 0x04,
+    CLKSRC_GPIN1 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
 impl ClkSysCtrlAuxsrc {
-    pub const CLKSRC_PLL_SYS: Self = Self(0);
-    pub const CLKSRC_PLL_USB: Self = Self(0x01);
-    pub const ROSC_CLKSRC: Self = Self(0x02);
-    pub const XOSC_CLKSRC: Self = Self(0x03);
-    pub const CLKSRC_GPIN0: Self = Self(0x04);
-    pub const CLKSRC_GPIN1: Self = Self(0x05);
-}
-#[repr(transparent)]
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkSysCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkSysCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkSysCtrlAuxsrc {
+        ClkSysCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkSysCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkSysCtrlAuxsrc) -> u8 {
+        ClkSysCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkSysCtrlSrc(pub u8);
+pub enum ClkSysCtrlSrc {
+    CLK_REF = 0,
+    CLKSRC_CLK_SYS_AUX = 0x01,
+}
 impl ClkSysCtrlSrc {
-    pub const CLK_REF: Self = Self(0);
-    pub const CLKSRC_CLK_SYS_AUX: Self = Self(0x01);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkSysCtrlSrc {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
 }
-#[repr(transparent)]
+impl From<u8> for ClkSysCtrlSrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkSysCtrlSrc {
+        ClkSysCtrlSrc::from_bits(val)
+    }
+}
+impl From<ClkSysCtrlSrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkSysCtrlSrc) -> u8 {
+        ClkSysCtrlSrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct ClkUsbCtrlAuxsrc(pub u8);
+pub enum ClkUsbCtrlAuxsrc {
+    CLKSRC_PLL_USB = 0,
+    CLKSRC_PLL_SYS = 0x01,
+    ROSC_CLKSRC_PH = 0x02,
+    XOSC_CLKSRC = 0x03,
+    CLKSRC_GPIN0 = 0x04,
+    CLKSRC_GPIN1 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+}
 impl ClkUsbCtrlAuxsrc {
-    pub const CLKSRC_PLL_USB: Self = Self(0);
-    pub const CLKSRC_PLL_SYS: Self = Self(0x01);
-    pub const ROSC_CLKSRC_PH: Self = Self(0x02);
-    pub const XOSC_CLKSRC: Self = Self(0x03);
-    pub const CLKSRC_GPIN0: Self = Self(0x04);
-    pub const CLKSRC_GPIN1: Self = Self(0x05);
-}
-#[repr(transparent)]
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> ClkUsbCtrlAuxsrc {
+        unsafe { core::mem::transmute(val & 0x07) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for ClkUsbCtrlAuxsrc {
+    #[inline(always)]
+    fn from(val: u8) -> ClkUsbCtrlAuxsrc {
+        ClkUsbCtrlAuxsrc::from_bits(val)
+    }
+}
+impl From<ClkUsbCtrlAuxsrc> for u8 {
+    #[inline(always)]
+    fn from(val: ClkUsbCtrlAuxsrc) -> u8 {
+        ClkUsbCtrlAuxsrc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Fc0src(pub u8);
+pub enum Fc0src {
+    NULL = 0,
+    PLL_SYS_CLKSRC_PRIMARY = 0x01,
+    PLL_USB_CLKSRC_PRIMARY = 0x02,
+    ROSC_CLKSRC = 0x03,
+    ROSC_CLKSRC_PH = 0x04,
+    XOSC_CLKSRC = 0x05,
+    CLKSRC_GPIN0 = 0x06,
+    CLKSRC_GPIN1 = 0x07,
+    CLK_REF = 0x08,
+    CLK_SYS = 0x09,
+    CLK_PERI = 0x0a,
+    CLK_USB = 0x0b,
+    CLK_ADC = 0x0c,
+    CLK_RTC = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    _RESERVED_1f = 0x1f,
+    _RESERVED_20 = 0x20,
+    _RESERVED_21 = 0x21,
+    _RESERVED_22 = 0x22,
+    _RESERVED_23 = 0x23,
+    _RESERVED_24 = 0x24,
+    _RESERVED_25 = 0x25,
+    _RESERVED_26 = 0x26,
+    _RESERVED_27 = 0x27,
+    _RESERVED_28 = 0x28,
+    _RESERVED_29 = 0x29,
+    _RESERVED_2a = 0x2a,
+    _RESERVED_2b = 0x2b,
+    _RESERVED_2c = 0x2c,
+    _RESERVED_2d = 0x2d,
+    _RESERVED_2e = 0x2e,
+    _RESERVED_2f = 0x2f,
+    _RESERVED_30 = 0x30,
+    _RESERVED_31 = 0x31,
+    _RESERVED_32 = 0x32,
+    _RESERVED_33 = 0x33,
+    _RESERVED_34 = 0x34,
+    _RESERVED_35 = 0x35,
+    _RESERVED_36 = 0x36,
+    _RESERVED_37 = 0x37,
+    _RESERVED_38 = 0x38,
+    _RESERVED_39 = 0x39,
+    _RESERVED_3a = 0x3a,
+    _RESERVED_3b = 0x3b,
+    _RESERVED_3c = 0x3c,
+    _RESERVED_3d = 0x3d,
+    _RESERVED_3e = 0x3e,
+    _RESERVED_3f = 0x3f,
+    _RESERVED_40 = 0x40,
+    _RESERVED_41 = 0x41,
+    _RESERVED_42 = 0x42,
+    _RESERVED_43 = 0x43,
+    _RESERVED_44 = 0x44,
+    _RESERVED_45 = 0x45,
+    _RESERVED_46 = 0x46,
+    _RESERVED_47 = 0x47,
+    _RESERVED_48 = 0x48,
+    _RESERVED_49 = 0x49,
+    _RESERVED_4a = 0x4a,
+    _RESERVED_4b = 0x4b,
+    _RESERVED_4c = 0x4c,
+    _RESERVED_4d = 0x4d,
+    _RESERVED_4e = 0x4e,
+    _RESERVED_4f = 0x4f,
+    _RESERVED_50 = 0x50,
+    _RESERVED_51 = 0x51,
+    _RESERVED_52 = 0x52,
+    _RESERVED_53 = 0x53,
+    _RESERVED_54 = 0x54,
+    _RESERVED_55 = 0x55,
+    _RESERVED_56 = 0x56,
+    _RESERVED_57 = 0x57,
+    _RESERVED_58 = 0x58,
+    _RESERVED_59 = 0x59,
+    _RESERVED_5a = 0x5a,
+    _RESERVED_5b = 0x5b,
+    _RESERVED_5c = 0x5c,
+    _RESERVED_5d = 0x5d,
+    _RESERVED_5e = 0x5e,
+    _RESERVED_5f = 0x5f,
+    _RESERVED_60 = 0x60,
+    _RESERVED_61 = 0x61,
+    _RESERVED_62 = 0x62,
+    _RESERVED_63 = 0x63,
+    _RESERVED_64 = 0x64,
+    _RESERVED_65 = 0x65,
+    _RESERVED_66 = 0x66,
+    _RESERVED_67 = 0x67,
+    _RESERVED_68 = 0x68,
+    _RESERVED_69 = 0x69,
+    _RESERVED_6a = 0x6a,
+    _RESERVED_6b = 0x6b,
+    _RESERVED_6c = 0x6c,
+    _RESERVED_6d = 0x6d,
+    _RESERVED_6e = 0x6e,
+    _RESERVED_6f = 0x6f,
+    _RESERVED_70 = 0x70,
+    _RESERVED_71 = 0x71,
+    _RESERVED_72 = 0x72,
+    _RESERVED_73 = 0x73,
+    _RESERVED_74 = 0x74,
+    _RESERVED_75 = 0x75,
+    _RESERVED_76 = 0x76,
+    _RESERVED_77 = 0x77,
+    _RESERVED_78 = 0x78,
+    _RESERVED_79 = 0x79,
+    _RESERVED_7a = 0x7a,
+    _RESERVED_7b = 0x7b,
+    _RESERVED_7c = 0x7c,
+    _RESERVED_7d = 0x7d,
+    _RESERVED_7e = 0x7e,
+    _RESERVED_7f = 0x7f,
+    _RESERVED_80 = 0x80,
+    _RESERVED_81 = 0x81,
+    _RESERVED_82 = 0x82,
+    _RESERVED_83 = 0x83,
+    _RESERVED_84 = 0x84,
+    _RESERVED_85 = 0x85,
+    _RESERVED_86 = 0x86,
+    _RESERVED_87 = 0x87,
+    _RESERVED_88 = 0x88,
+    _RESERVED_89 = 0x89,
+    _RESERVED_8a = 0x8a,
+    _RESERVED_8b = 0x8b,
+    _RESERVED_8c = 0x8c,
+    _RESERVED_8d = 0x8d,
+    _RESERVED_8e = 0x8e,
+    _RESERVED_8f = 0x8f,
+    _RESERVED_90 = 0x90,
+    _RESERVED_91 = 0x91,
+    _RESERVED_92 = 0x92,
+    _RESERVED_93 = 0x93,
+    _RESERVED_94 = 0x94,
+    _RESERVED_95 = 0x95,
+    _RESERVED_96 = 0x96,
+    _RESERVED_97 = 0x97,
+    _RESERVED_98 = 0x98,
+    _RESERVED_99 = 0x99,
+    _RESERVED_9a = 0x9a,
+    _RESERVED_9b = 0x9b,
+    _RESERVED_9c = 0x9c,
+    _RESERVED_9d = 0x9d,
+    _RESERVED_9e = 0x9e,
+    _RESERVED_9f = 0x9f,
+    _RESERVED_a0 = 0xa0,
+    _RESERVED_a1 = 0xa1,
+    _RESERVED_a2 = 0xa2,
+    _RESERVED_a3 = 0xa3,
+    _RESERVED_a4 = 0xa4,
+    _RESERVED_a5 = 0xa5,
+    _RESERVED_a6 = 0xa6,
+    _RESERVED_a7 = 0xa7,
+    _RESERVED_a8 = 0xa8,
+    _RESERVED_a9 = 0xa9,
+    _RESERVED_aa = 0xaa,
+    _RESERVED_ab = 0xab,
+    _RESERVED_ac = 0xac,
+    _RESERVED_ad = 0xad,
+    _RESERVED_ae = 0xae,
+    _RESERVED_af = 0xaf,
+    _RESERVED_b0 = 0xb0,
+    _RESERVED_b1 = 0xb1,
+    _RESERVED_b2 = 0xb2,
+    _RESERVED_b3 = 0xb3,
+    _RESERVED_b4 = 0xb4,
+    _RESERVED_b5 = 0xb5,
+    _RESERVED_b6 = 0xb6,
+    _RESERVED_b7 = 0xb7,
+    _RESERVED_b8 = 0xb8,
+    _RESERVED_b9 = 0xb9,
+    _RESERVED_ba = 0xba,
+    _RESERVED_bb = 0xbb,
+    _RESERVED_bc = 0xbc,
+    _RESERVED_bd = 0xbd,
+    _RESERVED_be = 0xbe,
+    _RESERVED_bf = 0xbf,
+    _RESERVED_c0 = 0xc0,
+    _RESERVED_c1 = 0xc1,
+    _RESERVED_c2 = 0xc2,
+    _RESERVED_c3 = 0xc3,
+    _RESERVED_c4 = 0xc4,
+    _RESERVED_c5 = 0xc5,
+    _RESERVED_c6 = 0xc6,
+    _RESERVED_c7 = 0xc7,
+    _RESERVED_c8 = 0xc8,
+    _RESERVED_c9 = 0xc9,
+    _RESERVED_ca = 0xca,
+    _RESERVED_cb = 0xcb,
+    _RESERVED_cc = 0xcc,
+    _RESERVED_cd = 0xcd,
+    _RESERVED_ce = 0xce,
+    _RESERVED_cf = 0xcf,
+    _RESERVED_d0 = 0xd0,
+    _RESERVED_d1 = 0xd1,
+    _RESERVED_d2 = 0xd2,
+    _RESERVED_d3 = 0xd3,
+    _RESERVED_d4 = 0xd4,
+    _RESERVED_d5 = 0xd5,
+    _RESERVED_d6 = 0xd6,
+    _RESERVED_d7 = 0xd7,
+    _RESERVED_d8 = 0xd8,
+    _RESERVED_d9 = 0xd9,
+    _RESERVED_da = 0xda,
+    _RESERVED_db = 0xdb,
+    _RESERVED_dc = 0xdc,
+    _RESERVED_dd = 0xdd,
+    _RESERVED_de = 0xde,
+    _RESERVED_df = 0xdf,
+    _RESERVED_e0 = 0xe0,
+    _RESERVED_e1 = 0xe1,
+    _RESERVED_e2 = 0xe2,
+    _RESERVED_e3 = 0xe3,
+    _RESERVED_e4 = 0xe4,
+    _RESERVED_e5 = 0xe5,
+    _RESERVED_e6 = 0xe6,
+    _RESERVED_e7 = 0xe7,
+    _RESERVED_e8 = 0xe8,
+    _RESERVED_e9 = 0xe9,
+    _RESERVED_ea = 0xea,
+    _RESERVED_eb = 0xeb,
+    _RESERVED_ec = 0xec,
+    _RESERVED_ed = 0xed,
+    _RESERVED_ee = 0xee,
+    _RESERVED_ef = 0xef,
+    _RESERVED_f0 = 0xf0,
+    _RESERVED_f1 = 0xf1,
+    _RESERVED_f2 = 0xf2,
+    _RESERVED_f3 = 0xf3,
+    _RESERVED_f4 = 0xf4,
+    _RESERVED_f5 = 0xf5,
+    _RESERVED_f6 = 0xf6,
+    _RESERVED_f7 = 0xf7,
+    _RESERVED_f8 = 0xf8,
+    _RESERVED_f9 = 0xf9,
+    _RESERVED_fa = 0xfa,
+    _RESERVED_fb = 0xfb,
+    _RESERVED_fc = 0xfc,
+    _RESERVED_fd = 0xfd,
+    _RESERVED_fe = 0xfe,
+    _RESERVED_ff = 0xff,
+}
 impl Fc0src {
-    pub const NULL: Self = Self(0);
-    pub const PLL_SYS_CLKSRC_PRIMARY: Self = Self(0x01);
-    pub const PLL_USB_CLKSRC_PRIMARY: Self = Self(0x02);
-    pub const ROSC_CLKSRC: Self = Self(0x03);
-    pub const ROSC_CLKSRC_PH: Self = Self(0x04);
-    pub const XOSC_CLKSRC: Self = Self(0x05);
-    pub const CLKSRC_GPIN0: Self = Self(0x06);
-    pub const CLKSRC_GPIN1: Self = Self(0x07);
-    pub const CLK_REF: Self = Self(0x08);
-    pub const CLK_SYS: Self = Self(0x09);
-    pub const CLK_PERI: Self = Self(0x0a);
-    pub const CLK_USB: Self = Self(0x0b);
-    pub const CLK_ADC: Self = Self(0x0c);
-    pub const CLK_RTC: Self = Self(0x0d);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Fc0src {
+        unsafe { core::mem::transmute(val & 0xff) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Fc0src {
+    #[inline(always)]
+    fn from(val: u8) -> Fc0src {
+        Fc0src::from_bits(val)
+    }
+}
+impl From<Fc0src> for u8 {
+    #[inline(always)]
+    fn from(val: Fc0src) -> u8 {
+        Fc0src::to_bits(val)
+    }
 }
diff --git a/src/dma.rs b/src/dma.rs
index 001a784e..b60413c3 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -13,82 +13,82 @@ impl Channel {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "DMA Channel 8 Read Address pointer This register updates automatically each time a read completes. The current value is the next address to be read by this channel."]
+    #[doc = "DMA Channel 11 Read Address pointer This register updates automatically each time a read completes. The current value is the next address to be read by this channel."]
     #[inline(always)]
     pub const fn read_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
-    #[doc = "DMA Channel 8 Write Address pointer This register updates automatically each time a write completes. The current value is the next address to be written by this channel."]
+    #[doc = "DMA Channel 11 Write Address pointer This register updates automatically each time a write completes. The current value is the next address to be written by this channel."]
     #[inline(always)]
     pub const fn write_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
-    #[doc = "DMA Channel 8 Transfer Count Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
+    #[doc = "DMA Channel 11 Transfer Count Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
     #[inline(always)]
     pub const fn trans_count(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
-    #[doc = "DMA Channel 8 Control and Status"]
+    #[doc = "DMA Channel 11 Control and Status"]
     #[inline(always)]
     pub const fn ctrl_trig(self) -> crate::common::Reg<regs::CtrlTrig, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
     }
-    #[doc = "Alias for channel 8 CTRL register"]
+    #[doc = "Alias for channel 11 CTRL register"]
     #[inline(always)]
     pub const fn al1_ctrl(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
     }
-    #[doc = "Alias for channel 8 READ_ADDR register"]
+    #[doc = "Alias for channel 11 READ_ADDR register"]
     #[inline(always)]
     pub const fn al1_read_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(20usize) as _) }
     }
-    #[doc = "Alias for channel 8 WRITE_ADDR register"]
+    #[doc = "Alias for channel 11 WRITE_ADDR register"]
     #[inline(always)]
     pub const fn al1_write_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(24usize) as _) }
     }
-    #[doc = "Alias for channel 8 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
+    #[doc = "Alias for channel 11 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
     #[inline(always)]
     pub const fn al1_trans_count_trig(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(28usize) as _) }
     }
-    #[doc = "Alias for channel 8 CTRL register"]
+    #[doc = "Alias for channel 11 CTRL register"]
     #[inline(always)]
     pub const fn al2_ctrl(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(32usize) as _) }
     }
-    #[doc = "Alias for channel 8 TRANS_COUNT register"]
+    #[doc = "Alias for channel 11 TRANS_COUNT register"]
     #[inline(always)]
     pub const fn al2_trans_count(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(36usize) as _) }
     }
-    #[doc = "Alias for channel 8 READ_ADDR register"]
+    #[doc = "Alias for channel 11 READ_ADDR register"]
     #[inline(always)]
     pub const fn al2_read_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(40usize) as _) }
     }
-    #[doc = "Alias for channel 8 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
+    #[doc = "Alias for channel 11 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
     #[inline(always)]
     pub const fn al2_write_addr_trig(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(44usize) as _) }
     }
-    #[doc = "Alias for channel 8 CTRL register"]
+    #[doc = "Alias for channel 11 CTRL register"]
     #[inline(always)]
     pub const fn al3_ctrl(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(48usize) as _) }
     }
-    #[doc = "Alias for channel 8 WRITE_ADDR register"]
+    #[doc = "Alias for channel 11 WRITE_ADDR register"]
     #[inline(always)]
     pub const fn al3_write_addr(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(52usize) as _) }
     }
-    #[doc = "Alias for channel 8 TRANS_COUNT register"]
+    #[doc = "Alias for channel 11 TRANS_COUNT register"]
     #[inline(always)]
     pub const fn al3_trans_count(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(56usize) as _) }
     }
-    #[doc = "Alias for channel 8 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
+    #[doc = "Alias for channel 11 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."]
     #[inline(always)]
     pub const fn al3_read_addr_trig(self) -> crate::common::Reg<u32, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(60usize) as _) }
diff --git a/src/dma/regs.rs b/src/dma/regs.rs
index 9a5ba98c..3306ca56 100644
--- a/src/dma/regs.rs
+++ b/src/dma/regs.rs
@@ -21,7 +21,7 @@ impl Default for ChanAbort {
         ChanAbort(0)
     }
 }
-#[doc = "DMA Channel 4 Control and Status"]
+#[doc = "DMA Channel 6 Control and Status"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct CtrlTrig(pub u32);
@@ -52,12 +52,12 @@ impl CtrlTrig {
     #[inline(always)]
     pub const fn data_size(&self) -> super::vals::DataSize {
         let val = (self.0 >> 2usize) & 0x03;
-        super::vals::DataSize(val as u8)
+        super::vals::DataSize::from_bits(val as u8)
     }
     #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
     #[inline(always)]
     pub fn set_data_size(&mut self, val: super::vals::DataSize) {
-        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.0 as u32) & 0x03) << 2usize);
+        self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize);
     }
     #[doc = "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."]
     #[inline(always)]
@@ -118,12 +118,12 @@ impl CtrlTrig {
     #[inline(always)]
     pub const fn treq_sel(&self) -> super::vals::TreqSel {
         let val = (self.0 >> 15usize) & 0x3f;
-        super::vals::TreqSel(val as u8)
+        super::vals::TreqSel::from_bits(val as u8)
     }
     #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"]
     #[inline(always)]
     pub fn set_treq_sel(&mut self, val: super::vals::TreqSel) {
-        self.0 = (self.0 & !(0x3f << 15usize)) | (((val.0 as u32) & 0x3f) << 15usize);
+        self.0 = (self.0 & !(0x3f << 15usize)) | (((val.to_bits() as u32) & 0x3f) << 15usize);
     }
     #[doc = "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
     #[inline(always)]
@@ -215,12 +215,12 @@ impl Default for CtrlTrig {
 pub struct DbgCtdreq(pub u32);
 impl DbgCtdreq {
     #[inline(always)]
-    pub const fn ch8_dbg_ctdreq(&self) -> u8 {
+    pub const fn dbg_ctdreq(&self) -> u8 {
         let val = (self.0 >> 0usize) & 0x3f;
         val as u8
     }
     #[inline(always)]
-    pub fn set_ch8_dbg_ctdreq(&mut self, val: u8) {
+    pub fn set_dbg_ctdreq(&mut self, val: u8) {
         self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
     }
 }
@@ -510,11 +510,11 @@ impl SniffCtrl {
     #[inline(always)]
     pub const fn calc(&self) -> super::vals::Calc {
         let val = (self.0 >> 5usize) & 0x0f;
-        super::vals::Calc(val as u8)
+        super::vals::Calc::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_calc(&mut self, val: super::vals::Calc) {
-        self.0 = (self.0 & !(0x0f << 5usize)) | (((val.0 as u32) & 0x0f) << 5usize);
+        self.0 = (self.0 & !(0x0f << 5usize)) | (((val.to_bits() as u32) & 0x0f) << 5usize);
     }
     #[doc = "Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."]
     #[inline(always)]
diff --git a/src/dma/vals.rs b/src/dma/vals.rs
index 74b43c7c..7e3ca402 100644
--- a/src/dma/vals.rs
+++ b/src/dma/vals.rs
@@ -1,27 +1,80 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Calc(pub u8);
-impl Calc {
+pub enum Calc {
     #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"]
-    pub const CRC32: Self = Self(0);
+    CRC32 = 0,
     #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"]
-    pub const CRC32R: Self = Self(0x01);
+    CRC32R = 0x01,
     #[doc = "Calculate a CRC-16-CCITT"]
-    pub const CRC16: Self = Self(0x02);
+    CRC16 = 0x02,
     #[doc = "Calculate a CRC-16-CCITT with bit reversed data"]
-    pub const CRC16R: Self = Self(0x03);
+    CRC16R = 0x03,
+    _RESERVED_4 = 0x04,
+    _RESERVED_5 = 0x05,
+    _RESERVED_6 = 0x06,
+    _RESERVED_7 = 0x07,
+    _RESERVED_8 = 0x08,
+    _RESERVED_9 = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
     #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."]
-    pub const EVEN: Self = Self(0x0e);
+    EVEN = 0x0e,
     #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"]
-    pub const SUM: Self = Self(0x0f);
+    SUM = 0x0f,
 }
-#[repr(transparent)]
+impl Calc {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Calc {
+        unsafe { core::mem::transmute(val & 0x0f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Calc {
+    #[inline(always)]
+    fn from(val: u8) -> Calc {
+        Calc::from_bits(val)
+    }
+}
+impl From<Calc> for u8 {
+    #[inline(always)]
+    fn from(val: Calc) -> u8 {
+        Calc::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct DataSize(pub u8);
+pub enum DataSize {
+    SIZE_BYTE = 0,
+    SIZE_HALFWORD = 0x01,
+    SIZE_WORD = 0x02,
+    _RESERVED_3 = 0x03,
+}
 impl DataSize {
-    pub const SIZE_BYTE: Self = Self(0);
-    pub const SIZE_HALFWORD: Self = Self(0x01);
-    pub const SIZE_WORD: Self = Self(0x02);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> DataSize {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for DataSize {
+    #[inline(always)]
+    fn from(val: u8) -> DataSize {
+        DataSize::from_bits(val)
+    }
+}
+impl From<DataSize> for u8 {
+    #[inline(always)]
+    fn from(val: DataSize) -> u8 {
+        DataSize::to_bits(val)
+    }
 }
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -38,3 +91,23 @@ impl TreqSel {
     #[doc = "Permanent request, for unpaced transfers."]
     pub const PERMANENT: Self = Self(0x3f);
 }
+impl TreqSel {
+    pub const fn from_bits(val: u8) -> TreqSel {
+        Self(val & 0x3f)
+    }
+    pub const fn to_bits(self) -> u8 {
+        self.0
+    }
+}
+impl From<u8> for TreqSel {
+    #[inline(always)]
+    fn from(val: u8) -> TreqSel {
+        TreqSel::from_bits(val)
+    }
+}
+impl From<TreqSel> for u8 {
+    #[inline(always)]
+    fn from(val: TreqSel) -> u8 {
+        TreqSel::to_bits(val)
+    }
+}
diff --git a/src/i2c/regs.rs b/src/i2c/regs.rs
index 18eb4a9d..523318fe 100644
--- a/src/i2c/regs.rs
+++ b/src/i2c/regs.rs
@@ -417,12 +417,12 @@ impl IcCon {
     #[inline(always)]
     pub const fn speed(&self) -> super::vals::Speed {
         let val = (self.0 >> 1usize) & 0x03;
-        super::vals::Speed(val as u8)
+        super::vals::Speed::from_bits(val as u8)
     }
     #[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
     #[inline(always)]
     pub fn set_speed(&mut self, val: super::vals::Speed) {
-        self.0 = (self.0 & !(0x03 << 1usize)) | (((val.0 as u32) & 0x03) << 1usize);
+        self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
     }
     #[doc = "When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
     #[inline(always)]
diff --git a/src/i2c/vals.rs b/src/i2c/vals.rs
index 339adf9a..41e0860e 100644
--- a/src/i2c/vals.rs
+++ b/src/i2c/vals.rs
@@ -1,11 +1,33 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Speed(pub u8);
-impl Speed {
+pub enum Speed {
+    _RESERVED_0 = 0,
     #[doc = "Standard Speed mode of operation"]
-    pub const STANDARD: Self = Self(0x01);
+    STANDARD = 0x01,
     #[doc = "Fast or Fast Plus mode of operation"]
-    pub const FAST: Self = Self(0x02);
+    FAST = 0x02,
     #[doc = "High Speed mode of operation"]
-    pub const HIGH: Self = Self(0x03);
+    HIGH = 0x03,
+}
+impl Speed {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Speed {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Speed {
+    #[inline(always)]
+    fn from(val: u8) -> Speed {
+        Speed::from_bits(val)
+    }
+}
+impl From<Speed> for u8 {
+    #[inline(always)]
+    fn from(val: Speed) -> u8 {
+        Speed::to_bits(val)
+    }
 }
diff --git a/src/io.rs b/src/io.rs
index c5500440..6af22042 100644
--- a/src/io.rs
+++ b/src/io.rs
@@ -39,19 +39,19 @@ impl Int {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "Interrupt Enable for dormant_wake"]
+    #[doc = "Interrupt Enable for proc0"]
     #[inline(always)]
     pub const fn inte(self, n: usize) -> crate::common::Reg<regs::Int, crate::common::RW> {
         assert!(n < 4usize);
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize + n * 4usize) as _) }
     }
-    #[doc = "Interrupt Force for dormant_wake"]
+    #[doc = "Interrupt Force for proc0"]
     #[inline(always)]
     pub const fn intf(self, n: usize) -> crate::common::Reg<regs::Int, crate::common::RW> {
         assert!(n < 4usize);
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize + n * 4usize) as _) }
     }
-    #[doc = "Interrupt status after masking & forcing for dormant_wake"]
+    #[doc = "Interrupt status after masking & forcing for proc0"]
     #[inline(always)]
     pub const fn ints(self, n: usize) -> crate::common::Reg<regs::Int, crate::common::RW> {
         assert!(n < 4usize);
diff --git a/src/io/regs.rs b/src/io/regs.rs
index 2ee2bed7..40595ff9 100644
--- a/src/io/regs.rs
+++ b/src/io/regs.rs
@@ -17,38 +17,38 @@ impl GpioCtrl {
     #[inline(always)]
     pub const fn outover(&self) -> super::vals::Outover {
         let val = (self.0 >> 8usize) & 0x03;
-        super::vals::Outover(val as u8)
+        super::vals::Outover::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_outover(&mut self, val: super::vals::Outover) {
-        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
     }
     #[inline(always)]
     pub const fn oeover(&self) -> super::vals::Oeover {
         let val = (self.0 >> 12usize) & 0x03;
-        super::vals::Oeover(val as u8)
+        super::vals::Oeover::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_oeover(&mut self, val: super::vals::Oeover) {
-        self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+        self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
     }
     #[inline(always)]
     pub const fn inover(&self) -> super::vals::Inover {
         let val = (self.0 >> 16usize) & 0x03;
-        super::vals::Inover(val as u8)
+        super::vals::Inover::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_inover(&mut self, val: super::vals::Inover) {
-        self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
+        self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize);
     }
     #[inline(always)]
     pub const fn irqover(&self) -> super::vals::Irqover {
         let val = (self.0 >> 28usize) & 0x03;
-        super::vals::Irqover(val as u8)
+        super::vals::Irqover::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_irqover(&mut self, val: super::vals::Irqover) {
-        self.0 = (self.0 & !(0x03 << 28usize)) | (((val.0 as u32) & 0x03) << 28usize);
+        self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize);
     }
 }
 impl Default for GpioCtrl {
@@ -157,7 +157,7 @@ impl Default for GpioStatus {
         GpioStatus(0)
     }
 }
-#[doc = "Interrupt Force for dormant_wake"]
+#[doc = "Interrupt status after masking & forcing for dormant_wake"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/io/vals.rs b/src/io/vals.rs
index f4ce8918..91264334 100644
--- a/src/io/vals.rs
+++ b/src/io/vals.rs
@@ -1,493 +1,1876 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio0ctrlFuncsel(pub u8);
+pub enum Gpio0ctrlFuncsel {
+    JTAG_TCK = 0,
+    SPI0_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_0 = 0x04,
+    SIO_0 = 0x05,
+    PIO0_0 = 0x06,
+    PIO1_0 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio0ctrlFuncsel {
-    pub const JTAG_TCK: Self = Self(0);
-    pub const SPI0_RX: Self = Self(0x01);
-    pub const UART0_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_0: Self = Self(0x04);
-    pub const SIO_0: Self = Self(0x05);
-    pub const PIO0_0: Self = Self(0x06);
-    pub const PIO1_0: Self = Self(0x07);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio10ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio0ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio0ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio0ctrlFuncsel {
+        Gpio0ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio0ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio0ctrlFuncsel) -> u8 {
+        Gpio0ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio10ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_5 = 0x04,
+    SIO_10 = 0x05,
+    PIO0_10 = 0x06,
+    PIO1_10 = 0x07,
+    USB_MUXING_EXTPHY_VM = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio10ctrlFuncsel {
-    pub const SPI1_SCLK: Self = Self(0x01);
-    pub const UART1_CTS: Self = Self(0x02);
-    pub const I2C1_SDA: Self = Self(0x03);
-    pub const PWM_A_5: Self = Self(0x04);
-    pub const SIO_10: Self = Self(0x05);
-    pub const PIO0_10: Self = Self(0x06);
-    pub const PIO1_10: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_VM: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio11ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio10ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio10ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio10ctrlFuncsel {
+        Gpio10ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio10ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio10ctrlFuncsel) -> u8 {
+        Gpio10ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio11ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_5 = 0x04,
+    SIO_11 = 0x05,
+    PIO0_11 = 0x06,
+    PIO1_11 = 0x07,
+    USB_MUXING_EXTPHY_SUSPND = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio11ctrlFuncsel {
-    pub const SPI1_TX: Self = Self(0x01);
-    pub const UART1_RTS: Self = Self(0x02);
-    pub const I2C1_SCL: Self = Self(0x03);
-    pub const PWM_B_5: Self = Self(0x04);
-    pub const SIO_11: Self = Self(0x05);
-    pub const PIO0_11: Self = Self(0x06);
-    pub const PIO1_11: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_SUSPND: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio12ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio11ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio11ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio11ctrlFuncsel {
+        Gpio11ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio11ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio11ctrlFuncsel) -> u8 {
+        Gpio11ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio12ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_6 = 0x04,
+    SIO_12 = 0x05,
+    PIO0_12 = 0x06,
+    PIO1_12 = 0x07,
+    USB_MUXING_EXTPHY_SPEED = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio12ctrlFuncsel {
-    pub const SPI1_RX: Self = Self(0x01);
-    pub const UART0_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_6: Self = Self(0x04);
-    pub const SIO_12: Self = Self(0x05);
-    pub const PIO0_12: Self = Self(0x06);
-    pub const PIO1_12: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_SPEED: Self = Self(0x08);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio13ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio12ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio12ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio12ctrlFuncsel {
+        Gpio12ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio12ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio12ctrlFuncsel) -> u8 {
+        Gpio12ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio13ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_6 = 0x04,
+    SIO_13 = 0x05,
+    PIO0_13 = 0x06,
+    PIO1_13 = 0x07,
+    USB_MUXING_EXTPHY_VPO = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio13ctrlFuncsel {
-    pub const SPI1_SS_N: Self = Self(0x01);
-    pub const UART0_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_6: Self = Self(0x04);
-    pub const SIO_13: Self = Self(0x05);
-    pub const PIO0_13: Self = Self(0x06);
-    pub const PIO1_13: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_VPO: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio14ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio13ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio13ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio13ctrlFuncsel {
+        Gpio13ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio13ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio13ctrlFuncsel) -> u8 {
+        Gpio13ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio14ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_7 = 0x04,
+    SIO_14 = 0x05,
+    PIO0_14 = 0x06,
+    PIO1_14 = 0x07,
+    USB_MUXING_EXTPHY_VMO = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio14ctrlFuncsel {
-    pub const SPI1_SCLK: Self = Self(0x01);
-    pub const UART0_CTS: Self = Self(0x02);
-    pub const I2C1_SDA: Self = Self(0x03);
-    pub const PWM_A_7: Self = Self(0x04);
-    pub const SIO_14: Self = Self(0x05);
-    pub const PIO0_14: Self = Self(0x06);
-    pub const PIO1_14: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_VMO: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio15ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio14ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio14ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio14ctrlFuncsel {
+        Gpio14ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio14ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio14ctrlFuncsel) -> u8 {
+        Gpio14ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio15ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_7 = 0x04,
+    SIO_15 = 0x05,
+    PIO0_15 = 0x06,
+    PIO1_15 = 0x07,
+    USB_MUXING_DIGITAL_DP = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio15ctrlFuncsel {
-    pub const SPI1_TX: Self = Self(0x01);
-    pub const UART0_RTS: Self = Self(0x02);
-    pub const I2C1_SCL: Self = Self(0x03);
-    pub const PWM_B_7: Self = Self(0x04);
-    pub const SIO_15: Self = Self(0x05);
-    pub const PIO0_15: Self = Self(0x06);
-    pub const PIO1_15: Self = Self(0x07);
-    pub const USB_MUXING_DIGITAL_DP: Self = Self(0x08);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio16ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio15ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio15ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio15ctrlFuncsel {
+        Gpio15ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio15ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio15ctrlFuncsel) -> u8 {
+        Gpio15ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio16ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_0 = 0x04,
+    SIO_16 = 0x05,
+    PIO0_16 = 0x06,
+    PIO1_16 = 0x07,
+    USB_MUXING_DIGITAL_DM = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio16ctrlFuncsel {
-    pub const SPI0_RX: Self = Self(0x01);
-    pub const UART0_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_0: Self = Self(0x04);
-    pub const SIO_16: Self = Self(0x05);
-    pub const PIO0_16: Self = Self(0x06);
-    pub const PIO1_16: Self = Self(0x07);
-    pub const USB_MUXING_DIGITAL_DM: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio17ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio16ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio16ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio16ctrlFuncsel {
+        Gpio16ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio16ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio16ctrlFuncsel) -> u8 {
+        Gpio16ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio17ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_0 = 0x04,
+    SIO_17 = 0x05,
+    PIO0_17 = 0x06,
+    PIO1_17 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio17ctrlFuncsel {
-    pub const SPI0_SS_N: Self = Self(0x01);
-    pub const UART0_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_0: Self = Self(0x04);
-    pub const SIO_17: Self = Self(0x05);
-    pub const PIO0_17: Self = Self(0x06);
-    pub const PIO1_17: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio18ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio17ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio17ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio17ctrlFuncsel {
+        Gpio17ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio17ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio17ctrlFuncsel) -> u8 {
+        Gpio17ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio18ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_1 = 0x04,
+    SIO_18 = 0x05,
+    PIO0_18 = 0x06,
+    PIO1_18 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio18ctrlFuncsel {
-    pub const SPI0_SCLK: Self = Self(0x01);
-    pub const UART0_CTS: Self = Self(0x02);
-    pub const I2C1_SDA: Self = Self(0x03);
-    pub const PWM_A_1: Self = Self(0x04);
-    pub const SIO_18: Self = Self(0x05);
-    pub const PIO0_18: Self = Self(0x06);
-    pub const PIO1_18: Self = Self(0x07);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio19ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio18ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio18ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio18ctrlFuncsel {
+        Gpio18ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio18ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio18ctrlFuncsel) -> u8 {
+        Gpio18ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio19ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_1 = 0x04,
+    SIO_19 = 0x05,
+    PIO0_19 = 0x06,
+    PIO1_19 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio19ctrlFuncsel {
-    pub const SPI0_TX: Self = Self(0x01);
-    pub const UART0_RTS: Self = Self(0x02);
-    pub const I2C1_SCL: Self = Self(0x03);
-    pub const PWM_B_1: Self = Self(0x04);
-    pub const SIO_19: Self = Self(0x05);
-    pub const PIO0_19: Self = Self(0x06);
-    pub const PIO1_19: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio1ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio19ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio19ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio19ctrlFuncsel {
+        Gpio19ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio19ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio19ctrlFuncsel) -> u8 {
+        Gpio19ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio1ctrlFuncsel {
+    JTAG_TMS = 0,
+    SPI0_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_0 = 0x04,
+    SIO_1 = 0x05,
+    PIO0_1 = 0x06,
+    PIO1_1 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio1ctrlFuncsel {
-    pub const JTAG_TMS: Self = Self(0);
-    pub const SPI0_SS_N: Self = Self(0x01);
-    pub const UART0_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_0: Self = Self(0x04);
-    pub const SIO_1: Self = Self(0x05);
-    pub const PIO0_1: Self = Self(0x06);
-    pub const PIO1_1: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio20ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio1ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio1ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio1ctrlFuncsel {
+        Gpio1ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio1ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio1ctrlFuncsel) -> u8 {
+        Gpio1ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio20ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_2 = 0x04,
+    SIO_20 = 0x05,
+    PIO0_20 = 0x06,
+    PIO1_20 = 0x07,
+    CLOCKS_GPIN_0 = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio20ctrlFuncsel {
-    pub const SPI0_RX: Self = Self(0x01);
-    pub const UART1_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_2: Self = Self(0x04);
-    pub const SIO_20: Self = Self(0x05);
-    pub const PIO0_20: Self = Self(0x06);
-    pub const PIO1_20: Self = Self(0x07);
-    pub const CLOCKS_GPIN_0: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio21ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio20ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio20ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio20ctrlFuncsel {
+        Gpio20ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio20ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio20ctrlFuncsel) -> u8 {
+        Gpio20ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio21ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_2 = 0x04,
+    SIO_21 = 0x05,
+    PIO0_21 = 0x06,
+    PIO1_21 = 0x07,
+    CLOCKS_GPOUT_0 = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio21ctrlFuncsel {
-    pub const SPI0_SS_N: Self = Self(0x01);
-    pub const UART1_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_2: Self = Self(0x04);
-    pub const SIO_21: Self = Self(0x05);
-    pub const PIO0_21: Self = Self(0x06);
-    pub const PIO1_21: Self = Self(0x07);
-    pub const CLOCKS_GPOUT_0: Self = Self(0x08);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio22ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio21ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio21ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio21ctrlFuncsel {
+        Gpio21ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio21ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio21ctrlFuncsel) -> u8 {
+        Gpio21ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio22ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_3 = 0x04,
+    SIO_22 = 0x05,
+    PIO0_22 = 0x06,
+    PIO1_22 = 0x07,
+    CLOCKS_GPIN_1 = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio22ctrlFuncsel {
-    pub const SPI0_SCLK: Self = Self(0x01);
-    pub const UART1_CTS: Self = Self(0x02);
-    pub const I2C1_SDA: Self = Self(0x03);
-    pub const PWM_A_3: Self = Self(0x04);
-    pub const SIO_22: Self = Self(0x05);
-    pub const PIO0_22: Self = Self(0x06);
-    pub const PIO1_22: Self = Self(0x07);
-    pub const CLOCKS_GPIN_1: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio23ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio22ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio22ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio22ctrlFuncsel {
+        Gpio22ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio22ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio22ctrlFuncsel) -> u8 {
+        Gpio22ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio23ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_3 = 0x04,
+    SIO_23 = 0x05,
+    PIO0_23 = 0x06,
+    PIO1_23 = 0x07,
+    CLOCKS_GPOUT_1 = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio23ctrlFuncsel {
-    pub const SPI0_TX: Self = Self(0x01);
-    pub const UART1_RTS: Self = Self(0x02);
-    pub const I2C1_SCL: Self = Self(0x03);
-    pub const PWM_B_3: Self = Self(0x04);
-    pub const SIO_23: Self = Self(0x05);
-    pub const PIO0_23: Self = Self(0x06);
-    pub const PIO1_23: Self = Self(0x07);
-    pub const CLOCKS_GPOUT_1: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio24ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio23ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio23ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio23ctrlFuncsel {
+        Gpio23ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio23ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio23ctrlFuncsel) -> u8 {
+        Gpio23ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio24ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_4 = 0x04,
+    SIO_24 = 0x05,
+    PIO0_24 = 0x06,
+    PIO1_24 = 0x07,
+    CLOCKS_GPOUT_2 = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio24ctrlFuncsel {
-    pub const SPI1_RX: Self = Self(0x01);
-    pub const UART1_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_4: Self = Self(0x04);
-    pub const SIO_24: Self = Self(0x05);
-    pub const PIO0_24: Self = Self(0x06);
-    pub const PIO1_24: Self = Self(0x07);
-    pub const CLOCKS_GPOUT_2: Self = Self(0x08);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio25ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio24ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio24ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio24ctrlFuncsel {
+        Gpio24ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio24ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio24ctrlFuncsel) -> u8 {
+        Gpio24ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio25ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_4 = 0x04,
+    SIO_25 = 0x05,
+    PIO0_25 = 0x06,
+    PIO1_25 = 0x07,
+    CLOCKS_GPOUT_3 = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio25ctrlFuncsel {
-    pub const SPI1_SS_N: Self = Self(0x01);
-    pub const UART1_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_4: Self = Self(0x04);
-    pub const SIO_25: Self = Self(0x05);
-    pub const PIO0_25: Self = Self(0x06);
-    pub const PIO1_25: Self = Self(0x07);
-    pub const CLOCKS_GPOUT_3: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio26ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio25ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio25ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio25ctrlFuncsel {
+        Gpio25ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio25ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio25ctrlFuncsel) -> u8 {
+        Gpio25ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio26ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_5 = 0x04,
+    SIO_26 = 0x05,
+    PIO0_26 = 0x06,
+    PIO1_26 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio26ctrlFuncsel {
-    pub const SPI1_SCLK: Self = Self(0x01);
-    pub const UART1_CTS: Self = Self(0x02);
-    pub const I2C1_SDA: Self = Self(0x03);
-    pub const PWM_A_5: Self = Self(0x04);
-    pub const SIO_26: Self = Self(0x05);
-    pub const PIO0_26: Self = Self(0x06);
-    pub const PIO1_26: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio27ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio26ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio26ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio26ctrlFuncsel {
+        Gpio26ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio26ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio26ctrlFuncsel) -> u8 {
+        Gpio26ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio27ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_5 = 0x04,
+    SIO_27 = 0x05,
+    PIO0_27 = 0x06,
+    PIO1_27 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio27ctrlFuncsel {
-    pub const SPI1_TX: Self = Self(0x01);
-    pub const UART1_RTS: Self = Self(0x02);
-    pub const I2C1_SCL: Self = Self(0x03);
-    pub const PWM_B_5: Self = Self(0x04);
-    pub const SIO_27: Self = Self(0x05);
-    pub const PIO0_27: Self = Self(0x06);
-    pub const PIO1_27: Self = Self(0x07);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio28ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio27ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio27ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio27ctrlFuncsel {
+        Gpio27ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio27ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio27ctrlFuncsel) -> u8 {
+        Gpio27ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio28ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART0_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_6 = 0x04,
+    SIO_28 = 0x05,
+    PIO0_28 = 0x06,
+    PIO1_28 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio28ctrlFuncsel {
-    pub const SPI1_RX: Self = Self(0x01);
-    pub const UART0_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_6: Self = Self(0x04);
-    pub const SIO_28: Self = Self(0x05);
-    pub const PIO0_28: Self = Self(0x06);
-    pub const PIO1_28: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio29ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio28ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio28ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio28ctrlFuncsel {
+        Gpio28ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio28ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio28ctrlFuncsel) -> u8 {
+        Gpio28ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio29ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART0_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_6 = 0x04,
+    SIO_29 = 0x05,
+    PIO0_29 = 0x06,
+    PIO1_29 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio29ctrlFuncsel {
-    pub const SPI1_SS_N: Self = Self(0x01);
-    pub const UART0_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_6: Self = Self(0x04);
-    pub const SIO_29: Self = Self(0x05);
-    pub const PIO0_29: Self = Self(0x06);
-    pub const PIO1_29: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio2ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio29ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio29ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio29ctrlFuncsel {
+        Gpio29ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio29ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio29ctrlFuncsel) -> u8 {
+        Gpio29ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio2ctrlFuncsel {
+    JTAG_TDI = 0,
+    SPI0_SCLK = 0x01,
+    UART0_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_1 = 0x04,
+    SIO_2 = 0x05,
+    PIO0_2 = 0x06,
+    PIO1_2 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio2ctrlFuncsel {
-    pub const JTAG_TDI: Self = Self(0);
-    pub const SPI0_SCLK: Self = Self(0x01);
-    pub const UART0_CTS: Self = Self(0x02);
-    pub const I2C1_SDA: Self = Self(0x03);
-    pub const PWM_A_1: Self = Self(0x04);
-    pub const SIO_2: Self = Self(0x05);
-    pub const PIO0_2: Self = Self(0x06);
-    pub const PIO1_2: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio3ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio2ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio2ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio2ctrlFuncsel {
+        Gpio2ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio2ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio2ctrlFuncsel) -> u8 {
+        Gpio2ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio3ctrlFuncsel {
+    JTAG_TDO = 0,
+    SPI0_TX = 0x01,
+    UART0_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_1 = 0x04,
+    SIO_3 = 0x05,
+    PIO0_3 = 0x06,
+    PIO1_3 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio3ctrlFuncsel {
-    pub const JTAG_TDO: Self = Self(0);
-    pub const SPI0_TX: Self = Self(0x01);
-    pub const UART0_RTS: Self = Self(0x02);
-    pub const I2C1_SCL: Self = Self(0x03);
-    pub const PWM_B_1: Self = Self(0x04);
-    pub const SIO_3: Self = Self(0x05);
-    pub const PIO0_3: Self = Self(0x06);
-    pub const PIO1_3: Self = Self(0x07);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio4ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio3ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio3ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio3ctrlFuncsel {
+        Gpio3ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio3ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio3ctrlFuncsel) -> u8 {
+        Gpio3ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio4ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_2 = 0x04,
+    SIO_4 = 0x05,
+    PIO0_4 = 0x06,
+    PIO1_4 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio4ctrlFuncsel {
-    pub const SPI0_RX: Self = Self(0x01);
-    pub const UART1_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_2: Self = Self(0x04);
-    pub const SIO_4: Self = Self(0x05);
-    pub const PIO0_4: Self = Self(0x06);
-    pub const PIO1_4: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio5ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio4ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio4ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio4ctrlFuncsel {
+        Gpio4ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio4ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio4ctrlFuncsel) -> u8 {
+        Gpio4ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio5ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_2 = 0x04,
+    SIO_5 = 0x05,
+    PIO0_5 = 0x06,
+    PIO1_5 = 0x07,
+    _RESERVED_8 = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio5ctrlFuncsel {
-    pub const SPI0_SS_N: Self = Self(0x01);
-    pub const UART1_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_2: Self = Self(0x04);
-    pub const SIO_5: Self = Self(0x05);
-    pub const PIO0_5: Self = Self(0x06);
-    pub const PIO1_5: Self = Self(0x07);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio6ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio5ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio5ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio5ctrlFuncsel {
+        Gpio5ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio5ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio5ctrlFuncsel) -> u8 {
+        Gpio5ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio6ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_SCLK = 0x01,
+    UART1_CTS = 0x02,
+    I2C1_SDA = 0x03,
+    PWM_A_3 = 0x04,
+    SIO_6 = 0x05,
+    PIO0_6 = 0x06,
+    PIO1_6 = 0x07,
+    USB_MUXING_EXTPHY_SOFTCON = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio6ctrlFuncsel {
-    pub const SPI0_SCLK: Self = Self(0x01);
-    pub const UART1_CTS: Self = Self(0x02);
-    pub const I2C1_SDA: Self = Self(0x03);
-    pub const PWM_A_3: Self = Self(0x04);
-    pub const SIO_6: Self = Self(0x05);
-    pub const PIO0_6: Self = Self(0x06);
-    pub const PIO1_6: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_SOFTCON: Self = Self(0x08);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio7ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio6ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio6ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio6ctrlFuncsel {
+        Gpio6ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio6ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio6ctrlFuncsel) -> u8 {
+        Gpio6ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio7ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI0_TX = 0x01,
+    UART1_RTS = 0x02,
+    I2C1_SCL = 0x03,
+    PWM_B_3 = 0x04,
+    SIO_7 = 0x05,
+    PIO0_7 = 0x06,
+    PIO1_7 = 0x07,
+    USB_MUXING_EXTPHY_OE_N = 0x08,
+    USB_MUXING_VBUS_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio7ctrlFuncsel {
-    pub const SPI0_TX: Self = Self(0x01);
-    pub const UART1_RTS: Self = Self(0x02);
-    pub const I2C1_SCL: Self = Self(0x03);
-    pub const PWM_B_3: Self = Self(0x04);
-    pub const SIO_7: Self = Self(0x05);
-    pub const PIO0_7: Self = Self(0x06);
-    pub const PIO1_7: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_OE_N: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio8ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio7ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio7ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio7ctrlFuncsel {
+        Gpio7ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio7ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio7ctrlFuncsel) -> u8 {
+        Gpio7ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio8ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_RX = 0x01,
+    UART1_TX = 0x02,
+    I2C0_SDA = 0x03,
+    PWM_A_4 = 0x04,
+    SIO_8 = 0x05,
+    PIO0_8 = 0x06,
+    PIO1_8 = 0x07,
+    USB_MUXING_EXTPHY_RCV = 0x08,
+    USB_MUXING_VBUS_EN = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio8ctrlFuncsel {
-    pub const SPI1_RX: Self = Self(0x01);
-    pub const UART1_TX: Self = Self(0x02);
-    pub const I2C0_SDA: Self = Self(0x03);
-    pub const PWM_A_4: Self = Self(0x04);
-    pub const SIO_8: Self = Self(0x05);
-    pub const PIO0_8: Self = Self(0x06);
-    pub const PIO1_8: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_RCV: Self = Self(0x08);
-    pub const USB_MUXING_VBUS_EN: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Gpio9ctrlFuncsel(pub u8);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio8ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio8ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio8ctrlFuncsel {
+        Gpio8ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio8ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio8ctrlFuncsel) -> u8 {
+        Gpio8ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Gpio9ctrlFuncsel {
+    _RESERVED_0 = 0,
+    SPI1_SS_N = 0x01,
+    UART1_RX = 0x02,
+    I2C0_SCL = 0x03,
+    PWM_B_4 = 0x04,
+    SIO_9 = 0x05,
+    PIO0_9 = 0x06,
+    PIO1_9 = 0x07,
+    USB_MUXING_EXTPHY_VP = 0x08,
+    USB_MUXING_OVERCURR_DETECT = 0x09,
+    _RESERVED_a = 0x0a,
+    _RESERVED_b = 0x0b,
+    _RESERVED_c = 0x0c,
+    _RESERVED_d = 0x0d,
+    _RESERVED_e = 0x0e,
+    _RESERVED_f = 0x0f,
+    _RESERVED_10 = 0x10,
+    _RESERVED_11 = 0x11,
+    _RESERVED_12 = 0x12,
+    _RESERVED_13 = 0x13,
+    _RESERVED_14 = 0x14,
+    _RESERVED_15 = 0x15,
+    _RESERVED_16 = 0x16,
+    _RESERVED_17 = 0x17,
+    _RESERVED_18 = 0x18,
+    _RESERVED_19 = 0x19,
+    _RESERVED_1a = 0x1a,
+    _RESERVED_1b = 0x1b,
+    _RESERVED_1c = 0x1c,
+    _RESERVED_1d = 0x1d,
+    _RESERVED_1e = 0x1e,
+    NULL = 0x1f,
+}
 impl Gpio9ctrlFuncsel {
-    pub const SPI1_SS_N: Self = Self(0x01);
-    pub const UART1_RX: Self = Self(0x02);
-    pub const I2C0_SCL: Self = Self(0x03);
-    pub const PWM_B_4: Self = Self(0x04);
-    pub const SIO_9: Self = Self(0x05);
-    pub const PIO0_9: Self = Self(0x06);
-    pub const PIO1_9: Self = Self(0x07);
-    pub const USB_MUXING_EXTPHY_VP: Self = Self(0x08);
-    pub const USB_MUXING_OVERCURR_DETECT: Self = Self(0x09);
-    pub const NULL: Self = Self(0x1f);
-}
-#[repr(transparent)]
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Inover(pub u8);
-impl Inover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Gpio9ctrlFuncsel {
+        unsafe { core::mem::transmute(val & 0x1f) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Gpio9ctrlFuncsel {
+    #[inline(always)]
+    fn from(val: u8) -> Gpio9ctrlFuncsel {
+        Gpio9ctrlFuncsel::from_bits(val)
+    }
+}
+impl From<Gpio9ctrlFuncsel> for u8 {
+    #[inline(always)]
+    fn from(val: Gpio9ctrlFuncsel) -> u8 {
+        Gpio9ctrlFuncsel::to_bits(val)
+    }
+}
+#[repr(u8)]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum Inover {
     #[doc = "don't invert the peri input"]
-    pub const NORMAL: Self = Self(0);
+    NORMAL = 0,
     #[doc = "invert the peri input"]
-    pub const INVERT: Self = Self(0x01);
+    INVERT = 0x01,
     #[doc = "drive peri input low"]
-    pub const LOW: Self = Self(0x02);
+    LOW = 0x02,
     #[doc = "drive peri input high"]
-    pub const HIGH: Self = Self(0x03);
+    HIGH = 0x03,
+}
+impl Inover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Inover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Inover {
+    #[inline(always)]
+    fn from(val: u8) -> Inover {
+        Inover::from_bits(val)
+    }
+}
+impl From<Inover> for u8 {
+    #[inline(always)]
+    fn from(val: Inover) -> u8 {
+        Inover::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Irqover(pub u8);
-impl Irqover {
+pub enum Irqover {
     #[doc = "don't invert the interrupt"]
-    pub const NORMAL: Self = Self(0);
+    NORMAL = 0,
     #[doc = "invert the interrupt"]
-    pub const INVERT: Self = Self(0x01);
+    INVERT = 0x01,
     #[doc = "drive interrupt low"]
-    pub const LOW: Self = Self(0x02);
+    LOW = 0x02,
     #[doc = "drive interrupt high"]
-    pub const HIGH: Self = Self(0x03);
+    HIGH = 0x03,
+}
+impl Irqover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Irqover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Irqover {
+    #[inline(always)]
+    fn from(val: u8) -> Irqover {
+        Irqover::from_bits(val)
+    }
+}
+impl From<Irqover> for u8 {
+    #[inline(always)]
+    fn from(val: Irqover) -> u8 {
+        Irqover::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Oeover(pub u8);
-impl Oeover {
+pub enum Oeover {
     #[doc = "drive output enable from peripheral signal selected by funcsel"]
-    pub const NORMAL: Self = Self(0);
+    NORMAL = 0,
     #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"]
-    pub const INVERT: Self = Self(0x01);
+    INVERT = 0x01,
     #[doc = "disable output"]
-    pub const DISABLE: Self = Self(0x02);
+    DISABLE = 0x02,
     #[doc = "enable output"]
-    pub const ENABLE: Self = Self(0x03);
+    ENABLE = 0x03,
+}
+impl Oeover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Oeover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Oeover {
+    #[inline(always)]
+    fn from(val: u8) -> Oeover {
+        Oeover::from_bits(val)
+    }
+}
+impl From<Oeover> for u8 {
+    #[inline(always)]
+    fn from(val: Oeover) -> u8 {
+        Oeover::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Outover(pub u8);
-impl Outover {
+pub enum Outover {
     #[doc = "drive output from peripheral signal selected by funcsel"]
-    pub const NORMAL: Self = Self(0);
+    NORMAL = 0,
     #[doc = "drive output from inverse of peripheral signal selected by funcsel"]
-    pub const INVERT: Self = Self(0x01);
+    INVERT = 0x01,
     #[doc = "drive output low"]
-    pub const LOW: Self = Self(0x02);
+    LOW = 0x02,
     #[doc = "drive output high"]
-    pub const HIGH: Self = Self(0x03);
+    HIGH = 0x03,
+}
+impl Outover {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Outover {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Outover {
+    #[inline(always)]
+    fn from(val: u8) -> Outover {
+        Outover::from_bits(val)
+    }
+}
+impl From<Outover> for u8 {
+    #[inline(always)]
+    fn from(val: Outover) -> u8 {
+        Outover::to_bits(val)
+    }
 }
diff --git a/src/pads/regs.rs b/src/pads/regs.rs
index 5de50e0d..79ce2eb8 100644
--- a/src/pads/regs.rs
+++ b/src/pads/regs.rs
@@ -51,12 +51,12 @@ impl GpioCtrl {
     #[inline(always)]
     pub const fn drive(&self) -> super::vals::Drive {
         let val = (self.0 >> 4usize) & 0x03;
-        super::vals::Drive(val as u8)
+        super::vals::Drive::from_bits(val as u8)
     }
     #[doc = "Drive strength."]
     #[inline(always)]
     pub fn set_drive(&mut self, val: super::vals::Drive) {
-        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.0 as u32) & 0x03) << 4usize);
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
     }
     #[doc = "Input enable"]
     #[inline(always)]
@@ -95,11 +95,11 @@ impl VoltageSelect {
     #[inline(always)]
     pub const fn voltage_select(&self) -> super::vals::VoltageSelect {
         let val = (self.0 >> 0usize) & 0x01;
-        super::vals::VoltageSelect(val as u8)
+        super::vals::VoltageSelect::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_voltage_select(&mut self, val: super::vals::VoltageSelect) {
-        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
+        self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize);
     }
 }
 impl Default for VoltageSelect {
diff --git a/src/pads/vals.rs b/src/pads/vals.rs
index 98df731d..f9e7d6c3 100644
--- a/src/pads/vals.rs
+++ b/src/pads/vals.rs
@@ -1,18 +1,60 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Drive(pub u8);
+pub enum Drive {
+    _2MA = 0,
+    _4MA = 0x01,
+    _8MA = 0x02,
+    _12MA = 0x03,
+}
 impl Drive {
-    pub const _2MA: Self = Self(0);
-    pub const _4MA: Self = Self(0x01);
-    pub const _8MA: Self = Self(0x02);
-    pub const _12MA: Self = Self(0x03);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Drive {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Drive {
+    #[inline(always)]
+    fn from(val: u8) -> Drive {
+        Drive::from_bits(val)
+    }
 }
-#[repr(transparent)]
+impl From<Drive> for u8 {
+    #[inline(always)]
+    fn from(val: Drive) -> u8 {
+        Drive::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct VoltageSelect(pub u8);
-impl VoltageSelect {
+pub enum VoltageSelect {
     #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"]
-    pub const _3V3: Self = Self(0);
+    _3V3 = 0,
     #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"]
-    pub const _1V8: Self = Self(0x01);
+    _1V8 = 0x01,
+}
+impl VoltageSelect {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> VoltageSelect {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for VoltageSelect {
+    #[inline(always)]
+    fn from(val: u8) -> VoltageSelect {
+        VoltageSelect::from_bits(val)
+    }
+}
+impl From<VoltageSelect> for u8 {
+    #[inline(always)]
+    fn from(val: VoltageSelect) -> u8 {
+        VoltageSelect::to_bits(val)
+    }
 }
diff --git a/src/pio.rs b/src/pio.rs
index 7dc44336..29068f8e 100644
--- a/src/pio.rs
+++ b/src/pio.rs
@@ -13,17 +13,17 @@ impl Irq {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "Interrupt Enable for irq1"]
+    #[doc = "Interrupt Enable for irq0"]
     #[inline(always)]
     pub const fn inte(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
-    #[doc = "Interrupt Force for irq1"]
+    #[doc = "Interrupt Force for irq0"]
     #[inline(always)]
     pub const fn intf(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
-    #[doc = "Interrupt status after masking & forcing for irq1"]
+    #[doc = "Interrupt status after masking & forcing for irq0"]
     #[inline(always)]
     pub const fn ints(self) -> crate::common::Reg<regs::Intr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
@@ -147,27 +147,27 @@ impl StateMachine {
     pub const fn as_ptr(&self) -> *mut () {
         self.ptr as _
     }
-    #[doc = "Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
+    #[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"]
     #[inline(always)]
     pub const fn clkdiv(self) -> crate::common::Reg<regs::SmClkdiv, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(0usize) as _) }
     }
-    #[doc = "Execution/behavioural settings for state machine 1"]
+    #[doc = "Execution/behavioural settings for state machine 0"]
     #[inline(always)]
     pub const fn execctrl(self) -> crate::common::Reg<regs::SmExecctrl, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(4usize) as _) }
     }
-    #[doc = "Control behaviour of the input/output shift registers for state machine 1"]
+    #[doc = "Control behaviour of the input/output shift registers for state machine 0"]
     #[inline(always)]
     pub const fn shiftctrl(self) -> crate::common::Reg<regs::SmShiftctrl, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(8usize) as _) }
     }
-    #[doc = "Current instruction address of state machine 1"]
+    #[doc = "Current instruction address of state machine 0"]
     #[inline(always)]
     pub const fn addr(self) -> crate::common::Reg<regs::SmAddr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(12usize) as _) }
     }
-    #[doc = "Read to see the instruction currently addressed by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
+    #[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
     #[inline(always)]
     pub const fn instr(self) -> crate::common::Reg<regs::SmInstr, crate::common::RW> {
         unsafe { crate::common::Reg::from_ptr(self.ptr.add(16usize) as _) }
diff --git a/src/pio/regs.rs b/src/pio/regs.rs
index e4f9833c..ca04b855 100644
--- a/src/pio/regs.rs
+++ b/src/pio/regs.rs
@@ -284,7 +284,7 @@ impl Default for Fstat {
         Fstat(0)
     }
 }
-#[doc = "Write-only access to instruction memory location 2"]
+#[doc = "Write-only access to instruction memory location 14"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct InstrMem(pub u32);
@@ -305,7 +305,7 @@ impl Default for InstrMem {
         InstrMem(0)
     }
 }
-#[doc = "Interrupt Force for irq0"]
+#[doc = "Raw Interrupts"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Intr(pub u32);
@@ -522,7 +522,7 @@ impl Default for SmClkdiv {
         SmClkdiv(0)
     }
 }
-#[doc = "Execution/behavioural settings for state machine 0"]
+#[doc = "Execution/behavioural settings for state machine 2"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct SmExecctrl(pub u32);
@@ -542,12 +542,12 @@ impl SmExecctrl {
     #[inline(always)]
     pub const fn status_sel(&self) -> super::vals::SmExecctrlStatusSel {
         let val = (self.0 >> 4usize) & 0x01;
-        super::vals::SmExecctrlStatusSel(val as u8)
+        super::vals::SmExecctrlStatusSel::from_bits(val as u8)
     }
     #[doc = "Comparison used for the MOV x, STATUS instruction."]
     #[inline(always)]
     pub fn set_status_sel(&mut self, val: super::vals::SmExecctrlStatusSel) {
-        self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
+        self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
     }
     #[doc = "After reaching wrap_top, execution is wrapped to this address."]
     #[inline(always)]
@@ -655,7 +655,7 @@ impl Default for SmExecctrl {
         SmExecctrl(0)
     }
 }
-#[doc = "Read to see the instruction currently addressed by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
+#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct SmInstr(pub u32);
diff --git a/src/pio/vals.rs b/src/pio/vals.rs
index ebf91e48..0a80df0a 100644
--- a/src/pio/vals.rs
+++ b/src/pio/vals.rs
@@ -1,9 +1,30 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct SmExecctrlStatusSel(pub u8);
-impl SmExecctrlStatusSel {
+pub enum SmExecctrlStatusSel {
     #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"]
-    pub const TXLEVEL: Self = Self(0);
+    TXLEVEL = 0,
     #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"]
-    pub const RXLEVEL: Self = Self(0x01);
+    RXLEVEL = 0x01,
+}
+impl SmExecctrlStatusSel {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SmExecctrlStatusSel {
+        unsafe { core::mem::transmute(val & 0x01) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SmExecctrlStatusSel {
+    #[inline(always)]
+    fn from(val: u8) -> SmExecctrlStatusSel {
+        SmExecctrlStatusSel::from_bits(val)
+    }
+}
+impl From<SmExecctrlStatusSel> for u8 {
+    #[inline(always)]
+    fn from(val: SmExecctrlStatusSel) -> u8 {
+        SmExecctrlStatusSel::to_bits(val)
+    }
 }
diff --git a/src/pwm/regs.rs b/src/pwm/regs.rs
index c995fdb3..917427d2 100644
--- a/src/pwm/regs.rs
+++ b/src/pwm/regs.rs
@@ -80,11 +80,11 @@ impl ChCsr {
     #[inline(always)]
     pub const fn divmode(&self) -> super::vals::Divmode {
         let val = (self.0 >> 4usize) & 0x03;
-        super::vals::Divmode(val as u8)
+        super::vals::Divmode::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_divmode(&mut self, val: super::vals::Divmode) {
-        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.0 as u32) & 0x03) << 4usize);
+        self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize);
     }
     #[doc = "Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."]
     #[inline(always)]
diff --git a/src/pwm/vals.rs b/src/pwm/vals.rs
index 0e2b2d7b..d71aae43 100644
--- a/src/pwm/vals.rs
+++ b/src/pwm/vals.rs
@@ -1,13 +1,34 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Divmode(pub u8);
-impl Divmode {
+pub enum Divmode {
     #[doc = "Free-running counting at rate dictated by fractional divider"]
-    pub const DIV: Self = Self(0);
+    DIV = 0,
     #[doc = "Fractional divider operation is gated by the PWM B pin."]
-    pub const LEVEL: Self = Self(0x01);
+    LEVEL = 0x01,
     #[doc = "Counter advances with each rising edge of the PWM B pin."]
-    pub const RISE: Self = Self(0x02);
+    RISE = 0x02,
     #[doc = "Counter advances with each falling edge of the PWM B pin."]
-    pub const FALL: Self = Self(0x03);
+    FALL = 0x03,
+}
+impl Divmode {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Divmode {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Divmode {
+    #[inline(always)]
+    fn from(val: u8) -> Divmode {
+        Divmode::from_bits(val)
+    }
+}
+impl From<Divmode> for u8 {
+    #[inline(always)]
+    fn from(val: Divmode) -> u8 {
+        Divmode::to_bits(val)
+    }
 }
diff --git a/src/rosc/regs.rs b/src/rosc/regs.rs
index 03b04b73..5d61fd98 100644
--- a/src/rosc/regs.rs
+++ b/src/rosc/regs.rs
@@ -28,23 +28,23 @@ impl Ctrl {
     #[inline(always)]
     pub const fn freq_range(&self) -> super::vals::FreqRange {
         let val = (self.0 >> 0usize) & 0x0fff;
-        super::vals::FreqRange(val as u16)
+        super::vals::FreqRange::from_bits(val as u16)
     }
     #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 HIGH uses stages 0 to 3 TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
     #[inline(always)]
     pub fn set_freq_range(&mut self, val: super::vals::FreqRange) {
-        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.0 as u32) & 0x0fff) << 0usize);
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.to_bits() as u32) & 0x0fff) << 0usize);
     }
     #[doc = "On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
     #[inline(always)]
     pub const fn enable(&self) -> super::vals::Enable {
         let val = (self.0 >> 12usize) & 0x0fff;
-        super::vals::Enable(val as u16)
+        super::vals::Enable::from_bits(val as u16)
     }
     #[doc = "On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
     #[inline(always)]
     pub fn set_enable(&mut self, val: super::vals::Enable) {
-        self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.0 as u32) & 0x0fff) << 12usize);
+        self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.to_bits() as u32) & 0x0fff) << 12usize);
     }
 }
 impl Default for Ctrl {
@@ -62,12 +62,12 @@ impl Div {
     #[inline(always)]
     pub const fn div(&self) -> super::vals::Div {
         let val = (self.0 >> 0usize) & 0x0fff;
-        super::vals::Div(val as u16)
+        super::vals::Div::from_bits(val as u16)
     }
     #[doc = "set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16"]
     #[inline(always)]
     pub fn set_div(&mut self, val: super::vals::Div) {
-        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.0 as u32) & 0x0fff) << 0usize);
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.to_bits() as u32) & 0x0fff) << 0usize);
     }
 }
 impl Default for Div {
@@ -129,12 +129,12 @@ impl Freqa {
     #[inline(always)]
     pub const fn passwd(&self) -> super::vals::Passwd {
         let val = (self.0 >> 16usize) & 0xffff;
-        super::vals::Passwd(val as u16)
+        super::vals::Passwd::from_bits(val as u16)
     }
     #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
     #[inline(always)]
     pub fn set_passwd(&mut self, val: super::vals::Passwd) {
-        self.0 = (self.0 & !(0xffff << 16usize)) | (((val.0 as u32) & 0xffff) << 16usize);
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val.to_bits() as u32) & 0xffff) << 16usize);
     }
 }
 impl Default for Freqa {
@@ -196,12 +196,12 @@ impl Freqb {
     #[inline(always)]
     pub const fn passwd(&self) -> super::vals::Passwd {
         let val = (self.0 >> 16usize) & 0xffff;
-        super::vals::Passwd(val as u16)
+        super::vals::Passwd::from_bits(val as u16)
     }
     #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
     #[inline(always)]
     pub fn set_passwd(&mut self, val: super::vals::Passwd) {
-        self.0 = (self.0 & !(0xffff << 16usize)) | (((val.0 as u32) & 0xffff) << 16usize);
+        self.0 = (self.0 & !(0xffff << 16usize)) | (((val.to_bits() as u32) & 0xffff) << 16usize);
     }
 }
 impl Default for Freqb {
diff --git a/src/rosc/vals.rs b/src/rosc/vals.rs
index 24901ab5..3ef92549 100644
--- a/src/rosc/vals.rs
+++ b/src/rosc/vals.rs
@@ -4,6 +4,26 @@ pub struct Div(pub u16);
 impl Div {
     pub const PASS: Self = Self(0x0aa0);
 }
+impl Div {
+    pub const fn from_bits(val: u16) -> Div {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Div {
+    #[inline(always)]
+    fn from(val: u16) -> Div {
+        Div::from_bits(val)
+    }
+}
+impl From<Div> for u16 {
+    #[inline(always)]
+    fn from(val: Div) -> u16 {
+        Div::to_bits(val)
+    }
+}
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
 pub struct Enable(pub u16);
@@ -11,6 +31,26 @@ impl Enable {
     pub const DISABLE: Self = Self(0x0d1e);
     pub const ENABLE: Self = Self(0x0fab);
 }
+impl Enable {
+    pub const fn from_bits(val: u16) -> Enable {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Enable {
+    #[inline(always)]
+    fn from(val: u16) -> Enable {
+        Enable::from_bits(val)
+    }
+}
+impl From<Enable> for u16 {
+    #[inline(always)]
+    fn from(val: Enable) -> u16 {
+        Enable::to_bits(val)
+    }
+}
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
 pub struct FreqRange(pub u16);
@@ -20,9 +60,49 @@ impl FreqRange {
     pub const TOOHIGH: Self = Self(0x0fa6);
     pub const HIGH: Self = Self(0x0fa7);
 }
+impl FreqRange {
+    pub const fn from_bits(val: u16) -> FreqRange {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for FreqRange {
+    #[inline(always)]
+    fn from(val: u16) -> FreqRange {
+        FreqRange::from_bits(val)
+    }
+}
+impl From<FreqRange> for u16 {
+    #[inline(always)]
+    fn from(val: FreqRange) -> u16 {
+        FreqRange::to_bits(val)
+    }
+}
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
 pub struct Passwd(pub u16);
 impl Passwd {
     pub const PASS: Self = Self(0x9696);
 }
+impl Passwd {
+    pub const fn from_bits(val: u16) -> Passwd {
+        Self(val & 0xffff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Passwd {
+    #[inline(always)]
+    fn from(val: u16) -> Passwd {
+        Passwd::from_bits(val)
+    }
+}
+impl From<Passwd> for u16 {
+    #[inline(always)]
+    fn from(val: Passwd) -> u16 {
+        Passwd::to_bits(val)
+    }
+}
diff --git a/src/rtc/regs.rs b/src/rtc/regs.rs
index bbf88553..fb3c9295 100644
--- a/src/rtc/regs.rs
+++ b/src/rtc/regs.rs
@@ -75,7 +75,7 @@ impl Default for Ctrl {
         Ctrl(0)
     }
 }
-#[doc = "Interrupt status after masking & forcing"]
+#[doc = "Interrupt Force"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/timer/regs.rs b/src/timer/regs.rs
index c14c49d9..6bbdc0b3 100644
--- a/src/timer/regs.rs
+++ b/src/timer/regs.rs
@@ -53,7 +53,7 @@ impl Default for Dbgpause {
         Dbgpause(0)
     }
 }
-#[doc = "Interrupt Force"]
+#[doc = "Interrupt Enable"]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct Int(pub u32);
diff --git a/src/usb/regs.rs b/src/usb/regs.rs
index 575e47e6..a29fdddf 100644
--- a/src/usb/regs.rs
+++ b/src/usb/regs.rs
@@ -32,7 +32,7 @@ impl Default for AddrEndp {
         AddrEndp(0)
     }
 }
-#[doc = "Interrupt endpoint 8. Only valid for HOST mode."]
+#[doc = "Interrupt endpoint 10. Only valid for HOST mode."]
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq)]
 pub struct AddrEndpX(pub u32);
diff --git a/src/usb_dpram/regs.rs b/src/usb_dpram/regs.rs
index c02aabd8..165d477e 100644
--- a/src/usb_dpram/regs.rs
+++ b/src/usb_dpram/regs.rs
@@ -106,7 +106,7 @@ impl EpBufferControl {
         &self,
     ) -> super::vals::EpBufferControlDoubleBufferIsoOffset {
         let val = (self.0 >> 27usize) & 0x03;
-        super::vals::EpBufferControlDoubleBufferIsoOffset(val as u8)
+        super::vals::EpBufferControlDoubleBufferIsoOffset::from_bits(val as u8)
     }
     #[doc = "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."]
     #[inline(always)]
@@ -114,7 +114,7 @@ impl EpBufferControl {
         &mut self,
         val: super::vals::EpBufferControlDoubleBufferIsoOffset,
     ) {
-        self.0 = (self.0 & !(0x03 << 27usize)) | (((val.0 as u32) & 0x03) << 27usize);
+        self.0 = (self.0 & !(0x03 << 27usize)) | (((val.to_bits() as u32) & 0x03) << 27usize);
     }
 }
 impl Default for EpBufferControl {
@@ -163,11 +163,11 @@ impl EpControl {
     #[inline(always)]
     pub const fn endpoint_type(&self) -> super::vals::EpControlEndpointType {
         let val = (self.0 >> 26usize) & 0x03;
-        super::vals::EpControlEndpointType(val as u8)
+        super::vals::EpControlEndpointType::from_bits(val as u8)
     }
     #[inline(always)]
     pub fn set_endpoint_type(&mut self, val: super::vals::EpControlEndpointType) {
-        self.0 = (self.0 & !(0x03 << 26usize)) | (((val.0 as u32) & 0x03) << 26usize);
+        self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize);
     }
     #[doc = "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
     #[inline(always)]
diff --git a/src/usb_dpram/vals.rs b/src/usb_dpram/vals.rs
index 5a7d2bf8..d0e39228 100644
--- a/src/usb_dpram/vals.rs
+++ b/src/usb_dpram/vals.rs
@@ -1,18 +1,60 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct EpBufferControlDoubleBufferIsoOffset(pub u8);
+pub enum EpBufferControlDoubleBufferIsoOffset {
+    _128 = 0,
+    _256 = 0x01,
+    _512 = 0x02,
+    _1024 = 0x03,
+}
 impl EpBufferControlDoubleBufferIsoOffset {
-    pub const _128: Self = Self(0);
-    pub const _256: Self = Self(0x01);
-    pub const _512: Self = Self(0x02);
-    pub const _1024: Self = Self(0x03);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> EpBufferControlDoubleBufferIsoOffset {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for EpBufferControlDoubleBufferIsoOffset {
+    #[inline(always)]
+    fn from(val: u8) -> EpBufferControlDoubleBufferIsoOffset {
+        EpBufferControlDoubleBufferIsoOffset::from_bits(val)
+    }
+}
+impl From<EpBufferControlDoubleBufferIsoOffset> for u8 {
+    #[inline(always)]
+    fn from(val: EpBufferControlDoubleBufferIsoOffset) -> u8 {
+        EpBufferControlDoubleBufferIsoOffset::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct EpControlEndpointType(pub u8);
+pub enum EpControlEndpointType {
+    CONTROL = 0,
+    ISOCHRONOUS = 0x01,
+    BULK = 0x02,
+    INTERRUPT = 0x03,
+}
 impl EpControlEndpointType {
-    pub const CONTROL: Self = Self(0);
-    pub const ISOCHRONOUS: Self = Self(0x01);
-    pub const BULK: Self = Self(0x02);
-    pub const INTERRUPT: Self = Self(0x03);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> EpControlEndpointType {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for EpControlEndpointType {
+    #[inline(always)]
+    fn from(val: u8) -> EpControlEndpointType {
+        EpControlEndpointType::from_bits(val)
+    }
+}
+impl From<EpControlEndpointType> for u8 {
+    #[inline(always)]
+    fn from(val: EpControlEndpointType) -> u8 {
+        EpControlEndpointType::to_bits(val)
+    }
 }
diff --git a/src/xip_ssi/regs.rs b/src/xip_ssi/regs.rs
index 4f2b4ee6..a2b32a64 100644
--- a/src/xip_ssi/regs.rs
+++ b/src/xip_ssi/regs.rs
@@ -74,12 +74,12 @@ impl Ctrlr0 {
     #[inline(always)]
     pub const fn tmod(&self) -> super::vals::Tmod {
         let val = (self.0 >> 8usize) & 0x03;
-        super::vals::Tmod(val as u8)
+        super::vals::Tmod::from_bits(val as u8)
     }
     #[doc = "Transfer mode"]
     #[inline(always)]
     pub fn set_tmod(&mut self, val: super::vals::Tmod) {
-        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
     }
     #[doc = "Slave output enable"]
     #[inline(always)]
@@ -129,12 +129,12 @@ impl Ctrlr0 {
     #[inline(always)]
     pub const fn spi_frf(&self) -> super::vals::SpiFrf {
         let val = (self.0 >> 21usize) & 0x03;
-        super::vals::SpiFrf(val as u8)
+        super::vals::SpiFrf::from_bits(val as u8)
     }
     #[doc = "SPI frame format"]
     #[inline(always)]
     pub fn set_spi_frf(&mut self, val: super::vals::SpiFrf) {
-        self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
+        self.0 = (self.0 & !(0x03 << 21usize)) | (((val.to_bits() as u32) & 0x03) << 21usize);
     }
     #[doc = "Slave select toggle enable"]
     #[inline(always)]
@@ -729,12 +729,12 @@ impl SpiCtrlr0 {
     #[inline(always)]
     pub const fn trans_type(&self) -> super::vals::TransType {
         let val = (self.0 >> 0usize) & 0x03;
-        super::vals::TransType(val as u8)
+        super::vals::TransType::from_bits(val as u8)
     }
     #[doc = "Address and instruction transfer format"]
     #[inline(always)]
     pub fn set_trans_type(&mut self, val: super::vals::TransType) {
-        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
     }
     #[doc = "Address length (0b-60b in 4b increments)"]
     #[inline(always)]
@@ -751,12 +751,12 @@ impl SpiCtrlr0 {
     #[inline(always)]
     pub const fn inst_l(&self) -> super::vals::InstL {
         let val = (self.0 >> 8usize) & 0x03;
-        super::vals::InstL(val as u8)
+        super::vals::InstL::from_bits(val as u8)
     }
     #[doc = "Instruction length (0/4/8/16b)"]
     #[inline(always)]
     pub fn set_inst_l(&mut self, val: super::vals::InstL) {
-        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
+        self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
     }
     #[doc = "Wait cycles between control frame transmit and data reception (in SCLK cycles)"]
     #[inline(always)]
diff --git a/src/xip_ssi/vals.rs b/src/xip_ssi/vals.rs
index 90daa152..27d0365b 100644
--- a/src/xip_ssi/vals.rs
+++ b/src/xip_ssi/vals.rs
@@ -1,48 +1,134 @@
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct InstL(pub u8);
-impl InstL {
+pub enum InstL {
     #[doc = "No instruction"]
-    pub const NONE: Self = Self(0);
+    NONE = 0,
     #[doc = "4-bit instruction"]
-    pub const _4B: Self = Self(0x01);
+    _4B = 0x01,
     #[doc = "8-bit instruction"]
-    pub const _8B: Self = Self(0x02);
+    _8B = 0x02,
     #[doc = "16-bit instruction"]
-    pub const _16B: Self = Self(0x03);
+    _16B = 0x03,
+}
+impl InstL {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> InstL {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for InstL {
+    #[inline(always)]
+    fn from(val: u8) -> InstL {
+        InstL::from_bits(val)
+    }
+}
+impl From<InstL> for u8 {
+    #[inline(always)]
+    fn from(val: InstL) -> u8 {
+        InstL::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct SpiFrf(pub u8);
-impl SpiFrf {
+pub enum SpiFrf {
     #[doc = "Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex"]
-    pub const STD: Self = Self(0);
+    STD = 0,
     #[doc = "Dual-SPI frame format; two bits per SCK, half-duplex"]
-    pub const DUAL: Self = Self(0x01);
+    DUAL = 0x01,
     #[doc = "Quad-SPI frame format; four bits per SCK, half-duplex"]
-    pub const QUAD: Self = Self(0x02);
+    QUAD = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl SpiFrf {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> SpiFrf {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for SpiFrf {
+    #[inline(always)]
+    fn from(val: u8) -> SpiFrf {
+        SpiFrf::from_bits(val)
+    }
+}
+impl From<SpiFrf> for u8 {
+    #[inline(always)]
+    fn from(val: SpiFrf) -> u8 {
+        SpiFrf::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct Tmod(pub u8);
-impl Tmod {
+pub enum Tmod {
     #[doc = "Both transmit and receive"]
-    pub const TX_AND_RX: Self = Self(0);
+    TX_AND_RX = 0,
     #[doc = "Transmit only (not for FRF == 0, standard SPI mode)"]
-    pub const TX_ONLY: Self = Self(0x01);
+    TX_ONLY = 0x01,
     #[doc = "Receive only (not for FRF == 0, standard SPI mode)"]
-    pub const RX_ONLY: Self = Self(0x02);
+    RX_ONLY = 0x02,
     #[doc = "EEPROM read mode (TX then RX; RX starts after control data TX'd)"]
-    pub const EEPROM_READ: Self = Self(0x03);
+    EEPROM_READ = 0x03,
+}
+impl Tmod {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> Tmod {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for Tmod {
+    #[inline(always)]
+    fn from(val: u8) -> Tmod {
+        Tmod::from_bits(val)
+    }
+}
+impl From<Tmod> for u8 {
+    #[inline(always)]
+    fn from(val: Tmod) -> u8 {
+        Tmod::to_bits(val)
+    }
 }
-#[repr(transparent)]
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct TransType(pub u8);
-impl TransType {
+pub enum TransType {
     #[doc = "Command and address both in standard SPI frame format"]
-    pub const _1C1A: Self = Self(0);
+    _1C1A = 0,
     #[doc = "Command in standard SPI format, address in format specified by FRF"]
-    pub const _1C2A: Self = Self(0x01);
+    _1C2A = 0x01,
     #[doc = "Command and address both in format specified by FRF (e.g. Dual-SPI)"]
-    pub const _2C2A: Self = Self(0x02);
+    _2C2A = 0x02,
+    _RESERVED_3 = 0x03,
+}
+impl TransType {
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> TransType {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for TransType {
+    #[inline(always)]
+    fn from(val: u8) -> TransType {
+        TransType::from_bits(val)
+    }
+}
+impl From<TransType> for u8 {
+    #[inline(always)]
+    fn from(val: TransType) -> u8 {
+        TransType::to_bits(val)
+    }
 }
diff --git a/src/xosc/regs.rs b/src/xosc/regs.rs
index f99927b8..56eba56c 100644
--- a/src/xosc/regs.rs
+++ b/src/xosc/regs.rs
@@ -28,23 +28,23 @@ impl Ctrl {
     #[inline(always)]
     pub const fn freq_range(&self) -> super::vals::CtrlFreqRange {
         let val = (self.0 >> 0usize) & 0x0fff;
-        super::vals::CtrlFreqRange(val as u16)
+        super::vals::CtrlFreqRange::from_bits(val as u16)
     }
     #[doc = "Frequency range. This resets to 0xAA0 and cannot be changed."]
     #[inline(always)]
     pub fn set_freq_range(&mut self, val: super::vals::CtrlFreqRange) {
-        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.0 as u32) & 0x0fff) << 0usize);
+        self.0 = (self.0 & !(0x0fff << 0usize)) | (((val.to_bits() as u32) & 0x0fff) << 0usize);
     }
     #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
     #[inline(always)]
     pub const fn enable(&self) -> super::vals::Enable {
         let val = (self.0 >> 12usize) & 0x0fff;
-        super::vals::Enable(val as u16)
+        super::vals::Enable::from_bits(val as u16)
     }
     #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
     #[inline(always)]
     pub fn set_enable(&mut self, val: super::vals::Enable) {
-        self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.0 as u32) & 0x0fff) << 12usize);
+        self.0 = (self.0 & !(0x0fff << 12usize)) | (((val.to_bits() as u32) & 0x0fff) << 12usize);
     }
 }
 impl Default for Ctrl {
@@ -96,12 +96,12 @@ impl Status {
     #[inline(always)]
     pub const fn freq_range(&self) -> super::vals::StatusFreqRange {
         let val = (self.0 >> 0usize) & 0x03;
-        super::vals::StatusFreqRange(val as u8)
+        super::vals::StatusFreqRange::from_bits(val as u8)
     }
     #[doc = "The current frequency range setting, always reads 0"]
     #[inline(always)]
     pub fn set_freq_range(&mut self, val: super::vals::StatusFreqRange) {
-        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
+        self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
     }
     #[doc = "Oscillator is enabled but not necessarily running and stable, resets to 0"]
     #[inline(always)]
diff --git a/src/xosc/vals.rs b/src/xosc/vals.rs
index 93fe13b6..e8400c32 100644
--- a/src/xosc/vals.rs
+++ b/src/xosc/vals.rs
@@ -7,6 +7,26 @@ impl CtrlFreqRange {
     pub const RESERVED_2: Self = Self(0x0aa2);
     pub const RESERVED_3: Self = Self(0x0aa3);
 }
+impl CtrlFreqRange {
+    pub const fn from_bits(val: u16) -> CtrlFreqRange {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for CtrlFreqRange {
+    #[inline(always)]
+    fn from(val: u16) -> CtrlFreqRange {
+        CtrlFreqRange::from_bits(val)
+    }
+}
+impl From<CtrlFreqRange> for u16 {
+    #[inline(always)]
+    fn from(val: CtrlFreqRange) -> u16 {
+        CtrlFreqRange::to_bits(val)
+    }
+}
 #[repr(transparent)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
 pub struct Enable(pub u16);
@@ -14,12 +34,53 @@ impl Enable {
     pub const DISABLE: Self = Self(0x0d1e);
     pub const ENABLE: Self = Self(0x0fab);
 }
-#[repr(transparent)]
+impl Enable {
+    pub const fn from_bits(val: u16) -> Enable {
+        Self(val & 0x0fff)
+    }
+    pub const fn to_bits(self) -> u16 {
+        self.0
+    }
+}
+impl From<u16> for Enable {
+    #[inline(always)]
+    fn from(val: u16) -> Enable {
+        Enable::from_bits(val)
+    }
+}
+impl From<Enable> for u16 {
+    #[inline(always)]
+    fn from(val: Enable) -> u16 {
+        Enable::to_bits(val)
+    }
+}
+#[repr(u8)]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-pub struct StatusFreqRange(pub u8);
+pub enum StatusFreqRange {
+    _1_15MHZ = 0,
+    RESERVED_1 = 0x01,
+    RESERVED_2 = 0x02,
+    RESERVED_3 = 0x03,
+}
 impl StatusFreqRange {
-    pub const _1_15MHZ: Self = Self(0);
-    pub const RESERVED_1: Self = Self(0x01);
-    pub const RESERVED_2: Self = Self(0x02);
-    pub const RESERVED_3: Self = Self(0x03);
+    #[inline(always)]
+    pub const fn from_bits(val: u8) -> StatusFreqRange {
+        unsafe { core::mem::transmute(val & 0x03) }
+    }
+    #[inline(always)]
+    pub const fn to_bits(self) -> u8 {
+        unsafe { core::mem::transmute(self) }
+    }
+}
+impl From<u8> for StatusFreqRange {
+    #[inline(always)]
+    fn from(val: u8) -> StatusFreqRange {
+        StatusFreqRange::from_bits(val)
+    }
+}
+impl From<StatusFreqRange> for u8 {
+    #[inline(always)]
+    fn from(val: StatusFreqRange) -> u8 {
+        StatusFreqRange::to_bits(val)
+    }
 }