Add dependency scanning as a testcase.

tests/project/designA/file_A1.vhdl

@@ -1,14 +1,17 @@
+library IEEE;
+use     IEEE.std_logic_1164.all;
 
-library libraryCommon;
-use     libraryCommon.P1.all;
+library libCommon;
+use     libCommon.P1.all;
 
 entity A1 is
-
+	port (
+		signal Clock : in std_logic
+	);
 end entity;
 
 architecture rtl of A1 is
 
 begin
 
 end architecture;
-

tests/project/designA/file_A2.vhdl

@@ -1,16 +1,20 @@
+library IEEE;
+use     IEEE.std_logic_1164.all;
 
-library libraryCommon;
-use     libraryCommon.P2.all;
+library libCommon;
+use     libCommon.P2.all;
 
 entity A2 is
-
+	port (
+		signal Clock : in std_logic
+	);
 end entity;
 
 architecture rtl of A2 is
 
 begin
   a : entity work.A1
-    port (
-
+    port map (
+			Clock => Clock
     );
 end architecture;

tests/unit/DependencyScan.py

@@ -11,7 +11,7 @@
 #                                                                                                                      #
 # License:                                                                                                             #
 # ==================================================================================================================== #
-# Copyright 2017-2022 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
 #                                                                                                                      #
 # Licensed under the Apache License, Version 2.0 (the "License");                                                      #
 # you may not use this file except in compliance with the License.                                                     #
@@ -29,11 +29,22 @@
 # ==================================================================================================================== #
 #
 """Instantiation tests for the project model."""
-from unittest import TestCase
+from pathlib     import Path
+from unittest    import TestCase
 
+from pyGHDL.dom import DOMException
+from pyGHDL.libghdl import LibGHDLException
+from pytest      import mark
 from pyVHDLModel import VHDLVersion
 
-from pyEDAA.ProjectModel import Design, VHDLLibrary, Project
+from pyEDAA.ProjectModel      import Design, VHDLLibrary, Project, VHDLSourceFile, VerilogSourceFile, FileSet
+
+try:
+	from pyGHDL.dom.NonStandard import Design as DOMDesign, Document
+
+	withGHDL = True
+except ImportError:
+	withGHDL = False
 
 
 if __name__ == "__main__": # pragma: no cover
@@ -42,64 +53,52 @@
 	exit(1)
 
 
-class Instantiate(TestCase):
+class VHDL(TestCase):
+	@mark.skipif(withGHDL is False, reason="No 'pyGHDL' package found.")
 	def test_VHDLLibrary(self):
-		library = VHDLLibrary("library")
-
-		self.assertIsNotNone(library)
-		self.assertEqual(library.Name, "library")
-		self.assertIsNone(library.Project)
-		self.assertIsNone(library.Design)
-		self.assertEqual(0, len(library._files))
-
-	def test_VHDLLibraryFromDesign(self):
-		design =  Design("design")
-		library = VHDLLibrary("library", design=design)
-
-		self.assertIsNone(library.Project)
-		self.assertIs(design, library.Design)
-
-	def test_VHDLLibraryFromProject(self):
-		project = Project("project")
-		library = VHDLLibrary("library", project=project)
-
-		self.assertIs(project, library.Project)
-		self.assertIs(project.DefaultDesign, library.Design)
-
-	def test_VHDLLibraryFromProjectAndDesign(self):
-		project = Project("project")
-		design =  Design("design", project=project)
-		library = VHDLLibrary("library", design=design)
-
-		self.assertIs(library.Project, project)
-		self.assertIs(library.Design, design)
-
-	def test_VHDLLibraryWithVersion(self):
-		library = VHDLLibrary("library", vhdlVersion=VHDLVersion.VHDL2019)
-
-		self.assertEqual(VHDLVersion.VHDL2019, library.VHDLVersion)
-
-	def test_VHDLLibrarySetProjectLater(self):
-		project = Project("project")
-		library = VHDLLibrary("library")
-
-		library.Project = project
-
-		self.assertIs(project, library.Project)
-
-	def test_VHDLLibrarySetVersionLater(self):
-		library = VHDLLibrary("library")
-
-		vhdlVersion = VHDLVersion.VHDL2019
-
-		library.VHDLVersion = vhdlVersion
-
-		self.assertEqual(vhdlVersion, library.VHDLVersion)
-
-	def test_VHDLLibraryGetVersionFromDesign(self):
-		vhdlVersion = VHDLVersion.VHDL2019
-
-		design = Design("design", vhdlVersion=vhdlVersion)
-		library = VHDLLibrary("library", design=design)
-
-		self.assertEqual(vhdlVersion, library.VHDLVersion)
+		project = Project("project", rootDirectory=Path("project"), vhdlVersion=VHDLVersion.VHDL2019)
+		designA = Design("designA", directory=Path("designA"), project=project)
+		fileSetA = FileSet("fileSetA", directory=Path("."), design=designA)
+		fileSetC = FileSet("fileSetC", directory=Path("../lib"), design=designA)
+		libraryA = VHDLLibrary("libA", design=designA)
+		libraryC = VHDLLibrary("libCommon", design=designA)
+
+		fileA1 = VHDLSourceFile(Path("file_A1.vhdl"), fileSet=fileSetA, vhdlLibrary=libraryA)
+		fileA2 = VHDLSourceFile(Path("file_A2.vhdl"), fileSet=fileSetA, vhdlLibrary=libraryA)
+		fileA3 = VerilogSourceFile(Path("file_A3.v"), fileSet=fileSetA)
+
+		fileP1 = VHDLSourceFile(Path("file_P1.vhdl"), fileSet=fileSetC, vhdlLibrary=libraryC)
+		fileP2 = VHDLSourceFile(Path("file_P2.vhdl"), fileSet=fileSetC, vhdlLibrary=libraryC)
+
+		print()
+		print(f"Loading design '{designA.Name}':")
+		design = DOMDesign(name=designA.Name)
+
+		print(f"  Loading default libraries (Std, Ieee, ...)")
+		design.LoadDefaultLibraries()
+
+		for libraryName, vhdlLibrary in designA.VHDLLibraries.items():
+			print(f"  Loading library '{libraryName}' ...")
+			lib = design.GetLibrary(libraryName)
+
+			for file in vhdlLibrary.Files:
+				print(f"    Parsing '{file.ResolvedPath}' ...")
+				try:
+					vhdlDocument = Document(file.ResolvedPath)
+				except DOMException as ex:
+					if isinstance(ex.__cause__, LibGHDLException):
+						print(ex.__cause__)
+						for message in ex.__cause__.InternalErrors:
+							print(f"  {message}")
+					else:
+						print(ex)
+
+				design.AddDocument(vhdlDocument, lib)
+
+		print(f"  Analyzing design ...")
+		design.Analyze()
+
+		print()
+		print(f"Toplevel: {design.TopLevel}")
+		hierarchy = design.TopLevel.HierarchyVertex.ConvertToTree()
+		# print(hierarchy.Render())