diff --git a/patches/gcc10.1/gcc-repair-TARGET_ADDX.patch b/patches/gcc10.1/gcc-repair-TARGET_ADDX.patch
deleted file mode 100644
index 47d88e6..0000000
--- a/patches/gcc10.1/gcc-repair-TARGET_ADDX.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
-index 5bf4b9f5..ffdc4cb2 100644
---- a/gcc/config/xtensa/predicates.md
-+++ b/gcc/config/xtensa/predicates.md
-@@ -29,6 +29,12 @@
- 		    || INTVAL (op) == 4
- 		    || INTVAL (op) == 8")))
- 
-+(define_predicate "addsubx_alt_operand"
-+  (and (match_code "const_int")
-+       (match_test "INTVAL (op) == 1
-+		    || INTVAL (op) == 2
-+		    || INTVAL (op) == 3")))
-+
- (define_predicate "arith_operand"
-   (ior (and (match_code "const_int")
- 	    (match_test "xtensa_simm8 (INTVAL (op))"))
-diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
-index b95b9901..7d7970f9 100644
---- a/gcc/config/xtensa/xtensa.md
-+++ b/gcc/config/xtensa/xtensa.md
-@@ -170,6 +170,20 @@
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"SI")
-    (set_attr "length"	"3")])
-+ 
-+(define_insn "*addx_alt"
-+  [(set (match_operand:SI 0 "register_operand" "=a")
-+	(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-+			    (match_operand:SI 3 "addsubx_alt_operand" "i"))
-+		 (match_operand:SI 2 "register_operand" "r")))]
-+  "TARGET_ADDX"
-+{
-+  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-+  return "addx%3\t%0, %1, %2";
-+}
-+  [(set_attr "type"	"arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"3")])
- 
- (define_insn "addsf3"
-   [(set (match_operand:SF 0 "register_operand" "=f")
-@@ -204,6 +218,20 @@
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"SI")
-    (set_attr "length"	"3")])
-+
-+(define_insn "*subx_alt"
-+  [(set (match_operand:SI 0 "register_operand" "=a")
-+	(minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-+			     (match_operand:SI 3 "addsubx_alt_operand" "i"))
-+		  (match_operand:SI 2 "register_operand" "r")))]
-+  "TARGET_ADDX"
-+{
-+  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-+  return "subx%3\t%0, %1, %2";
-+}
-+  [(set_attr "type"	"arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"3")])
- 
- (define_insn "subsf3"
-   [(set (match_operand:SF 0 "register_operand" "=f")
diff --git a/patches/gcc10.1/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch b/patches/gcc10.1/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch
deleted file mode 100644
index 7691ad9..0000000
--- a/patches/gcc10.1/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
-index 953f90a0..14be4081 100644
---- a/gcc/config/xtensa/xtensa.c
-+++ b/gcc/config/xtensa/xtensa.c
-@@ -1072,6 +1072,21 @@
- 
-       if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16)
- 	{
-+	  /* Try to emit MOVI.N + SLLI sequence, that is smaller than L32R + constant pool.  */
-+	  if (TARGET_DENSITY && mode == SImode && register_operand (dst, mode))
-+	    {
-+	      int srcval = INTVAL (src);
-+	      int shift;
-+	      if (! (srcval & 1))
-+		for (srcval >>= 1, shift = 1; ! (srcval & 1) && shift < 32; srcval >>= 1, shift++)
-+		  if (srcval >= -32 && srcval <= 95)
-+		    {
-+		      emit_move_insn (dst, GEN_INT (srcval));
-+		      emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift)));
-+		      return 1;
-+		    }
-+	    }
-+
- 	  src = force_const_mem (SImode, src);
- 	  operands[1] = src;
- 	}
-diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
-index 8e304a6f..dbb36b11 100644
---- a/gcc/config/xtensa/xtensa.md
-+++ b/gcc/config/xtensa/xtensa.md
-@@ -721,8 +721,22 @@
- 	(match_operand:DI 1 "general_operand" ""))]
-   ""
- {
--  if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
--    operands[1] = force_const_mem (DImode, operands[1]);
-+  if (CONSTANT_P (operands[1]))
-+    {
-+      /* Split in halves if 64-bit Const-to-Reg moves
-+         because of offering further optimization opportunities.  */
-+      if (register_operand (operands[0], DImode))
-+        {
-+          rtx first, second;
-+          split_double (operands[1], &first, &second);
-+          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first));
-+          emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second));
-+          DONE;
-+        }
-+
-+      if (!TARGET_CONST16)
-+        operands[1] = force_const_mem (DImode, operands[1]);
-+    }
- 
-   if (!register_operand (operands[0], DImode)
-       && !register_operand (operands[1], DImode))
diff --git a/patches/gcc10.1/gcc-improve-shift-operations.patch b/patches/gcc10.1/gcc-xtensa-add-optimizations-for-shift-operations.patch
similarity index 58%
rename from patches/gcc10.1/gcc-improve-shift-operations.patch
rename to patches/gcc10.1/gcc-xtensa-add-optimizations-for-shift-operations.patch
index 86825df..6eb160c 100644
--- a/patches/gcc10.1/gcc-improve-shift-operations.patch
+++ b/patches/gcc10.1/gcc-xtensa-add-optimizations-for-shift-operations.patch
@@ -1,8 +1,26 @@
+From 40bf68bbe0bdba305fde4ab825a06c085ba486fc Mon Sep 17 00:00:00 2001
+From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+Date: Wed, 16 Dec 2020 12:53:56 -0800
+Subject: [PATCH] gcc: xtensa: add optimizations for shift operations
+
+2020-12-16  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+gcc/
+	* config/xtensa/xtensa.md (*ashlsi3_1, *ashlsi3_3x, *ashrsi3_3x)
+	(*lshrsi3_3x): New patterns.
+
+gcc/testsuite/
+	* gcc.target/xtensa/shifts.c: New test.
+---
+ gcc/config/xtensa/xtensa.md              | 43 ++++++++++++++++++++++++
+ gcc/testsuite/gcc.target/xtensa/shifts.c | 31 +++++++++++++++++
+ 2 files changed, 74 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/shifts.c
+
 diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
-index 21d60ffa..e82c466d 100644
+index 5fbe4ad4af9f..462a7244a35d 100644
 --- a/gcc/config/xtensa/xtensa.md
 +++ b/gcc/config/xtensa/xtensa.md
-@@ -1050,6 +1050,16 @@
+@@ -1071,6 +1071,16 @@
    operands[1] = xtensa_copy_incoming_a7 (operands[1]);
  })
  
@@ -19,7 +37,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "ashlsi3_internal"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1062,6 +1072,17 @@
+@@ -1083,6 +1093,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
  
@@ -37,7 +55,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1074,6 +1095,17 @@
+@@ -1095,6 +1116,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
  
@@ -55,7 +73,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1093,6 +1125,17 @@
+@@ -1114,6 +1146,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
  
@@ -73,3 +91,40 @@ index 21d60ffa..e82c466d 100644
  (define_insn "rotlsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(rotate:SI (match_operand:SI 1 "register_operand" "r,r")
+diff --git a/gcc/testsuite/gcc.target/xtensa/shifts.c b/gcc/testsuite/gcc.target/xtensa/shifts.c
+new file mode 100644
+index 000000000000..8d7e4a928d3a
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/shifts.c
+@@ -0,0 +1,31 @@
++/* { dg-do compile } */
++/* { dg-options "-O1" } */
++
++int lshift1(int v)
++{
++  return v << 1;
++}
++
++int lshift2(int v, int s)
++{
++  return v << (s * 8);
++}
++
++unsigned int lshift3(unsigned int v, int s)
++{
++  return v << (s * 8);
++}
++
++int rshift1(int v, int s)
++{
++  return v >> (s * 8);
++}
++
++unsigned int rshift2(unsigned int v, int s)
++{
++  return v >> (s * 8);
++}
++
++/* { dg-final { scan-assembler-not "slli" } } */
++/* { dg-final { scan-assembler-times "ssa8l" 2 } } */
++/* { dg-final { scan-assembler-times "ssa8b" 2 } } */
diff --git a/patches/gcc10.1/gcc-xtensa-fix-PR-target-98285.patch b/patches/gcc10.1/gcc-xtensa-fix-PR-target-98285.patch
new file mode 100644
index 0000000..d1ea1ec
--- /dev/null
+++ b/patches/gcc10.1/gcc-xtensa-fix-PR-target-98285.patch
@@ -0,0 +1,137 @@
+From 06ff8708f0b834cf1b35afa46113c6c973905cad Mon Sep 17 00:00:00 2001
+From: Max Filippov <jcmvbkbc@gmail.com>
+Date: Sat, 12 Dec 2020 12:14:40 -0800
+Subject: [PATCH] gcc: xtensa: fix PR target/98285
+
+2020-12-14  Max Filippov  <jcmvbkbc@gmail.com>
+gcc/
+	* config/xtensa/predicates.md (addsubx_operand): Change accepted
+	values from 2/4/8 to 1..3.
+	* config/xtensa/xtensa.md (*addx, *subx): Change RTL pattern
+	to use 'ashift' instead of 'mult'. Update operands[3] value.
+
+gcc/testsuite/
+	* gcc.target/xtensa/pr98285.c: New test.
+---
+ gcc/config/xtensa/predicates.md           |  5 +--
+ gcc/config/xtensa/xtensa.md               | 18 +++++---
+ gcc/testsuite/gcc.target/xtensa/pr98285.c | 54 +++++++++++++++++++++++
+ 3 files changed, 68 insertions(+), 9 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/pr98285.c
+
+diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
+index 1721640dc79e..eb52b05aafad 100644
+--- a/gcc/config/xtensa/predicates.md
++++ b/gcc/config/xtensa/predicates.md
+@@ -25,9 +25,8 @@
+ 
+ (define_predicate "addsubx_operand"
+   (and (match_code "const_int")
+-       (match_test "INTVAL (op) == 2
+-		    || INTVAL (op) == 4
+-		    || INTVAL (op) == 8")))
++       (match_test "INTVAL (op) >= 1
++		    && INTVAL (op) <= 3")))
+ 
+ (define_predicate "arith_operand"
+   (ior (and (match_code "const_int")
+diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
+index 749fe477d562..671c4bea144f 100644
+--- a/gcc/config/xtensa/xtensa.md
++++ b/gcc/config/xtensa/xtensa.md
+@@ -162,11 +162,14 @@
+ 
+ (define_insn "*addx"
+   [(set (match_operand:SI 0 "register_operand" "=a")
+-	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+-			  (match_operand:SI 3 "addsubx_operand" "i"))
++	(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
++			    (match_operand:SI 3 "addsubx_operand" "i"))
+ 		 (match_operand:SI 2 "register_operand" "r")))]
+   "TARGET_ADDX"
+-  "addx%3\t%0, %1, %2"
++{
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++  return "addx%3\t%0, %1, %2";
++}
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+    (set_attr "length"	"3")])
+@@ -196,11 +199,14 @@
+ 
+ (define_insn "*subx"
+   [(set (match_operand:SI 0 "register_operand" "=a")
+-	(minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+-			   (match_operand:SI 3 "addsubx_operand" "i"))
++	(minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
++			     (match_operand:SI 3 "addsubx_operand" "i"))
+ 		  (match_operand:SI 2 "register_operand" "r")))]
+   "TARGET_ADDX"
+-  "subx%3\t%0, %1, %2"
++{
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++  return "subx%3\t%0, %1, %2";
++}
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+    (set_attr "length"	"3")])
+diff --git a/gcc/testsuite/gcc.target/xtensa/pr98285.c b/gcc/testsuite/gcc.target/xtensa/pr98285.c
+new file mode 100644
+index 000000000000..2c037d546565
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/pr98285.c
+@@ -0,0 +1,54 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int mul3(int v)
++{
++  return v * 3;
++}
++
++int mul5(int v)
++{
++  return v * 5;
++}
++
++int mul7(int v)
++{
++  return v * 7;
++}
++
++int mul9(int v)
++{
++  return v * 9;
++}
++
++int mul2sub(int a, int b)
++{
++  return a * 2 - b;
++}
++
++int mul4sub(int a, int b)
++{
++  return a * 4 - b;
++}
++
++short index2(short *p, int i)
++{
++  return p[i];
++}
++
++int index4(int *p, int i)
++{
++  return p[i];
++}
++
++long long index8(long long *p, int i)
++{
++  return p[i];
++}
++
++/* { dg-final { scan-assembler-times "addx2" 2 } } */
++/* { dg-final { scan-assembler-times "addx4" 2 } } */
++/* { dg-final { scan-assembler-times "addx8" 2 } } */
++/* { dg-final { scan-assembler-times "subx2" 1 } } */
++/* { dg-final { scan-assembler-times "subx4" 1 } } */
++/* { dg-final { scan-assembler-times "subx8" 1 } } */
diff --git a/patches/gcc10.1/gcc-xtensa-implement-bswapsi2-bswapdi2-and-helpers.patch b/patches/gcc10.1/gcc-xtensa-implement-bswapsi2-bswapdi2-and-helpers.patch
new file mode 100644
index 0000000..a896377
--- /dev/null
+++ b/patches/gcc10.1/gcc-xtensa-implement-bswapsi2-bswapdi2-and-helpers.patch
@@ -0,0 +1,138 @@
+From 18e86fae2a14f78e70aae06afce6bb9853068bb1 Mon Sep 17 00:00:00 2001
+From: Max Filippov <jcmvbkbc@gmail.com>
+Date: Sun, 20 Dec 2020 02:23:12 -0800
+Subject: [PATCH] gcc: xtensa: implement bswapsi2, bswapdi2 and helpers
+
+2020-12-20  Max Filippov  <jcmvbkbc@gmail.com>
+gcc/
+	* config/xtensa/xtensa.md (bswapsi2, bswapdi2): New patterns.
+
+gcc/testsuite/
+	* gcc.target/xtensa/bswap.c: New test.
+
+libgcc/
+	* config/xtensa/lib1funcs.S (__bswapsi2, __bswapdi2): New
+	functions.
+	* config/xtensa/t-xtensa (LIB1ASMFUNCS): Add _bswapsi2 and
+	_bswapdi2.
+---
+ gcc/config/xtensa/xtensa.md             | 21 +++++++++++++
+ gcc/testsuite/gcc.target/xtensa/bswap.c | 14 +++++++++
+ libgcc/config/xtensa/lib1funcs.S        | 39 +++++++++++++++++++++++++
+ libgcc/config/xtensa/t-xtensa           |  1 +
+ 4 files changed, 75 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/bswap.c
+
+diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
+index 462a7244a35d..cfb6a546d922 100644
+--- a/gcc/config/xtensa/xtensa.md
++++ b/gcc/config/xtensa/xtensa.md
+@@ -468,6 +468,27 @@
+   DONE;
+ })
+ 
++
++;; Byte swap.
++
++(define_insn "bswapsi2"
++  [(set (match_operand:SI 0 "register_operand" "=&a")
++	(bswap:SI (match_operand:SI 1 "register_operand" "r")))]
++  "!optimize_size"
++  "ssai\t8\;srli\t%0, %1, 16\;src\t%0, %0, %1\;src\t%0, %0, %0\;src\t%0, %1, %0"
++  [(set_attr "type"	"arith")
++   (set_attr "mode"	"SI")
++   (set_attr "length"	"15")])
++
++(define_insn "bswapdi2"
++  [(set (match_operand:DI 0 "register_operand" "=&a")
++	(bswap:DI (match_operand:DI 1 "register_operand" "r")))]
++  "!optimize_size"
++  "ssai\t8\;srli\t%0, %D1, 16\;src\t%0, %0, %D1\;src\t%0, %0, %0\;src\t%0, %D1, %0\;srli\t%D0, %1, 16\;src\t%D0, %D0, %1\;src\t%D0, %D0, %D0\;src\t%D0, %1, %D0"
++  [(set_attr "type"	"arith")
++   (set_attr "mode"	"DI")
++   (set_attr "length"	"27")])
++
+ 
+ ;; Negation and one's complement.
+ 
+diff --git a/gcc/testsuite/gcc.target/xtensa/bswap.c b/gcc/testsuite/gcc.target/xtensa/bswap.c
+new file mode 100644
+index 000000000000..057a3569703f
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/bswap.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O1" } */
++
++unsigned long f32(unsigned long v)
++{
++  return __builtin_bswap32(v);
++}
++
++unsigned long long f64(unsigned long long v)
++{
++  return __builtin_bswap64(v);
++}
++
++/* { dg-final { scan-assembler-times "ssai" 2 } } */
+diff --git a/libgcc/config/xtensa/lib1funcs.S b/libgcc/config/xtensa/lib1funcs.S
+index 77e78885d84b..b19deae14483 100644
+--- a/libgcc/config/xtensa/lib1funcs.S
++++ b/libgcc/config/xtensa/lib1funcs.S
+@@ -840,5 +840,44 @@ __lshrdi3:
+ #endif /* L_lshrdi3 */
+ 
+ 
++#ifdef L_bswapsi2
++	.align	4
++	.global	__bswapsi2
++	.type	__bswapsi2, @function
++__bswapsi2:
++	leaf_entry sp, 16
++	ssai	8
++	srli	a3, a2, 16
++	src	a3, a3, a2
++	src	a3, a3, a3
++	src	a2, a2, a3
++	leaf_return
++	.size	__bswapsi2, . - __bswapsi2
++
++#endif /* L_bswapsi2 */
++
++
++#ifdef L_bswapdi2
++	.align	4
++	.global	__bswapdi2
++	.type	__bswapdi2, @function
++__bswapdi2:
++	leaf_entry sp, 16
++	ssai	8
++	srli	a4, a2, 16
++	src	a4, a4, a2
++	src	a4, a4, a4
++	src	a4, a2, a4
++	srli	a2, a3, 16
++	src	a2, a2, a3
++	src	a2, a2, a2
++	src	a2, a3, a2
++	mov	a3, a4
++	leaf_return
++	.size	__bswapdi2, . - __bswapdi2
++
++#endif /* L_bswapdi2 */
++
++
+ #include "ieee754-df.S"
+ #include "ieee754-sf.S"
+diff --git a/libgcc/config/xtensa/t-xtensa b/libgcc/config/xtensa/t-xtensa
+index 90df5f15daa9..9836c96aefc6 100644
+--- a/libgcc/config/xtensa/t-xtensa
++++ b/libgcc/config/xtensa/t-xtensa
+@@ -2,6 +2,7 @@ LIB1ASMSRC = xtensa/lib1funcs.S
+ LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 _udivsi3 _umodsi3 \
+ 	_umulsidi3 _clz _clzsi2 _ctzsi2 _ffssi2 \
+ 	_ashldi3 _ashrdi3 _lshrdi3 \
++	_bswapsi2 _bswapdi2 \
+ 	_negsf2 _addsubsf3 _mulsf3 _divsf3 _cmpsf2 _fixsfsi _fixsfdi \
+ 	_fixunssfsi _fixunssfdi _floatsisf _floatunsisf \
+ 	_sqrtf _recipsf2 _rsqrtsf2 \
diff --git a/patches/gcc10.1/gcc-xtensa-rearrange-DI-mode-constant-loading.patch b/patches/gcc10.1/gcc-xtensa-rearrange-DI-mode-constant-loading.patch
new file mode 100644
index 0000000..41c1ef2
--- /dev/null
+++ b/patches/gcc10.1/gcc-xtensa-rearrange-DI-mode-constant-loading.patch
@@ -0,0 +1,72 @@
+From 64a54505ec8249178b9767d1420354f8eb55de50 Mon Sep 17 00:00:00 2001
+From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+Date: Wed, 16 Dec 2020 12:53:56 -0800
+Subject: [PATCH] gcc: xtensa: rearrange DI mode constant loading
+
+2020-12-16  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+gcc/
+	* config/xtensa/xtensa.c (xtensa_emit_move_sequence): Try to
+	replace 'l32r' with 'movi' + 'slli' when optimizing for size.
+	* config/xtensa/xtensa.md (movdi): Split loading DI mode constant
+	into register pair into two loads of SI mode constants.
+---
+ gcc/config/xtensa/xtensa.c  | 15 +++++++++++++++
+ gcc/config/xtensa/xtensa.md | 19 +++++++++++++++++--
+ 2 files changed, 32 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
+index be1eb21a0b60..1cdc39acfffa 100644
+--- a/gcc/config/xtensa/xtensa.c
++++ b/gcc/config/xtensa/xtensa.c
+@@ -1082,6 +1082,21 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
+ 
+       if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16)
+ 	{
++	  /* Try to emit MOVI + SLLI sequence, that is smaller
++	     than L32R + literal.  */
++	  if (optimize_size && mode == SImode && register_operand (dst, mode))
++	    {
++	      HOST_WIDE_INT srcval = INTVAL (src);
++	      int shift = ctz_hwi (srcval);
++
++	      if (xtensa_simm12b (srcval >> shift))
++		{
++		  emit_move_insn (dst, GEN_INT (srcval >> shift));
++		  emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift)));
++		  return 1;
++		}
++	    }
++
+ 	  src = force_const_mem (SImode, src);
+ 	  operands[1] = src;
+ 	}
+diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
+index 671c4bea144f..5fbe4ad4af9f 100644
+--- a/gcc/config/xtensa/xtensa.md
++++ b/gcc/config/xtensa/xtensa.md
+@@ -727,8 +727,23 @@
+ 	(match_operand:DI 1 "general_operand" ""))]
+   ""
+ {
+-  if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
+-    operands[1] = force_const_mem (DImode, operands[1]);
++  if (CONSTANT_P (operands[1]))
++    {
++      /* Split in halves if 64-bit Const-to-Reg moves
++	 because of offering further optimization opportunities.  */
++      if (register_operand (operands[0], DImode))
++	{
++	  rtx first, second;
++
++	  split_double (operands[1], &first, &second);
++	  emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first));
++	  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second));
++	  DONE;
++	}
++
++      if (!TARGET_CONST16)
++	operands[1] = force_const_mem (DImode, operands[1]);
++    }
+ 
+   if (!register_operand (operands[0], DImode)
+       && !register_operand (operands[1], DImode))
diff --git a/patches/gcc10.2/gcc-repair-TARGET_ADDX.patch b/patches/gcc10.2/gcc-repair-TARGET_ADDX.patch
deleted file mode 100644
index 47d88e6..0000000
--- a/patches/gcc10.2/gcc-repair-TARGET_ADDX.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
-index 5bf4b9f5..ffdc4cb2 100644
---- a/gcc/config/xtensa/predicates.md
-+++ b/gcc/config/xtensa/predicates.md
-@@ -29,6 +29,12 @@
- 		    || INTVAL (op) == 4
- 		    || INTVAL (op) == 8")))
- 
-+(define_predicate "addsubx_alt_operand"
-+  (and (match_code "const_int")
-+       (match_test "INTVAL (op) == 1
-+		    || INTVAL (op) == 2
-+		    || INTVAL (op) == 3")))
-+
- (define_predicate "arith_operand"
-   (ior (and (match_code "const_int")
- 	    (match_test "xtensa_simm8 (INTVAL (op))"))
-diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
-index b95b9901..7d7970f9 100644
---- a/gcc/config/xtensa/xtensa.md
-+++ b/gcc/config/xtensa/xtensa.md
-@@ -170,6 +170,20 @@
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"SI")
-    (set_attr "length"	"3")])
-+ 
-+(define_insn "*addx_alt"
-+  [(set (match_operand:SI 0 "register_operand" "=a")
-+	(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-+			    (match_operand:SI 3 "addsubx_alt_operand" "i"))
-+		 (match_operand:SI 2 "register_operand" "r")))]
-+  "TARGET_ADDX"
-+{
-+  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-+  return "addx%3\t%0, %1, %2";
-+}
-+  [(set_attr "type"	"arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"3")])
- 
- (define_insn "addsf3"
-   [(set (match_operand:SF 0 "register_operand" "=f")
-@@ -204,6 +218,20 @@
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"SI")
-    (set_attr "length"	"3")])
-+
-+(define_insn "*subx_alt"
-+  [(set (match_operand:SI 0 "register_operand" "=a")
-+	(minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-+			     (match_operand:SI 3 "addsubx_alt_operand" "i"))
-+		  (match_operand:SI 2 "register_operand" "r")))]
-+  "TARGET_ADDX"
-+{
-+  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
-+  return "subx%3\t%0, %1, %2";
-+}
-+  [(set_attr "type"	"arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"3")])
- 
- (define_insn "subsf3"
-   [(set (match_operand:SF 0 "register_operand" "=f")
diff --git a/patches/gcc10.2/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch b/patches/gcc10.2/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch
deleted file mode 100644
index 7691ad9..0000000
--- a/patches/gcc10.2/gcc-try-to-avoid-using-L32R-to-load-32-64bit-const.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
-index 953f90a0..14be4081 100644
---- a/gcc/config/xtensa/xtensa.c
-+++ b/gcc/config/xtensa/xtensa.c
-@@ -1072,6 +1072,21 @@
- 
-       if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16)
- 	{
-+	  /* Try to emit MOVI.N + SLLI sequence, that is smaller than L32R + constant pool.  */
-+	  if (TARGET_DENSITY && mode == SImode && register_operand (dst, mode))
-+	    {
-+	      int srcval = INTVAL (src);
-+	      int shift;
-+	      if (! (srcval & 1))
-+		for (srcval >>= 1, shift = 1; ! (srcval & 1) && shift < 32; srcval >>= 1, shift++)
-+		  if (srcval >= -32 && srcval <= 95)
-+		    {
-+		      emit_move_insn (dst, GEN_INT (srcval));
-+		      emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift)));
-+		      return 1;
-+		    }
-+	    }
-+
- 	  src = force_const_mem (SImode, src);
- 	  operands[1] = src;
- 	}
-diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
-index 8e304a6f..dbb36b11 100644
---- a/gcc/config/xtensa/xtensa.md
-+++ b/gcc/config/xtensa/xtensa.md
-@@ -721,8 +721,22 @@
- 	(match_operand:DI 1 "general_operand" ""))]
-   ""
- {
--  if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
--    operands[1] = force_const_mem (DImode, operands[1]);
-+  if (CONSTANT_P (operands[1]))
-+    {
-+      /* Split in halves if 64-bit Const-to-Reg moves
-+         because of offering further optimization opportunities.  */
-+      if (register_operand (operands[0], DImode))
-+        {
-+          rtx first, second;
-+          split_double (operands[1], &first, &second);
-+          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first));
-+          emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second));
-+          DONE;
-+        }
-+
-+      if (!TARGET_CONST16)
-+        operands[1] = force_const_mem (DImode, operands[1]);
-+    }
- 
-   if (!register_operand (operands[0], DImode)
-       && !register_operand (operands[1], DImode))
diff --git a/patches/gcc10.2/gcc-improve-shift-operations.patch b/patches/gcc10.2/gcc-xtensa-add-optimizations-for-shift-operations.patch
similarity index 58%
rename from patches/gcc10.2/gcc-improve-shift-operations.patch
rename to patches/gcc10.2/gcc-xtensa-add-optimizations-for-shift-operations.patch
index 86825df..6eb160c 100644
--- a/patches/gcc10.2/gcc-improve-shift-operations.patch
+++ b/patches/gcc10.2/gcc-xtensa-add-optimizations-for-shift-operations.patch
@@ -1,8 +1,26 @@
+From 40bf68bbe0bdba305fde4ab825a06c085ba486fc Mon Sep 17 00:00:00 2001
+From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+Date: Wed, 16 Dec 2020 12:53:56 -0800
+Subject: [PATCH] gcc: xtensa: add optimizations for shift operations
+
+2020-12-16  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+gcc/
+	* config/xtensa/xtensa.md (*ashlsi3_1, *ashlsi3_3x, *ashrsi3_3x)
+	(*lshrsi3_3x): New patterns.
+
+gcc/testsuite/
+	* gcc.target/xtensa/shifts.c: New test.
+---
+ gcc/config/xtensa/xtensa.md              | 43 ++++++++++++++++++++++++
+ gcc/testsuite/gcc.target/xtensa/shifts.c | 31 +++++++++++++++++
+ 2 files changed, 74 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/shifts.c
+
 diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
-index 21d60ffa..e82c466d 100644
+index 5fbe4ad4af9f..462a7244a35d 100644
 --- a/gcc/config/xtensa/xtensa.md
 +++ b/gcc/config/xtensa/xtensa.md
-@@ -1050,6 +1050,16 @@
+@@ -1071,6 +1071,16 @@
    operands[1] = xtensa_copy_incoming_a7 (operands[1]);
  })
  
@@ -19,7 +37,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "ashlsi3_internal"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1062,6 +1072,17 @@
+@@ -1083,6 +1093,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
  
@@ -37,7 +55,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1074,6 +1095,17 @@
+@@ -1095,6 +1116,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
  
@@ -55,7 +73,7 @@ index 21d60ffa..e82c466d 100644
  (define_insn "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-@@ -1093,6 +1125,17 @@
+@@ -1114,6 +1146,17 @@
     (set_attr "mode"	"SI")
     (set_attr "length"	"3,6")])
  
@@ -73,3 +91,40 @@ index 21d60ffa..e82c466d 100644
  (define_insn "rotlsi3"
    [(set (match_operand:SI 0 "register_operand" "=a,a")
  	(rotate:SI (match_operand:SI 1 "register_operand" "r,r")
+diff --git a/gcc/testsuite/gcc.target/xtensa/shifts.c b/gcc/testsuite/gcc.target/xtensa/shifts.c
+new file mode 100644
+index 000000000000..8d7e4a928d3a
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/shifts.c
+@@ -0,0 +1,31 @@
++/* { dg-do compile } */
++/* { dg-options "-O1" } */
++
++int lshift1(int v)
++{
++  return v << 1;
++}
++
++int lshift2(int v, int s)
++{
++  return v << (s * 8);
++}
++
++unsigned int lshift3(unsigned int v, int s)
++{
++  return v << (s * 8);
++}
++
++int rshift1(int v, int s)
++{
++  return v >> (s * 8);
++}
++
++unsigned int rshift2(unsigned int v, int s)
++{
++  return v >> (s * 8);
++}
++
++/* { dg-final { scan-assembler-not "slli" } } */
++/* { dg-final { scan-assembler-times "ssa8l" 2 } } */
++/* { dg-final { scan-assembler-times "ssa8b" 2 } } */
diff --git a/patches/gcc10.2/gcc-xtensa-fix-PR-target-98285.patch b/patches/gcc10.2/gcc-xtensa-fix-PR-target-98285.patch
new file mode 100644
index 0000000..d1ea1ec
--- /dev/null
+++ b/patches/gcc10.2/gcc-xtensa-fix-PR-target-98285.patch
@@ -0,0 +1,137 @@
+From 06ff8708f0b834cf1b35afa46113c6c973905cad Mon Sep 17 00:00:00 2001
+From: Max Filippov <jcmvbkbc@gmail.com>
+Date: Sat, 12 Dec 2020 12:14:40 -0800
+Subject: [PATCH] gcc: xtensa: fix PR target/98285
+
+2020-12-14  Max Filippov  <jcmvbkbc@gmail.com>
+gcc/
+	* config/xtensa/predicates.md (addsubx_operand): Change accepted
+	values from 2/4/8 to 1..3.
+	* config/xtensa/xtensa.md (*addx, *subx): Change RTL pattern
+	to use 'ashift' instead of 'mult'. Update operands[3] value.
+
+gcc/testsuite/
+	* gcc.target/xtensa/pr98285.c: New test.
+---
+ gcc/config/xtensa/predicates.md           |  5 +--
+ gcc/config/xtensa/xtensa.md               | 18 +++++---
+ gcc/testsuite/gcc.target/xtensa/pr98285.c | 54 +++++++++++++++++++++++
+ 3 files changed, 68 insertions(+), 9 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/pr98285.c
+
+diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
+index 1721640dc79e..eb52b05aafad 100644
+--- a/gcc/config/xtensa/predicates.md
++++ b/gcc/config/xtensa/predicates.md
+@@ -25,9 +25,8 @@
+ 
+ (define_predicate "addsubx_operand"
+   (and (match_code "const_int")
+-       (match_test "INTVAL (op) == 2
+-		    || INTVAL (op) == 4
+-		    || INTVAL (op) == 8")))
++       (match_test "INTVAL (op) >= 1
++		    && INTVAL (op) <= 3")))
+ 
+ (define_predicate "arith_operand"
+   (ior (and (match_code "const_int")
+diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
+index 749fe477d562..671c4bea144f 100644
+--- a/gcc/config/xtensa/xtensa.md
++++ b/gcc/config/xtensa/xtensa.md
+@@ -162,11 +162,14 @@
+ 
+ (define_insn "*addx"
+   [(set (match_operand:SI 0 "register_operand" "=a")
+-	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+-			  (match_operand:SI 3 "addsubx_operand" "i"))
++	(plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
++			    (match_operand:SI 3 "addsubx_operand" "i"))
+ 		 (match_operand:SI 2 "register_operand" "r")))]
+   "TARGET_ADDX"
+-  "addx%3\t%0, %1, %2"
++{
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++  return "addx%3\t%0, %1, %2";
++}
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+    (set_attr "length"	"3")])
+@@ -196,11 +199,14 @@
+ 
+ (define_insn "*subx"
+   [(set (match_operand:SI 0 "register_operand" "=a")
+-	(minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+-			   (match_operand:SI 3 "addsubx_operand" "i"))
++	(minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
++			     (match_operand:SI 3 "addsubx_operand" "i"))
+ 		  (match_operand:SI 2 "register_operand" "r")))]
+   "TARGET_ADDX"
+-  "subx%3\t%0, %1, %2"
++{
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++  return "subx%3\t%0, %1, %2";
++}
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+    (set_attr "length"	"3")])
+diff --git a/gcc/testsuite/gcc.target/xtensa/pr98285.c b/gcc/testsuite/gcc.target/xtensa/pr98285.c
+new file mode 100644
+index 000000000000..2c037d546565
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/pr98285.c
+@@ -0,0 +1,54 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int mul3(int v)
++{
++  return v * 3;
++}
++
++int mul5(int v)
++{
++  return v * 5;
++}
++
++int mul7(int v)
++{
++  return v * 7;
++}
++
++int mul9(int v)
++{
++  return v * 9;
++}
++
++int mul2sub(int a, int b)
++{
++  return a * 2 - b;
++}
++
++int mul4sub(int a, int b)
++{
++  return a * 4 - b;
++}
++
++short index2(short *p, int i)
++{
++  return p[i];
++}
++
++int index4(int *p, int i)
++{
++  return p[i];
++}
++
++long long index8(long long *p, int i)
++{
++  return p[i];
++}
++
++/* { dg-final { scan-assembler-times "addx2" 2 } } */
++/* { dg-final { scan-assembler-times "addx4" 2 } } */
++/* { dg-final { scan-assembler-times "addx8" 2 } } */
++/* { dg-final { scan-assembler-times "subx2" 1 } } */
++/* { dg-final { scan-assembler-times "subx4" 1 } } */
++/* { dg-final { scan-assembler-times "subx8" 1 } } */
diff --git a/patches/gcc10.2/gcc-xtensa-implement-bswapsi2-bswapdi2-and-helpers.patch b/patches/gcc10.2/gcc-xtensa-implement-bswapsi2-bswapdi2-and-helpers.patch
new file mode 100644
index 0000000..a896377
--- /dev/null
+++ b/patches/gcc10.2/gcc-xtensa-implement-bswapsi2-bswapdi2-and-helpers.patch
@@ -0,0 +1,138 @@
+From 18e86fae2a14f78e70aae06afce6bb9853068bb1 Mon Sep 17 00:00:00 2001
+From: Max Filippov <jcmvbkbc@gmail.com>
+Date: Sun, 20 Dec 2020 02:23:12 -0800
+Subject: [PATCH] gcc: xtensa: implement bswapsi2, bswapdi2 and helpers
+
+2020-12-20  Max Filippov  <jcmvbkbc@gmail.com>
+gcc/
+	* config/xtensa/xtensa.md (bswapsi2, bswapdi2): New patterns.
+
+gcc/testsuite/
+	* gcc.target/xtensa/bswap.c: New test.
+
+libgcc/
+	* config/xtensa/lib1funcs.S (__bswapsi2, __bswapdi2): New
+	functions.
+	* config/xtensa/t-xtensa (LIB1ASMFUNCS): Add _bswapsi2 and
+	_bswapdi2.
+---
+ gcc/config/xtensa/xtensa.md             | 21 +++++++++++++
+ gcc/testsuite/gcc.target/xtensa/bswap.c | 14 +++++++++
+ libgcc/config/xtensa/lib1funcs.S        | 39 +++++++++++++++++++++++++
+ libgcc/config/xtensa/t-xtensa           |  1 +
+ 4 files changed, 75 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/xtensa/bswap.c
+
+diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
+index 462a7244a35d..cfb6a546d922 100644
+--- a/gcc/config/xtensa/xtensa.md
++++ b/gcc/config/xtensa/xtensa.md
+@@ -468,6 +468,27 @@
+   DONE;
+ })
+ 
++
++;; Byte swap.
++
++(define_insn "bswapsi2"
++  [(set (match_operand:SI 0 "register_operand" "=&a")
++	(bswap:SI (match_operand:SI 1 "register_operand" "r")))]
++  "!optimize_size"
++  "ssai\t8\;srli\t%0, %1, 16\;src\t%0, %0, %1\;src\t%0, %0, %0\;src\t%0, %1, %0"
++  [(set_attr "type"	"arith")
++   (set_attr "mode"	"SI")
++   (set_attr "length"	"15")])
++
++(define_insn "bswapdi2"
++  [(set (match_operand:DI 0 "register_operand" "=&a")
++	(bswap:DI (match_operand:DI 1 "register_operand" "r")))]
++  "!optimize_size"
++  "ssai\t8\;srli\t%0, %D1, 16\;src\t%0, %0, %D1\;src\t%0, %0, %0\;src\t%0, %D1, %0\;srli\t%D0, %1, 16\;src\t%D0, %D0, %1\;src\t%D0, %D0, %D0\;src\t%D0, %1, %D0"
++  [(set_attr "type"	"arith")
++   (set_attr "mode"	"DI")
++   (set_attr "length"	"27")])
++
+ 
+ ;; Negation and one's complement.
+ 
+diff --git a/gcc/testsuite/gcc.target/xtensa/bswap.c b/gcc/testsuite/gcc.target/xtensa/bswap.c
+new file mode 100644
+index 000000000000..057a3569703f
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/xtensa/bswap.c
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O1" } */
++
++unsigned long f32(unsigned long v)
++{
++  return __builtin_bswap32(v);
++}
++
++unsigned long long f64(unsigned long long v)
++{
++  return __builtin_bswap64(v);
++}
++
++/* { dg-final { scan-assembler-times "ssai" 2 } } */
+diff --git a/libgcc/config/xtensa/lib1funcs.S b/libgcc/config/xtensa/lib1funcs.S
+index 77e78885d84b..b19deae14483 100644
+--- a/libgcc/config/xtensa/lib1funcs.S
++++ b/libgcc/config/xtensa/lib1funcs.S
+@@ -840,5 +840,44 @@ __lshrdi3:
+ #endif /* L_lshrdi3 */
+ 
+ 
++#ifdef L_bswapsi2
++	.align	4
++	.global	__bswapsi2
++	.type	__bswapsi2, @function
++__bswapsi2:
++	leaf_entry sp, 16
++	ssai	8
++	srli	a3, a2, 16
++	src	a3, a3, a2
++	src	a3, a3, a3
++	src	a2, a2, a3
++	leaf_return
++	.size	__bswapsi2, . - __bswapsi2
++
++#endif /* L_bswapsi2 */
++
++
++#ifdef L_bswapdi2
++	.align	4
++	.global	__bswapdi2
++	.type	__bswapdi2, @function
++__bswapdi2:
++	leaf_entry sp, 16
++	ssai	8
++	srli	a4, a2, 16
++	src	a4, a4, a2
++	src	a4, a4, a4
++	src	a4, a2, a4
++	srli	a2, a3, 16
++	src	a2, a2, a3
++	src	a2, a2, a2
++	src	a2, a3, a2
++	mov	a3, a4
++	leaf_return
++	.size	__bswapdi2, . - __bswapdi2
++
++#endif /* L_bswapdi2 */
++
++
+ #include "ieee754-df.S"
+ #include "ieee754-sf.S"
+diff --git a/libgcc/config/xtensa/t-xtensa b/libgcc/config/xtensa/t-xtensa
+index 90df5f15daa9..9836c96aefc6 100644
+--- a/libgcc/config/xtensa/t-xtensa
++++ b/libgcc/config/xtensa/t-xtensa
+@@ -2,6 +2,7 @@ LIB1ASMSRC = xtensa/lib1funcs.S
+ LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 _udivsi3 _umodsi3 \
+ 	_umulsidi3 _clz _clzsi2 _ctzsi2 _ffssi2 \
+ 	_ashldi3 _ashrdi3 _lshrdi3 \
++	_bswapsi2 _bswapdi2 \
+ 	_negsf2 _addsubsf3 _mulsf3 _divsf3 _cmpsf2 _fixsfsi _fixsfdi \
+ 	_fixunssfsi _fixunssfdi _floatsisf _floatunsisf \
+ 	_sqrtf _recipsf2 _rsqrtsf2 \
diff --git a/patches/gcc10.2/gcc-xtensa-rearrange-DI-mode-constant-loading.patch b/patches/gcc10.2/gcc-xtensa-rearrange-DI-mode-constant-loading.patch
new file mode 100644
index 0000000..41c1ef2
--- /dev/null
+++ b/patches/gcc10.2/gcc-xtensa-rearrange-DI-mode-constant-loading.patch
@@ -0,0 +1,72 @@
+From 64a54505ec8249178b9767d1420354f8eb55de50 Mon Sep 17 00:00:00 2001
+From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+Date: Wed, 16 Dec 2020 12:53:56 -0800
+Subject: [PATCH] gcc: xtensa: rearrange DI mode constant loading
+
+2020-12-16  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+gcc/
+	* config/xtensa/xtensa.c (xtensa_emit_move_sequence): Try to
+	replace 'l32r' with 'movi' + 'slli' when optimizing for size.
+	* config/xtensa/xtensa.md (movdi): Split loading DI mode constant
+	into register pair into two loads of SI mode constants.
+---
+ gcc/config/xtensa/xtensa.c  | 15 +++++++++++++++
+ gcc/config/xtensa/xtensa.md | 19 +++++++++++++++++--
+ 2 files changed, 32 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
+index be1eb21a0b60..1cdc39acfffa 100644
+--- a/gcc/config/xtensa/xtensa.c
++++ b/gcc/config/xtensa/xtensa.c
+@@ -1082,6 +1082,21 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
+ 
+       if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16)
+ 	{
++	  /* Try to emit MOVI + SLLI sequence, that is smaller
++	     than L32R + literal.  */
++	  if (optimize_size && mode == SImode && register_operand (dst, mode))
++	    {
++	      HOST_WIDE_INT srcval = INTVAL (src);
++	      int shift = ctz_hwi (srcval);
++
++	      if (xtensa_simm12b (srcval >> shift))
++		{
++		  emit_move_insn (dst, GEN_INT (srcval >> shift));
++		  emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift)));
++		  return 1;
++		}
++	    }
++
+ 	  src = force_const_mem (SImode, src);
+ 	  operands[1] = src;
+ 	}
+diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
+index 671c4bea144f..5fbe4ad4af9f 100644
+--- a/gcc/config/xtensa/xtensa.md
++++ b/gcc/config/xtensa/xtensa.md
+@@ -727,8 +727,23 @@
+ 	(match_operand:DI 1 "general_operand" ""))]
+   ""
+ {
+-  if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
+-    operands[1] = force_const_mem (DImode, operands[1]);
++  if (CONSTANT_P (operands[1]))
++    {
++      /* Split in halves if 64-bit Const-to-Reg moves
++	 because of offering further optimization opportunities.  */
++      if (register_operand (operands[0], DImode))
++	{
++	  rtx first, second;
++
++	  split_double (operands[1], &first, &second);
++	  emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first));
++	  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second));
++	  DONE;
++	}
++
++      if (!TARGET_CONST16)
++	operands[1] = force_const_mem (DImode, operands[1]);
++    }
+ 
+   if (!register_operand (operands[0], DImode)
+       && !register_operand (operands[1], DImode))