From 8ccf71e6ed5ec2e935033a9e0a737558521722e4 Mon Sep 17 00:00:00 2001
From: Jean Pierre Dudey <me@jeandudey.tech>
Date: Wed, 21 Jul 2021 20:21:09 +0200
Subject: [PATCH] Add IC/DC fields to SCB_CCR register

These fields are available only for Cortex-M targets with an instruction
and data cache. As of now only Cortex-M7 and Cortex-M35P have options
for these caches.

Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
---
 Cargo.toml         |  2 ++
 src/map/reg/scb.rs |  6 ++++++
 src/thr/init.rs    | 12 ++++++++++++
 3 files changed, 20 insertions(+)

diff --git a/Cargo.toml b/Cargo.toml
index dec48fa..1890fec 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -40,6 +40,8 @@ bit-band = []
 floating-point-unit = []
 memory-protection-unit = []
 security-extension = []
+instruction-cache = []
+data-cache = []
 
 [dependencies.drone-cortexm-macros]
 version = "=0.14.1"
diff --git a/src/map/reg/scb.rs b/src/map/reg/scb.rs
index 41412c8..4c8133c 100644
--- a/src/map/reg/scb.rs
+++ b/src/map/reg/scb.rs
@@ -128,6 +128,12 @@ reg! {
         reset => 0x0000_0200;
         traits => { RReg WReg };
         fields => {
+            /// Enables L1 instruction cache.
+            #[cfg(feature = "instruction-cache")]
+            IC => { offset => 17; width => 1; traits => { RRRegField WWRegField } };
+            /// Enables L1 data cache.
+            #[cfg(feature = "data-cache")]
+            DC => { offset => 16; width => 1; traits => { RRRegField WWRegField } };
             /// Force exception stacking start in double word aligned address.
             #[cfg(not(cortexm_core = "cortexm_r0p1"))]
             STKALIGN => { offset => 9; width => 1; traits => { RRRegField WWRegField } };
diff --git a/src/thr/init.rs b/src/thr/init.rs
index c598070..d07f7a9 100644
--- a/src/thr/init.rs
+++ b/src/thr/init.rs
@@ -17,6 +17,10 @@ pub unsafe trait ThrsInitToken: Token {
 /// A set of register tokens returned by [`init_extended`].
 #[allow(missing_docs)]
 pub struct ThrInitExtended {
+    #[cfg(feature = "instruction-cache")]
+    pub scb_ccr_ic: scb::ccr::Ic<Srt>,
+    #[cfg(feature = "data-cache")]
+    pub scb_ccr_dc: scb::ccr::Dc<Srt>,
     pub scb_ccr_bfhfnmign: scb::ccr::Bfhfnmign<Srt>,
     pub scb_ccr_div_0_trp: scb::ccr::Div0Trp<Srt>,
     pub scb_ccr_unalign_trp: scb::ccr::UnalignTrp<Srt>,
@@ -67,6 +71,10 @@ pub fn init_extended<T: ThrsInitToken>(_token: T) -> (T::ThrTokens, ThrInitExten
     #[cfg(cortexm_core = "cortexm7_r0p1")]
     scb_ccr.store(|r| r.set_nonbasethrdena());
     let scb::Ccr {
+        #[cfg(feature = "instruction-cache")]
+        ic: scb_ccr_ic,
+        #[cfg(feature = "data-cache")]
+        dc: scb_ccr_dc,
         stkalign,
         bfhfnmign: scb_ccr_bfhfnmign,
         div_0_trp: scb_ccr_div_0_trp,
@@ -81,6 +89,10 @@ pub fn init_extended<T: ThrsInitToken>(_token: T) -> (T::ThrTokens, ThrInitExten
     drop(stkalign);
     drop(nonbasethrdena);
     (unsafe { T::ThrTokens::take() }, ThrInitExtended {
+        #[cfg(feature = "instruction-cache")]
+        scb_ccr_ic,
+        #[cfg(feature = "data-cache")]
+        scb_ccr_dc,
         scb_ccr_bfhfnmign,
         scb_ccr_div_0_trp,
         scb_ccr_unalign_trp,