From b25f5e8e1feb492f68366c7c2d4d000aae20a915 Mon Sep 17 00:00:00 2001
From: Samuel Ortiz <sameo@linux.intel.com>
Date: Sun, 7 Mar 2021 23:53:05 +0100
Subject: [PATCH] do-core1: Move instruction unit tests to do-core

And define a workspace.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
---
 Cargo.toml                 |  5 +++
 do-core/src/instruction.rs | 84 ++++++++++++++++++++++++++++++++++++++
 src/main.rs                | 83 -------------------------------------
 3 files changed, 89 insertions(+), 83 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index d51b0ef..0c82dd1 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -9,3 +9,8 @@ edition = "2018"
 [dependencies]
 clap = { version = "3.0.5", features = ["derive"] }
 do-core = { path = "do-core" }
+
+[workspace]
+members = [
+    "do-core"
+]
diff --git a/do-core/src/instruction.rs b/do-core/src/instruction.rs
index 3fa16e7..40f4380 100644
--- a/do-core/src/instruction.rs
+++ b/do-core/src/instruction.rs
@@ -63,3 +63,87 @@ impl Instruction {
         self.op1
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use crate::instruction::{Instruction, OpCode};
+    use crate::Error;
+
+    #[test]
+    fn test_instruction_disassemble_add_r1_r3() -> Result<(), Error> {
+        let insn_bytes: u32 = 0x1842;
+        let insn = Instruction::disassemble(insn_bytes)?;
+
+        assert_eq!(insn.opcode, OpCode::ADD);
+        assert_eq!(insn.op0, 1);
+        assert_eq!(insn.op1, 3);
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_instruction_disassemble_badop_r9_r1() -> Result<(), Error> {
+        // Use all 6 bytes for the opcode.
+        // It should be invalid for a while...
+        let insn_bytes: u32 = 0x067f;
+        assert!(Instruction::disassemble(insn_bytes).is_err());
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_instruction_disassemble_add_r0_r10() -> Result<(), Error> {
+        let insn_bytes: u32 = 0x20a;
+        assert!(Instruction::disassemble(insn_bytes).is_err());
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_instruction_disassemble_add_r7_r2() -> Result<(), Error> {
+        let insn_bytes: u32 = 0x11c2;
+        let insn = Instruction::disassemble(insn_bytes)?;
+
+        assert_eq!(insn.opcode, OpCode::ADD);
+        assert_eq!(insn.op0, 7);
+        assert_eq!(insn.op1, 2);
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_instruction_disassemble_ldw_r0_r1() -> Result<(), Error> {
+        let insn_bytes: u32 = 0x0800;
+        let insn = Instruction::disassemble(insn_bytes)?;
+
+        assert_eq!(insn.opcode, OpCode::LDW);
+        assert_eq!(insn.op0, 0);
+        assert_eq!(insn.op1, 1);
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_instruction_disassemble_xor_r2_r3() -> Result<(), Error> {
+        let insn_bytes: u32 = 0x1883;
+        let insn = Instruction::disassemble(insn_bytes)?;
+
+        assert_eq!(insn.opcode, OpCode::XOR);
+        assert_eq!(insn.op0, 2);
+        assert_eq!(insn.op1, 3);
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_instruction_disassemble_stw_r5_r0() -> Result<(), Error> {
+        let insn_bytes: u32 = 0x0141;
+        let insn = Instruction::disassemble(insn_bytes)?;
+
+        assert_eq!(insn.opcode, OpCode::STW);
+        assert_eq!(insn.op0, 5);
+        assert_eq!(insn.op1, 0);
+
+        Ok(())
+    }
+}
diff --git a/src/main.rs b/src/main.rs
index 5f30b2c..d29068e 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -56,86 +56,3 @@ fn main() -> Result<(), Error> {
 
     Ok(())
 }
-
-#[cfg(test)]
-mod tests {
-    use crate::{Error, Instruction, OpCode};
-
-    #[test]
-    fn test_instruction_disassemble_add_r1_r3() -> Result<(), Error> {
-        let insn_bytes: u32 = 0x1842;
-        let insn = Instruction::disassemble(insn_bytes)?;
-
-        assert_eq!(insn.opcode, OpCode::ADD);
-        assert_eq!(insn.op0, 1);
-        assert_eq!(insn.op1, 3);
-
-        Ok(())
-    }
-
-    #[test]
-    fn test_instruction_disassemble_badop_r9_r1() -> Result<(), Error> {
-        // Use all 6 bytes for the opcode.
-        // It should be invalid for a while...
-        let insn_bytes: u32 = 0x067f;
-        assert!(Instruction::disassemble(insn_bytes).is_err());
-
-        Ok(())
-    }
-
-    #[test]
-    fn test_instruction_disassemble_add_r0_r10() -> Result<(), Error> {
-        let insn_bytes: u32 = 0x20a;
-        assert!(Instruction::disassemble(insn_bytes).is_err());
-
-        Ok(())
-    }
-
-    #[test]
-    fn test_instruction_disassemble_add_r7_r2() -> Result<(), Error> {
-        let insn_bytes: u32 = 0x11c2;
-        let insn = Instruction::disassemble(insn_bytes)?;
-
-        assert_eq!(insn.opcode, OpCode::ADD);
-        assert_eq!(insn.op0, 7);
-        assert_eq!(insn.op1, 2);
-
-        Ok(())
-    }
-
-    #[test]
-    fn test_instruction_disassemble_ldw_r0_r1() -> Result<(), Error> {
-        let insn_bytes: u32 = 0x0800;
-        let insn = Instruction::disassemble(insn_bytes)?;
-
-        assert_eq!(insn.opcode, OpCode::LDW);
-        assert_eq!(insn.op0, 0);
-        assert_eq!(insn.op1, 1);
-
-        Ok(())
-    }
-
-    #[test]
-    fn test_instruction_disassemble_xor_r2_r3() -> Result<(), Error> {
-        let insn_bytes: u32 = 0x1883;
-        let insn = Instruction::disassemble(insn_bytes)?;
-
-        assert_eq!(insn.opcode, OpCode::XOR);
-        assert_eq!(insn.op0, 2);
-        assert_eq!(insn.op1, 3);
-
-        Ok(())
-    }
-
-    #[test]
-    fn test_instruction_disassemble_stw_r5_r0() -> Result<(), Error> {
-        let insn_bytes: u32 = 0x0141;
-        let insn = Instruction::disassemble(insn_bytes)?;
-
-        assert_eq!(insn.opcode, OpCode::STW);
-        assert_eq!(insn.op0, 5);
-        assert_eq!(insn.op1, 0);
-
-        Ok(())
-    }
-}