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Windows USB plug and unplug stop mounting #19

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briansune opened this issue Jan 8, 2022 · 1 comment
Open

Windows USB plug and unplug stop mounting #19

briansune opened this issue Jan 8, 2022 · 1 comment

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@briansune
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Hi all,

I would like to ask if any people encounter the soft-UART only work after boot / program the FPGA and stop working after plug and un-plug the USB cable.

@briansune
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Hi all,

I would like to ask if any people encounter the soft-UART only work after boot / program the FPGA and stop working after plug and un-plug the USB cable.

Problem can be solved by referencing: https://www.usbmadesimple.co.uk/ums_3.htm
Reset - behavior:

Snooping to the DP and DN line to see host is requesting a reset action during hot plug.

Adding Code to usb_uart.v:

	reg		[31 : 0]		reset_tick;
	reg					host_rst;
	
	localparam ticK_over = (48000000 / 100) - 1;

usb_uart_core u_u_c_np (
        .clk_48mhz  (clk_48mhz),
        .reset      (reset | host_rst),

        // pins - these must be connected properly to the outside world.  See below.
        .usb_p_tx(usb_p_tx),
        .usb_n_tx(usb_n_tx),
        .usb_p_rx(usb_p_rx),
        .usb_n_rx(usb_n_rx),
        .usb_tx_en(usb_tx_en),

        // uart pipeline in
        .uart_in_data( uart_in_data ),
        .uart_in_valid( uart_in_valid ),
        .uart_in_ready( uart_in_ready ),

        // uart pipeline out
        .uart_out_data( uart_out_data ),
        .uart_out_valid( uart_out_valid ),
        .uart_out_ready( uart_out_ready ),

        .debug( debug )
    );

	always@(posedge clk_48mhz)begin
		
		if(reset)begin
			
			host_rst <= 1'b0;
			reset_tick <= 'd0;
			
		end else begin
			if(!(usb_p_in | usb_n_in))begin
				if(reset_tick >= ticK_over)
					reset_tick <= 'd0;
				else
					reset_tick <= reset_tick + 'd1;
			end else begin
				reset_tick <= 'd0;
			end
			
			if(reset_tick >= ticK_over)
				host_rst <= 1'b1;
			else
				host_rst <= 1'b0;
		end
	end

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