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runme.log
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*** Running vivado
with args -log fir.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source fir.tcl -notrace
Command: read_checkpoint -auto_incremental -incremental /home/ubuntu/Desktop/project_1/project_1.srcs/utils_1/imports/synth_1/fir.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from /home/ubuntu/Desktop/project_1/project_1.srcs/utils_1/imports/synth_1/fir.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top fir -part xc7z020clg400-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 89926
WARNING: [Synth 8-9887] parameter declaration becomes local in 'fir' with formal parameter declaration list [/home/ubuntu/lab-fir/fir/rtl/fir.v:47]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'fir' with formal parameter declaration list [/home/ubuntu/lab-fir/fir/rtl/fir.v:48]
WARNING: [Synth 8-9887] parameter declaration becomes local in 'fir' with formal parameter declaration list [/home/ubuntu/lab-fir/fir/rtl/fir.v:49]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 1213 ; free virtual = 7379
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'fir' [/home/ubuntu/lab-fir/fir/rtl/fir.v:3]
INFO: [Synth 8-155] case statement is not full and has no default [/home/ubuntu/lab-fir/fir/rtl/fir.v:77]
INFO: [Synth 8-6155] done synthesizing module 'fir' (0#1) [/home/ubuntu/lab-fir/fir/rtl/fir.v:3]
WARNING: [Synth 8-6014] Unused sequential element rvalid_HIGH_delay3_reg was removed. [/home/ubuntu/lab-fir/fir/rtl/fir.v:187]
WARNING: [Synth 8-6014] Unused sequential element rvalid_HIGH_delay4_reg was removed. [/home/ubuntu/lab-fir/fir/rtl/fir.v:194]
WARNING: [Synth 8-6014] Unused sequential element r_done_reg was removed. [/home/ubuntu/lab-fir/fir/rtl/fir.v:201]
WARNING: [Synth 8-3848] Net last_counter in module/entity fir does not have driver. [/home/ubuntu/lab-fir/fir/rtl/fir.v:63]
WARNING: [Synth 8-3917] design fir has port tap_EN driven by constant 1
WARNING: [Synth 8-3917] design fir has port data_EN driven by constant 1
WARNING: [Synth 8-7129] Port ss_tlast in module fir is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 2306 ; free virtual = 8473
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 2308 ; free virtual = 8474
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 2308 ; free virtual = 8474
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2903.078 ; gain = 0.000 ; free physical = 2308 ; free virtual = 8474
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ubuntu/Desktop/project_1/project_1.srcs/constrs_1/new/constraints.xdc]
Finished Parsing XDC File [/home/ubuntu/Desktop/project_1/project_1.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2919.086 ; gain = 0.000 ; free physical = 2220 ; free virtual = 8387
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2919.086 ; gain = 0.000 ; free physical = 2220 ; free virtual = 8387
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2287 ; free virtual = 8453
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2287 ; free virtual = 8453
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2287 ; free virtual = 8453
---------------------------------------------------------------------------------
WARNING: [Synth 8-327] inferring latch for variable 'next_state_reg' [/home/ubuntu/lab-fir/fir/rtl/fir.v:79]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2275 ; free virtual = 8442
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 3
2 Input 12 Bit Adders := 3
2 Input 6 Bit Adders := 4
2 Input 1 Bit Adders := 1
+---Registers :
32 Bit Registers := 6
12 Bit Registers := 3
6 Bit Registers := 4
2 Bit Registers := 1
1 Bit Registers := 15
+---Multipliers :
32x32 Multipliers := 1
+---Muxes :
2 Input 32 Bit Muxes := 8
2 Input 12 Bit Muxes := 5
2 Input 6 Bit Muxes := 9
3 Input 6 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 28
4 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP mult_result, operation Mode is: A*B.
DSP Report: operator mult_result is absorbed into DSP mult_result.
DSP Report: operator mult_result is absorbed into DSP mult_result.
DSP Report: Generating DSP mult_result, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator mult_result is absorbed into DSP mult_result.
DSP Report: operator mult_result is absorbed into DSP mult_result.
DSP Report: Generating DSP mult_result, operation Mode is: A*B.
DSP Report: operator mult_result is absorbed into DSP mult_result.
DSP Report: operator mult_result is absorbed into DSP mult_result.
DSP Report: Generating DSP mult_result, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator mult_result is absorbed into DSP mult_result.
DSP Report: operator mult_result is absorbed into DSP mult_result.
WARNING: [Synth 8-3917] design fir has port tap_EN driven by constant 1
WARNING: [Synth 8-3917] design fir has port data_EN driven by constant 1
WARNING: [Synth 8-7129] Port ss_tlast in module fir is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2262 ; free virtual = 8433
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|fir | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|fir | (PCIN>>17)+A*B | 15 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|fir | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|fir | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2111 ; free virtual = 8282
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2098 ; free virtual = 8270
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|fir | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|fir | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|fir | PCIN>>17+A*B | 0 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+--------+------+
| |Cell |Count |
+------+--------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 46|
|3 |DSP48E1 | 3|
|4 |LUT1 | 49|
|5 |LUT2 | 29|
|6 |LUT3 | 137|
|7 |LUT4 | 40|
|8 |LUT5 | 56|
|9 |LUT6 | 101|
|10 |FDCE | 289|
|11 |FDPE | 2|
|12 |LD | 2|
|13 |IBUF | 160|
|14 |OBUF | 169|
+------+--------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.086 ; gain = 16.008 ; free physical = 2094 ; free virtual = 8265
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2919.086 ; gain = 0.000 ; free physical = 2163 ; free virtual = 8335
Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2919.094 ; gain = 16.008 ; free physical = 2163 ; free virtual = 8334
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2919.094 ; gain = 0.000 ; free physical = 2257 ; free virtual = 8428
INFO: [Netlist 29-17] Analyzing 51 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'fir' is not ideal for floorplanning, since the cellview 'fir' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2919.094 ; gain = 0.000 ; free physical = 2202 ; free virtual = 8373
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 2 instances were transformed.
LD => LDCE: 2 instances
Synth Design complete, checksum: c2bd25d4
INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 16 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 2919.094 ; gain = 16.016 ; free physical = 2412 ; free virtual = 8584
INFO: [Common 17-1381] The checkpoint '/home/ubuntu/Desktop/project_1/project_1.runs/synth_1/fir.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file fir_utilization_synth.rpt -pb fir_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Oct 20 12:33:26 2023...