[Calyx] Don't generate conflicting assignments when lowering unrolled loops

[rachitnigam]

Currently, when unrolled loops are lowered, they may generate conflicting assignments. The reason that this hasn't cause correctness problems in the past is because all of the assignments attempt to write the same value to the port. However, with Calyx's default simulation backend generating assertions to check for conflicts and the Calyx interpreter doing the same, this is no longer a tenable compilation solution.