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Change memory address bit widths to max(ceil(log2(n)), 1) #322
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For what it's worth, you can just write:
and run The culprit for the bits needed calculation is here: https://github.com/cucapra/dahlia/blob/master/src/main/scala/Utils.scala#L14 It compute |
Great; thanks for clarifying. Yeah, I think To expand a bit, I think the ideal thing to do here would probably be |
(Oh right, I meant to add that I was just using the weird |
I feel like I might be doing something incredibly dumb, but I was just trying to write a program (compiling to FuTIL) and found myself confused about the appropriate width for memory index subscripts. This program type-checks and compiles just fine:
And just for completeness, this program, of course, emits the "zero-padding not supported" error message I would expect in these scenarios:
But here's my confusion: I thought a 4-element memory would have 2-bit addresses. That is, 2 bits is enough to express addresses 0b00 through 0b11, covering the whole memory. We never need the address 0b100 (i.e., 4). In general, I would have thought that the type-checker would want to use log2(size) as the address width, not log2(size)+1.
Like I said above, I feel like I am missing something incredibly obvious, but I'd be ever so grateful if somebody could point out what's going wrong here.
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