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stm8s.h
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stm8s.h
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/**
******************************************************************************
* @file stm8s.h
* @author MCD Application Team
* @version V2.1.0
* @date 18-November-2011
* @brief This file contains all HW registers definitions and memory mapping.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8S_H
#define __STM8S_H
/** @addtogroup STM8S_StdPeriph_Driver
* @{
*/
/* Uncomment the line below according to the target STM8S or STM8A device used in your
application. */
/* #define STM8S208 */ /*!< STM8S High density devices with CAN */
/* #define STM8S207 */ /*!< STM8S High density devices without CAN */
/* #define STM8S007 */ /*!< STM8S Value Line High density devices */
/* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */
/* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */
// #define STM8S105 /*!< STM8S Medium density devices */
/* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */
/* #define STM8AF626x */ /*!< STM8A Medium density devices */
#define STM8S103 /*!< STM8S Low density devices */
/* #define STM8S003 */ /*!< STM8S Value Line Low density devices */
/* #define STM8S903 */ /*!< STM8S Low density devices */
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
- High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,
STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory
density ranges between 32 to 128 Kbytes
- Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,
STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory
density ranges between 8 to 32 Kbytes
- High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers
where the Flash memory density ranges between 32 to 128 Kbytes.
- Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers
where the Flash memory density ranges between 16 to 32-Kbytes.
- Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers
where the Flash density is 8 Kbytes. */
#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \
!defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \
!defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \
!defined (STM8S003)&& !defined (STM8S005)
#error "Please select first the target STM8S/A device used in your application (in stm8s.h file)"
#endif
/******************************************************************************/
/* Library configuration section */
/******************************************************************************/
/* Check the used compiler */
#if defined(__CSMC__)
#define _COSMIC_
#elif defined(__RCST7__)
#define _RAISONANCE_
#elif defined(__ICCSTM8__)
#define _IAR_
#else
#error "Unsupported Compiler!" /* Compiler defines not found */
#endif
#if !defined USE_STDPERIPH_DRIVER
/* Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will be
based on direct access to peripherals registers */
#define USE_STDPERIPH_DRIVER
#endif
/**
* @brief In the following line adjust the value of External High Speed oscillator (HSE)
used in your application
Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
*/
#if !defined HSE_Value
#if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
defined (STM8AF62Ax)
#define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/
#else
#define HSE_VALUE ((u32)12000000) /* Value of the External oscillator in Hz*/
#endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax */
#endif /* HSE_Value */
/**
* @brief Definition of Device on-chip RC oscillator frequencies
*/
#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
#define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */
#ifdef _COSMIC_
#define FAR @far
#define NEAR @near
#define TINY @tiny
#define EEPROM @eeprom
#define CONST const
#elif defined (_RAISONANCE_) /* __RCST7__ */
#define FAR far
#define NEAR data
#define TINY page0
#define EEPROM eeprom
#define CONST code
#if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
defined (STM8AF62Ax)
/*!< Used with memory Models for code higher than 64K */
#define MEMCPY fmemcpy
#else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x */
/*!< Used with memory Models for code less than 64K */
#define MEMCPY memcpy
#endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */
#else /*_IAR_*/
#define FAR __far
#define NEAR __near
#define TINY __tiny
#define EEPROM __eeprom
#define CONST const
#endif /* __CSMC__ */
/* For FLASH routines, select whether pointer will be declared as near (2 bytes,
to handle code smaller than 64KB) or far (3 bytes, to handle code larger
than 64K) */
#if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \
defined (STM8S903) || defined (STM8AF626x)
/*!< Used with memory Models for code smaller than 64K */
#define PointerAttr NEAR
#else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */
/*!< Used with memory Models for code higher than 64K */
#define PointerAttr FAR
#endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x */
/* Uncomment the line below to enable the FLASH functions execution from RAM */
#if !defined (RAM_EXECUTION)
#define RAM_EXECUTION (1)
#endif /* RAM_EXECUTION */
#ifdef RAM_EXECUTION
#ifdef _COSMIC_
#define IN_RAM(a) a
#elif defined (_RAISONANCE_) /* __RCST7__ */
#define IN_RAM(a) a inram
#else /*_IAR_*/
#define IN_RAM(a) __ramfunc a
#endif /* _COSMIC_ */
#else
#define IN_RAM(a) a
#endif /* RAM_EXECUTION */
/*!< [31:16] STM8S Standard Peripheral Library main version V2.1.0*/
#define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version */
#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01) /*!< [23:16] sub1 version */
#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */
#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */
#define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
|(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
|(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
|(__STM8S_STDPERIPH_VERSION_RC))
/******************************************************************************/
/* Includes ------------------------------------------------------------------*/
/* Exported types and constants ----------------------------------------------*/
/** @addtogroup Exported_types
* @{
*/
/**
* IO definitions
*
* define access restrictions to peripheral registers
*/
#define __I volatile const /*!< defines 'read only' permissions */
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/*!< Signed integer types */
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed long int32_t;
/*!< Unsigned integer types */
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned long uint32_t;
/*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define U8_MAX (255)
#define S8_MAX (127)
#define S8_MIN (-128)
#define U16_MAX (65535u)
#define S16_MAX (32767)
#define S16_MIN (-32768)
#define U32_MAX (4294967295uL)
#define S32_MAX (2147483647)
#define S32_MIN (-2147483648uL)
/**
* @}
*/
/** @addtogroup MAP_FILE_Exported_Types_and_Constants
* @{
*/
/******************************************************************************/
/* IP registers structures */
/******************************************************************************/
/**
* @brief General Purpose I/Os (GPIO)
*/
typedef struct GPIO_struct
{
__IO uint8_t ODR; /*!< Output Data Register */
__IO uint8_t IDR; /*!< Input Data Register */
__IO uint8_t DDR; /*!< Data Direction Register */
__IO uint8_t CR1; /*!< Configuration Register 1 */
__IO uint8_t CR2; /*!< Configuration Register 2 */
}
GPIO_TypeDef;
/** @addtogroup GPIO_Registers_Reset_Value
* @{
*/
#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/*----------------------------------------------------------------------------*/
#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
defined(STM8S903) || defined(STM8AF626x)
/**
* @brief Analog to Digital Converter (ADC1)
*/
typedef struct ADC1_struct
{
__IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */
__IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */
__IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */
uint8_t RESERVED[12]; /*!< Reserved byte */
__IO uint8_t CSR; /*!< ADC1 control status register */
__IO uint8_t CR1; /*!< ADC1 configuration register 1 */
__IO uint8_t CR2; /*!< ADC1 configuration register 2 */
__IO uint8_t CR3; /*!< ADC1 configuration register 3 */
__IO uint8_t DRH; /*!< ADC1 Data high */
__IO uint8_t DRL; /*!< ADC1 Data low */
__IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */
__IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */
__IO uint8_t HTRH; /*!< ADC1 high threshold register High*/
__IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/
__IO uint8_t LTRH; /*!< ADC1 low threshold register high */
__IO uint8_t LTRL; /*!< ADC1 low threshold register low */
__IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */
__IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */
__IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */
__IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */
}
ADC1_TypeDef;
/** @addtogroup ADC1_Registers_Reset_Value
* @{
*/
#define ADC1_CSR_RESET_VALUE ((uint8_t)0x00)
#define ADC1_CR1_RESET_VALUE ((uint8_t)0x00)
#define ADC1_CR2_RESET_VALUE ((uint8_t)0x00)
#define ADC1_CR3_RESET_VALUE ((uint8_t)0x00)
#define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00)
#define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00)
#define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03)
#define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF)
#define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00)
#define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00)
#define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00)
#define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/** @addtogroup ADC1_Registers_Bits_Definition
* @{
*/
#define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */
#define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */
#define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
#define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */
#define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */
#define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */
#define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */
#define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */
#define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
#define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */
#define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */
#define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */
#define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */
#define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */
#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Analog to Digital Converter (ADC2)
*/
#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
typedef struct ADC2_struct
{
__IO uint8_t CSR; /*!< ADC2 control status register */
__IO uint8_t CR1; /*!< ADC2 configuration register 1 */
__IO uint8_t CR2; /*!< ADC2 configuration register 2 */
uint8_t RESERVED; /*!< Reserved byte */
__IO uint8_t DRH; /*!< ADC2 Data high */
__IO uint8_t DRL; /*!< ADC2 Data low */
__IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */
__IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */
}
ADC2_TypeDef;
/** @addtogroup ADC2_Registers_Reset_Value
* @{
*/
#define ADC2_CSR_RESET_VALUE ((uint8_t)0x00)
#define ADC2_CR1_RESET_VALUE ((uint8_t)0x00)
#define ADC2_CR2_RESET_VALUE ((uint8_t)0x00)
#define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)
#define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/** @addtogroup ADC2_Registers_Bits_Definition
* @{
*/
#define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */
#define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
#define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */
#define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */
#define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */
#define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */
#define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
#define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */
#define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */
#endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Auto Wake Up (AWU) peripheral registers.
*/
typedef struct AWU_struct
{
__IO uint8_t CSR; /*!< AWU Control status register */
__IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */
__IO uint8_t TBR; /*!< AWU Time base selection register */
}
AWU_TypeDef;
/** @addtogroup AWU_Registers_Reset_Value
* @{
*/
#define AWU_CSR_RESET_VALUE ((uint8_t)0x00)
#define AWU_APR_RESET_VALUE ((uint8_t)0x3F)
#define AWU_TBR_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/** @addtogroup AWU_Registers_Bits_Definition
* @{
*/
#define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */
#define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */
#define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */
#define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */
#define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Beeper (BEEP) peripheral registers.
*/
typedef struct BEEP_struct
{
__IO uint8_t CSR; /*!< BEEP Control status register */
}
BEEP_TypeDef;
/** @addtogroup BEEP_Registers_Reset_Value
* @{
*/
#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
/**
* @}
*/
/** @addtogroup BEEP_Registers_Bits_Definition
* @{
*/
#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
#define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */
#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Clock Controller (CLK)
*/
typedef struct CLK_struct
{
__IO uint8_t ICKR; /*!< Internal Clocks Control Register */
__IO uint8_t ECKR; /*!< External Clocks Control Register */
uint8_t RESERVED; /*!< Reserved byte */
__IO uint8_t CMSR; /*!< Clock Master Status Register */
__IO uint8_t SWR; /*!< Clock Master Switch Register */
__IO uint8_t SWCR; /*!< Switch Control Register */
__IO uint8_t CKDIVR; /*!< Clock Divider Register */
__IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */
__IO uint8_t CSSR; /*!< Clock Security System Register */
__IO uint8_t CCOR; /*!< Configurable Clock Output Register */
__IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */
uint8_t RESERVED1; /*!< Reserved byte */
__IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
__IO uint8_t SWIMCCR; /*!< SWIM clock control register */
}
CLK_TypeDef;
/** @addtogroup CLK_Registers_Reset_Value
* @{
*/
#define CLK_ICKR_RESET_VALUE ((uint8_t)0x01)
#define CLK_ECKR_RESET_VALUE ((uint8_t)0x00)
#define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)
#define CLK_SWR_RESET_VALUE ((uint8_t)0xE1)
#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)
#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)
#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)
#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
#define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/** @addtogroup CLK_Registers_Bits_Definition
* @{
*/
#define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */
#define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator ready */
#define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */
#define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */
#define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */
#define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */
#define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */
#define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */
#define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */
#define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */
#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */
#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */
#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */
#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/
#define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock prescaler */
#define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */
#define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */
#define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */
#define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */
#define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */
#define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */
#define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */
#define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */
#define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */
#define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */
#define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */
#define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */
#define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */
#define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */
#define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */
#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection */
#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */
#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */
#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */
#define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */
#define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready */
#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */
#define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable */
#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */
#define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief 16-bit timer with complementary PWM outputs (TIM1)
*/
typedef struct TIM1_struct
{
__IO uint8_t CR1; /*!< control register 1 */
__IO uint8_t CR2; /*!< control register 2 */
__IO uint8_t SMCR; /*!< Synchro mode control register */
__IO uint8_t ETR; /*!< external trigger register */
__IO uint8_t IER; /*!< interrupt enable register*/
__IO uint8_t SR1; /*!< status register 1 */
__IO uint8_t SR2; /*!< status register 2 */
__IO uint8_t EGR; /*!< event generation register */
__IO uint8_t CCMR1; /*!< CC mode register 1 */
__IO uint8_t CCMR2; /*!< CC mode register 2 */
__IO uint8_t CCMR3; /*!< CC mode register 3 */
__IO uint8_t CCMR4; /*!< CC mode register 4 */
__IO uint8_t CCER1; /*!< CC enable register 1 */
__IO uint8_t CCER2; /*!< CC enable register 2 */
__IO uint8_t CNTRH; /*!< counter high */
__IO uint8_t CNTRL; /*!< counter low */
__IO uint8_t PSCRH; /*!< prescaler high */
__IO uint8_t PSCRL; /*!< prescaler low */
__IO uint8_t ARRH; /*!< auto-reload register high */
__IO uint8_t ARRL; /*!< auto-reload register low */
__IO uint8_t RCR; /*!< Repetition Counter register */
__IO uint8_t CCR1H; /*!< capture/compare register 1 high */
__IO uint8_t CCR1L; /*!< capture/compare register 1 low */
__IO uint8_t CCR2H; /*!< capture/compare register 2 high */
__IO uint8_t CCR2L; /*!< capture/compare register 2 low */
__IO uint8_t CCR3H; /*!< capture/compare register 3 high */
__IO uint8_t CCR3L; /*!< capture/compare register 3 low */
__IO uint8_t CCR4H; /*!< capture/compare register 3 high */
__IO uint8_t CCR4L; /*!< capture/compare register 3 low */
__IO uint8_t BKR; /*!< Break Register */
__IO uint8_t DTR; /*!< dead-time register */
__IO uint8_t OISR; /*!< Output idle register */
}
TIM1_TypeDef;
/** @addtogroup TIM1_Registers_Reset_Value
* @{
*/
#define TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
#define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
#define TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
#define TIM1_IER_RESET_VALUE ((uint8_t)0x00)
#define TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
#define TIM1_SR2_RESET_VALUE ((uint8_t)0x00)
#define TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
#define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
#define TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
#define TIM1_DTR_RESET_VALUE ((uint8_t)0x00)
#define TIM1_OISR_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/** @addtogroup TIM1_Registers_Bits_Definition
* @{
*/
/* CR1*/
#define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
#define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */
#define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */
#define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
#define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
#define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
#define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
/* CR2*/
#define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */
#define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */
#define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */
#define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */
/* SMCR*/
#define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
#define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */
#define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
/*ETR*/
#define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
#define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */
#define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
#define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
/*IER*/
#define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
#define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
#define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/
#define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
#define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
#define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
#define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
#define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
/*SR1*/
#define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
#define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
#define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
#define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
#define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
#define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
#define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
#define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
/*SR2*/
#define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
#define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
#define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
#define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
/*EGR*/
#define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */
#define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */
#define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */
#define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
#define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
#define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
#define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
#define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
/*CCMR*/
#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
#define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
#define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
#define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
#define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
#define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
#define CCMR_TIxDirect_Set ((uint8_t)0x01)
/*CCER1*/
#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
#define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
#define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
#define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
#define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
/*CCER2*/
#define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */
#define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */
#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
#define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
#define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
/*CNTRH*/
#define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
/*CNTRL*/
#define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
/*PSCH*/
#define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
/*PSCL*/
#define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
/*ARR*/
#define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
#define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
/*RCR*/
#define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
/*CCR1*/
#define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
#define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
/*CCR2*/
#define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
#define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
/*CCR3*/
#define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
#define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
/*CCR4*/
#define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
#define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
/*BKR*/
#define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */
#define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
#define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */
#define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */
#define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */
#define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */
#define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */
/*DTR*/
#define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
/*OISR*/
#define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */
#define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
#define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
#define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
#define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
#define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
#define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief 16-bit timer (TIM2)
*/
typedef struct TIM2_struct
{
__IO uint8_t CR1; /*!< control register 1 */
#if defined(STM8S103) || defined(STM8S003)
uint8_t RESERVED1; /*!< Reserved register */
uint8_t RESERVED2; /*!< Reserved register */
#endif
__IO uint8_t IER; /*!< interrupt enable register */
__IO uint8_t SR1; /*!< status register 1 */
__IO uint8_t SR2; /*!< status register 2 */
__IO uint8_t EGR; /*!< event generation register */
__IO uint8_t CCMR1; /*!< CC mode register 1 */
__IO uint8_t CCMR2; /*!< CC mode register 2 */
__IO uint8_t CCMR3; /*!< CC mode register 3 */
__IO uint8_t CCER1; /*!< CC enable register 1 */
__IO uint8_t CCER2; /*!< CC enable register 2 */
__IO uint8_t CNTRH; /*!< counter high */
__IO uint8_t CNTRL; /*!< counter low */
__IO uint8_t PSCR; /*!< prescaler register */
__IO uint8_t ARRH; /*!< auto-reload register high */
__IO uint8_t ARRL; /*!< auto-reload register low */
__IO uint8_t CCR1H; /*!< capture/compare register 1 high */
__IO uint8_t CCR1L; /*!< capture/compare register 1 low */
__IO uint8_t CCR2H; /*!< capture/compare register 2 high */
__IO uint8_t CCR2L; /*!< capture/compare register 2 low */
__IO uint8_t CCR3H; /*!< capture/compare register 3 high */
__IO uint8_t CCR3L; /*!< capture/compare register 3 low */
}
TIM2_TypeDef;
/** @addtogroup TIM2_Registers_Reset_Value
* @{
*/
#define TIM2_CR1_RESET_VALUE ((uint8_t)0x00)
#define TIM2_IER_RESET_VALUE ((uint8_t)0x00)
#define TIM2_SR1_RESET_VALUE ((uint8_t)0x00)
#define TIM2_SR2_RESET_VALUE ((uint8_t)0x00)
#define TIM2_EGR_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)
#define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/** @addtogroup TIM2_Registers_Bits_Definition
* @{
*/
/*CR1*/
#define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
#define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
#define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
#define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
#define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
/*IER*/
#define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
#define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
#define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
#define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
/*SR1*/
#define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
#define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
#define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
#define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
/*SR2*/
#define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
#define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
#define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
/*EGR*/
#define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
#define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
#define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
#define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
/*CCMR*/
#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
#define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
#define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
#define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
#define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
/*CCER1*/
#define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
#define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
#define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
#define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
/*CCER2*/
#define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
#define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
/*CNTR*/
#define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
#define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
/*PSCR*/
#define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
/*ARR*/
#define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
#define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
/*CCR1*/
#define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
#define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
/*CCR2*/
#define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
#define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
/*CCR3*/
#define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
#define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief 16-bit timer (TIM3)
*/
typedef struct TIM3_struct
{
__IO uint8_t CR1; /*!< control register 1 */
__IO uint8_t IER; /*!< interrupt enable register */
__IO uint8_t SR1; /*!< status register 1 */
__IO uint8_t SR2; /*!< status register 2 */
__IO uint8_t EGR; /*!< event generation register */
__IO uint8_t CCMR1; /*!< CC mode register 1 */
__IO uint8_t CCMR2; /*!< CC mode register 2 */
__IO uint8_t CCER1; /*!< CC enable register 1 */
__IO uint8_t CNTRH; /*!< counter high */
__IO uint8_t CNTRL; /*!< counter low */
__IO uint8_t PSCR; /*!< prescaler register */
__IO uint8_t ARRH; /*!< auto-reload register high */
__IO uint8_t ARRL; /*!< auto-reload register low */
__IO uint8_t CCR1H; /*!< capture/compare register 1 high */
__IO uint8_t CCR1L; /*!< capture/compare register 1 low */
__IO uint8_t CCR2H; /*!< capture/compare register 2 high */
__IO uint8_t CCR2L; /*!< capture/compare register 2 low */
}
TIM3_TypeDef;
/** @addtogroup TIM3_Registers_Reset_Value
* @{
*/
#define TIM3_CR1_RESET_VALUE ((uint8_t)0x00)
#define TIM3_IER_RESET_VALUE ((uint8_t)0x00)
#define TIM3_SR1_RESET_VALUE ((uint8_t)0x00)
#define TIM3_SR2_RESET_VALUE ((uint8_t)0x00)
#define TIM3_EGR_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)
#define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
/**
* @}
*/
/** @addtogroup TIM3_Registers_Bits_Definition
* @{
*/
/*CR1*/
#define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
#define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
#define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
#define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
#define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
/*IER*/
#define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
#define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
#define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
/*SR1*/
#define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
#define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
#define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */