diff --git a/AsmGen/Program.cs b/AsmGen/Program.cs index 400f9f0..1d0bd54 100644 --- a/AsmGen/Program.cs +++ b/AsmGen/Program.cs @@ -37,6 +37,11 @@ static void Main(string[] args) tests.Add(new StoreDataSchedTest(4, 64, 1)); tests.Add(new MixAddJumpSchedTest(2, 64, 1)); tests.Add(new FaddSchedTest(20, 120, 1)); + tests.Add(new FcmpSchedTest(8, 120, 1)); + tests.Add(new JsCvtSched(8, 120, 1)); + tests.Add(new MixAddvJsCvtSched(8, 120, 1)); + tests.Add(new AddvSched(8, 120, 1)); + tests.Add(new FmovSched(8, 120, 1)); tests.Add(new Fadd128SchedTest(32, 80, 1)); tests.Add(new Fadd256SchedTest(4, 64, 1)); tests.Add(new Fma256SchedTest(4, 64, 1)); @@ -46,6 +51,7 @@ static void Main(string[] args) tests.Add(new BtbTest(8, BtbTest.BranchType.Unconditional)); tests.Add(new BtbTest(16, BtbTest.BranchType.Unconditional)); tests.Add(new BtbTest(32, BtbTest.BranchType.Unconditional)); + tests.Add(new BtbTest(64, BtbTest.BranchType.Unconditional)); tests.Add(new BtbTest(4, BtbTest.BranchType.Conditional)); tests.Add(new BtbTest(8, BtbTest.BranchType.Conditional)); tests.Add(new BtbTest(16, BtbTest.BranchType.Conditional)); @@ -56,6 +62,18 @@ static void Main(string[] args) tests.Add(new BranchHistoryTest()); tests.Add(new NopLoopTest(512, 1)); tests.Add(new AddLoopTest(68, 256, 1)); + /* + tests.Add(new JsCvtNsq(8, 38, 1, 40)); // a710 + tests.Add(new FaddNsq(8, 48, 1, 55)); // a710 + tests.Add(new MixAddvJsCvtNsq(8, 55, 1)); // a710 + tests.Add(new AddvNsq(8, 38, 1, 40)); // a710 + */ + tests.Add(new JsCvtNsq(8, 48, 1, 60));// x2 + tests.Add(new FaddNsq(8, 48, 1, 55)); // x2 + tests.Add(new MixAddvJsCvtNsq(8, 80, 1)); + tests.Add(new AddvNsq(8, 48, 1, 60)); + tests.Add(new StoreNsq(8, 30, 1)); // x2 + tests.Add(new LoadNsq(8, 30, 1)); // x2 List tasks = new List(); tasks.Add(Task.Run(() => GenerateCFile(tests, IUarchTest.ISA.amd64))); @@ -135,6 +153,12 @@ static void GenerateMakefile() { sb.AppendLine(isa.ToString() + ":"); sb.AppendLine($"\tgcc clammicrobench_{isa.ToString()}.c clammicrobench_{isa.ToString()}.s -o cb"); + if (isa == IUarchTest.ISA.aarch64) + { + // hack for stupid compilers that need a ton of flags to do basic things + sb.AppendLine("android:"); + sb.AppendLine("clang -march=armv8.3-a -mfpu=neon-fp-armv8 clammicrobench_aarch64.c clammicrobench_aarch64.s -o cb"); + } } sb.AppendLine("win64:"); diff --git a/AsmGen/tests/AddvNsq.cs b/AsmGen/tests/AddvNsq.cs new file mode 100644 index 0000000..522c8ad --- /dev/null +++ b/AsmGen/tests/AddvNsq.cs @@ -0,0 +1,47 @@ +using System.Text; + +namespace AsmGen +{ + public class AddvNsq : UarchTest + { + private int totalOps; + public AddvNsq(int low, int high, int step, int totalOps) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "addvnsq"; + this.Description = "ADDV, excluding possible NSQ"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + this.totalOps = totalOps; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]"; + string initInstrs = " ldr d15, [x2]"; + string[] depInstrs = new string[4]; + depInstrs[0] = " addv h1, v16.4h"; + depInstrs[1] = " addv h2, v16.4h"; + depInstrs[2] = " addv h3, v16.4h"; + depInstrs[3] = " addv h4, v16.4h"; + + string[] indepInstrs = new string[4]; + indepInstrs[0] = " addv h1, v15.4h"; + indepInstrs[1] = " addv h2, v15.4h"; + indepInstrs[2] = " addv h3, v15.4h"; + indepInstrs[3] = " addv h4, v15.4h"; + UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.totalOps, this.Counts, this.Prefix, depInstrs, indepInstrs, false, initInstrs, + postLoadInstrs: postLoadInstrs1); + } + } + } +} diff --git a/AsmGen/tests/AddvSchedTest.cs b/AsmGen/tests/AddvSchedTest.cs new file mode 100644 index 0000000..3663d9b --- /dev/null +++ b/AsmGen/tests/AddvSchedTest.cs @@ -0,0 +1,39 @@ +using System.Text; + +namespace AsmGen +{ + public class AddvSched : UarchTest + { + public AddvSched(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "addvsched"; + this.Description = "ADDV Scheduler"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr q16, [x2, w25, sxtw #0]"; + string postLoadInstrs2 = " ldr q16, [x2, w25, sxtw #0]"; + string[] unrolledInstrs = new string[4]; + unrolledInstrs[0] = " addv h1, v16.4h"; + unrolledInstrs[1] = " addv h2, v16.4h"; + unrolledInstrs[2] = " addv h3, v16.4h"; + unrolledInstrs[3] = " addv h4, v16.4h"; + UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledInstrs, unrolledInstrs, false, null, + postLoadInstrs1: postLoadInstrs1, postLoadInstrs2: postLoadInstrs2); + } + } + } +} diff --git a/AsmGen/tests/BtbTest.cs b/AsmGen/tests/BtbTest.cs index 7412e25..2325e06 100644 --- a/AsmGen/tests/BtbTest.cs +++ b/AsmGen/tests/BtbTest.cs @@ -46,7 +46,7 @@ public enum BranchType public BtbTest(int spacing, BranchType branchType, bool varyspacing = false) { this.Counts = new int[] { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 768, 1024, 1536, 2048, - 3072, 4096, 4608, 5120, 6144, 7168, 8192, 10240, 16384, 32768 }; + 3072, 4096, 4608, 5120, 6144, 7168, 8192, 10240, 12288, 14336, 16384, 32768 }; this.Prefix = "btb" + spacing + (varyspacing ? "v" : "") + branchType; this.Description = $"Branch Target Buffer, " + branchType + $" branch every {spacing} bytes " + (varyspacing ? " (varied spacing)" : ""); this.FunctionDefinitionParameters = "uint64_t iterations"; diff --git a/AsmGen/tests/FaddNsq.cs b/AsmGen/tests/FaddNsq.cs new file mode 100644 index 0000000..89d7df9 --- /dev/null +++ b/AsmGen/tests/FaddNsq.cs @@ -0,0 +1,47 @@ +using System.Text; + +namespace AsmGen +{ + public class FaddNsq : UarchTest + { + private int totalOps; + public FaddNsq(int low, int high, int step, int totalOps) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "faddnsq"; + this.Description = "FADD, excluding possible NSQ"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + this.totalOps = totalOps; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr s16, [x2, w25, uxtw #2]"; + string initInstrs = " ldr s15, [x2]"; + string[] depInstrs = new string[4]; + depInstrs[0] = " fadd s0, s0, s16"; + depInstrs[1] = " fadd s1, s1, s16"; + depInstrs[2] = " fadd s2, s2, s16"; + depInstrs[3] = " fadd s3, s3, s16"; + + string[] indepInstrs = new string[4]; + indepInstrs[0] = " fadd s17, s17, s15"; + indepInstrs[1] = " fadd s18, s18, s15"; + indepInstrs[2] = " fadd s19, s19, s15"; + indepInstrs[3] = " fadd s20, s20, s15"; + UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.totalOps, this.Counts, this.Prefix, depInstrs, indepInstrs, false, initInstrs, + postLoadInstrs: postLoadInstrs1); + } + } + } +} diff --git a/AsmGen/tests/FcmpSchedTest.cs b/AsmGen/tests/FcmpSchedTest.cs new file mode 100644 index 0000000..b689344 --- /dev/null +++ b/AsmGen/tests/FcmpSchedTest.cs @@ -0,0 +1,36 @@ +using System.Text; + +namespace AsmGen +{ + public class FcmpSchedTest : UarchTest + { + public FcmpSchedTest(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "fcmpsched"; + this.Description = "FCMP Scheduler"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string[] unrolledAdds = new string[4]; + unrolledAdds[0] = " fcmp s17, s16"; + unrolledAdds[1] = " fcmp s19, s16"; + unrolledAdds[2] = " fcmp s19, s16"; + unrolledAdds[3] = " fcmp s20, s16"; + UarchTestHelpers.GenerateArmAsmFpSchedTestFuncs(sb, this.Counts, this.Prefix, unrolledAdds, unrolledAdds); + } + } + } +} diff --git a/AsmGen/tests/FmovSched.cs b/AsmGen/tests/FmovSched.cs new file mode 100644 index 0000000..dadc643 --- /dev/null +++ b/AsmGen/tests/FmovSched.cs @@ -0,0 +1,39 @@ +using System.Text; + +namespace AsmGen +{ + public class FmovSched : UarchTest + { + public FmovSched(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "fmovsched"; + this.Description = "FMOV vec to gpr Scheduler"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]"; + string postLoadInstrs2 = " ldr d16, [x2, w25, sxtw #0]"; + string[] unrolledInstrs = new string[4]; + unrolledInstrs[0] = " fmov x15, d16"; + unrolledInstrs[1] = " fmov x14, d16"; + unrolledInstrs[2] = " fmov x13, d16"; + unrolledInstrs[3] = " fmov x12, d16"; + UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledInstrs, unrolledInstrs, false, null, + postLoadInstrs1: postLoadInstrs1, postLoadInstrs2: postLoadInstrs2); + } + } + } +} diff --git a/AsmGen/tests/JsCvtNsq.cs b/AsmGen/tests/JsCvtNsq.cs new file mode 100644 index 0000000..ed7ebd1 --- /dev/null +++ b/AsmGen/tests/JsCvtNsq.cs @@ -0,0 +1,47 @@ +using System.Text; + +namespace AsmGen +{ + public class JsCvtNsq : UarchTest + { + private int totalOps; + public JsCvtNsq(int low, int high, int step, int totalOps) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "jscvtnsq"; + this.Description = "FJCVTZS (FP Javascript Convert to Signed Fixed Point, Rounding toward Zero) Scheduler, excluding possible NSQ"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + this.totalOps = totalOps; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]"; + string initInstrs = " ldr d15, [x2]"; + string[] depInstrs = new string[4]; + depInstrs[0] = " fjcvtzs w15, d16"; + depInstrs[1] = " fjcvtzs w14, d16"; + depInstrs[2] = " fjcvtzs w13, d16"; + depInstrs[3] = " fjcvtzs w12, d16"; + + string[] indepInstrs = new string[4]; + indepInstrs[0] = " fjcvtzs w15, d15"; + indepInstrs[1] = " fjcvtzs w14, d15"; + indepInstrs[2] = " fjcvtzs w13, d15"; + indepInstrs[3] = " fjcvtzs w12, d15"; + UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.totalOps, this.Counts, this.Prefix, depInstrs, indepInstrs, false, initInstrs, + postLoadInstrs: postLoadInstrs1); + } + } + } +} diff --git a/AsmGen/tests/JsCvtSched.cs b/AsmGen/tests/JsCvtSched.cs new file mode 100644 index 0000000..8757c2f --- /dev/null +++ b/AsmGen/tests/JsCvtSched.cs @@ -0,0 +1,39 @@ +using System.Text; + +namespace AsmGen +{ + public class JsCvtSched : UarchTest + { + public JsCvtSched(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "jscvtsched"; + this.Description = "FJCVTZS (FP Javascript Convert to Signed Fixed Point, Rounding toward Zero) Scheduler"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr d16, [x2, w25, sxtw #0]"; + string postLoadInstrs2 = " ldr d16, [x2, w25, sxtw #0]"; + string[] unrolledInstrs = new string[4]; + unrolledInstrs[0] = " fjcvtzs w15, d16"; + unrolledInstrs[1] = " fjcvtzs w14, d16"; + unrolledInstrs[2] = " fjcvtzs w13, d16"; + unrolledInstrs[3] = " fjcvtzs w12, d16"; + UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledInstrs, unrolledInstrs, false, null, + postLoadInstrs1: postLoadInstrs1, postLoadInstrs2: postLoadInstrs2); + } + } + } +} diff --git a/AsmGen/tests/LoadNsq.cs b/AsmGen/tests/LoadNsq.cs new file mode 100644 index 0000000..f65c8df --- /dev/null +++ b/AsmGen/tests/LoadNsq.cs @@ -0,0 +1,40 @@ +using System.Text; + +namespace AsmGen +{ + public class LoadNsq : UarchTest + { + public LoadNsq(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "loadnsq"; + this.Description = "Load Address Scheduler, Excluding any NSQ"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string[] dep = new string[3]; + dep[0] = " ldr w15, [x2, w25, uxtw #2]"; + dep[1] = " ldr w14, [x2, w25, uxtw #2]"; + dep[2] = " ldr w13, [x2, w25, uxtw #2]"; + + string[] indep = new string[3]; + indep[0] = " ldr w12, [x2]"; + indep[1] = " ldr w11, [x2]"; + indep[2] = " ldr w10, [x2]"; + UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.Counts[this.Counts.Length - 1], this.Counts, this.Prefix, dep, indep); + } + } + } +} diff --git a/AsmGen/tests/MixAddvJsCvtNsq.cs b/AsmGen/tests/MixAddvJsCvtNsq.cs new file mode 100644 index 0000000..2e8e150 --- /dev/null +++ b/AsmGen/tests/MixAddvJsCvtNsq.cs @@ -0,0 +1,45 @@ +using System.Text; + +namespace AsmGen +{ + public class MixAddvJsCvtNsq : UarchTest + { + public MixAddvJsCvtNsq(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "mixaddvjscvtnsq"; + this.Description = "ADDV and fjcvtzs Scheduler, Excluding any NSQ"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr q16, [x2, w25, sxtw #0]\n ldr d2, [x2, w25, sxtw #0]"; + string initInstrs = " ldr q17, [x2]\n ldr d15, [x2]"; + string[] depInstrs = new string[4]; + depInstrs[0] = " addv h1, v16.4h"; + depInstrs[1] = " fjcvtzs w15, d2"; + depInstrs[2] = " addv h3, v16.4h"; + depInstrs[3] = " fjcvtzs w14, d2"; + + string[] indepInstrs = new string[4]; + indepInstrs[0] = " addv h4, v17.4h"; + indepInstrs[1] = " fjcvtzs w12, d15"; + indepInstrs[2] = " addv h5, v17.4h"; + indepInstrs[3] = " fjcvtzs w13, d15"; + UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.Counts[this.Counts.Length - 1], this.Counts, this.Prefix, depInstrs, indepInstrs, false, initInstrs: initInstrs, + postLoadInstrs: postLoadInstrs1); + } + } + } +} diff --git a/AsmGen/tests/MixAddvJsCvtSched.cs b/AsmGen/tests/MixAddvJsCvtSched.cs new file mode 100644 index 0000000..c102dc3 --- /dev/null +++ b/AsmGen/tests/MixAddvJsCvtSched.cs @@ -0,0 +1,39 @@ +using System.Text; + +namespace AsmGen +{ + public class MixAddvJsCvtSched : UarchTest + { + public MixAddvJsCvtSched(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "mixaddvjscvtsched"; + this.Description = "ADDV and fjcvtzs Scheduler"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string postLoadInstrs1 = " ldr q16, [x2, w25, sxtw #0]\n ldr d2, [x2, w25, sxtw #0]"; + string postLoadInstrs2 = " ldr q16, [x2, w26, sxtw #0]\n ldr d2, [x2, w26, sxtw #0]"; + string[] unrolledInstrs = new string[4]; + unrolledInstrs[0] = " addv h1, v16.4h"; + unrolledInstrs[1] = " fjcvtzs w15, d2"; + unrolledInstrs[2] = " addv h3, v16.4h"; + unrolledInstrs[3] = " fjcvtzs w14, d2"; + UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, unrolledInstrs, unrolledInstrs, false, null, + postLoadInstrs1: postLoadInstrs1, postLoadInstrs2: postLoadInstrs2); + } + } + } +} diff --git a/AsmGen/tests/MixLoadStoreSchedTest.cs b/AsmGen/tests/MixLoadStoreSchedTest.cs new file mode 100644 index 0000000..11950d5 --- /dev/null +++ b/AsmGen/tests/MixLoadStoreSchedTest.cs @@ -0,0 +1,58 @@ +using System.Text; + +namespace AsmGen +{ + public class MixLoadStoreSched : UarchTest + { + public MixLoadStoreSched(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "mixloadstoresched"; + this.Description = "Mixed Load/Store Address Scheduler"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.amd64) return true; + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.amd64) + { + string[] dependentLoads = new string[4]; + dependentLoads[0] = " mov %r15, (%r8, %rdi, 4)"; + dependentLoads[1] = " mov (%r8, %rdi, 2), %r14"; + dependentLoads[2] = " mov %r13, (%r8, %rdi, 4)"; + dependentLoads[3] = " mov (%r8, %rdi, 2), %r12"; + + string[] dependentLoads1 = new string[4]; + dependentLoads1[0] = " mov %r15, (%r8, %rsi, 4)"; + dependentLoads1[1] = " mov (%r8, %rsi, 4), %r14"; + dependentLoads1[2] = " mov %r13, (%r8, %rsi, 4)"; + dependentLoads1[3] = " mov (%r8, %rsi, 4), %r12"; + UarchTestHelpers.GenerateX86AsmStructureTestFuncs(sb, this.Counts, this.Prefix, dependentLoads, dependentLoads1, includePtrChasingLoads: true); + } + else if (isa == IUarchTest.ISA.aarch64) + { + string[] dependentLoads = new string[4]; + dependentLoads[0] = " str w15, [x2, w25, uxtw #2]"; + dependentLoads[1] = " ldr w14, [x1, w25, uxtw #0]"; + dependentLoads[2] = " str w13, [x2, w25, uxtw #2]"; + dependentLoads[3] = " ldr w12, [x1, w25, uxtw #0]"; + + string[] dependentLoads1 = new string[4]; + dependentLoads1[0] = " str w15, [x2, w26, uxtw #2]"; + dependentLoads1[1] = " ldr w14, [x1, w26, uxtw #0]"; + dependentLoads1[2] = " str w13, [x2, w26, uxtw #2]"; + dependentLoads1[3] = " ldr w12, [x1, w26, uxtw #0]"; + UarchTestHelpers.GenerateArmAsmStructureTestFuncs(sb, this.Counts, this.Prefix, dependentLoads, dependentLoads1, includePtrChasingLoads: true); + } + } + } +} diff --git a/AsmGen/tests/StoreNsq.cs b/AsmGen/tests/StoreNsq.cs new file mode 100644 index 0000000..3099855 --- /dev/null +++ b/AsmGen/tests/StoreNsq.cs @@ -0,0 +1,42 @@ +using System.Text; + +namespace AsmGen +{ + public class StoreNsq : UarchTest + { + public StoreNsq(int low, int high, int step) + { + this.Counts = UarchTestHelpers.GenerateCountArray(low, high, step); + this.Prefix = "storensq"; + this.Description = "Store Address Scheduler, Excluding any NSQ"; + this.FunctionDefinitionParameters = "uint64_t iterations, int *arr, float *floatArr"; + this.GetFunctionCallParameters = "structIterations, A, fpArr"; + this.DivideTimeByCount = false; + } + + public override bool SupportsIsa(IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) return true; + return false; + } + + public override void GenerateAsm(StringBuilder sb, IUarchTest.ISA isa) + { + if (isa == IUarchTest.ISA.aarch64) + { + string[] depStores = new string[4]; + depStores[0] = " str w15, [x2, w25, uxtw #2]"; + depStores[1] = " str w14, [x2, w25, uxtw #2]"; + depStores[2] = " str w13, [x2, w25, uxtw #2]"; + depStores[3] = " str w12, [x2, w25, uxtw #2]"; + + string[] indepStores = new string[4]; + indepStores[0] = " str w15, [x2, w26, uxtw #2]"; + indepStores[1] = " str w14, [x2, w26, uxtw #2]"; + indepStores[2] = " str w13, [x2, w26, uxtw #2]"; + indepStores[3] = " str w12, [x2, w26, uxtw #2]"; + UarchTestHelpers.GenerateArmAsmNsqTestFuncs(sb, this.Counts[this.Counts.Length - 1], this.Counts, this.Prefix, depStores, indepStores); + } + } + } +}