How to define a DEFINE is not documented

[rodrigomelo9]

It is the result of help read_systemverilog:

    read_systemverilog [options] [filenames]

Read SystemVerilog files using Surelog into the current design

    -noassert
        ignore assert() statements
    -debug
        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2

    -dump_ast1
        dump abstract syntax tree (before simplification)

    -dump_ast2
        dump abstract syntax tree (after simplification)

    -no_dump_ptr
        do not include hex memory addresses in dump (easier to diff dumps)

    -dump_vlog1
        dump ast as Verilog code (before simplification)

    -dump_vlog2
        dump ast as Verilog code (after simplification)

    -dump_rtlil
        dump generated RTLIL netlist

    -defer
        only read the abstract syntax tree and defer actual compilation
        to a later 'hierarchy' command. Useful in cases where the default
        parameters of modules yield invalid or not synthesizable code.
        Needs to be followed by read_systemverilog -link after reading
        all files.

    -link
        performs linking and elaboration of the files read with -defer

    -parse-only
        this parameter only applies to read_systemverilog command,
        it runs only Surelog to parse design, but doesn't load generated
        tree into Yosys.

    -formal
        enable support for SystemVerilog assertions and some Yosys extensions
        replace the implicit -D SYNTHESIS with -D FORMAL

    -parseall
        enable non-synthesizable SystemVerilog code which is discarded by default

    -Ipath
        add include path.

    -Pparameter=value
        define parameter as value.

Nothing is said about defines, but I tried -Ddefine=value (available according to Surelog docs) and it works.