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I think it would be good to mention the possibility to use GHDL as plugin for Yosys as a second, open-source way to use VHDL as RTL language. Would be some additions in the RST and the toolchain-flow.svg image.
Maybe I could create a PR if there is interest.
The text was updated successfully, but these errors were encountered:
Although GHDL is not available as a Conda package or supported in f4pga.flows yet, in #643 we added CI examples to show how to use a container along with the F4PGA Action in order to generate bitstreams for Xilinx's 7 Series devices from VHDL sources.
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Oct 3, 2022
I think it would be good to mention the possibility to use GHDL as plugin for Yosys as a second, open-source way to use VHDL as RTL language. Would be some additions in the RST and the toolchain-flow.svg image.
Maybe I could create a PR if there is interest.
The text was updated successfully, but these errors were encountered: