diff --git a/include/Surelog/Design/ModuleDefinition.h b/include/Surelog/Design/ModuleDefinition.h index c9996cd6e5..ed3c24542c 100644 --- a/include/Surelog/Design/ModuleDefinition.h +++ b/include/Surelog/Design/ModuleDefinition.h @@ -94,6 +94,10 @@ class ModuleDefinition : public DesignComponent, public ClockingBlockHolder { attributes_ = data; return true; } + std::vector* getModuleArrays() { return m_moduleArrays; } + void setModuleArrays(std::vector* modules) { + m_moduleArrays = modules; + } private: const std::string m_name; @@ -104,6 +108,7 @@ class ModuleDefinition : public DesignComponent, public ClockingBlockHolder { UHDM::udp_defn* m_udpDefn; UHDM::VectorOfattribute* attributes_ = nullptr; + std::vector* m_moduleArrays = nullptr; }; class ModuleDefinitionFactory { diff --git a/include/Surelog/Design/ModuleInstance.h b/include/Surelog/Design/ModuleInstance.h index 4e06e5e493..c6d257d8d2 100644 --- a/include/Surelog/Design/ModuleInstance.h +++ b/include/Surelog/Design/ModuleInstance.h @@ -50,10 +50,16 @@ class ModuleInstance : public ValuedComponentI { std::string_view instName, std::string_view moduleName); ~ModuleInstance() override; + typedef std::map> + ModuleArrayModuleInstancesMap; + void addSubInstance(ModuleInstance* subInstance); std::vector& getAllSubInstances() { return m_allSubInstances; } + ModuleArrayModuleInstancesMap& getModuleArrayModuleInstancesMap() { + return m_moduleArrayModuleInstancesMap; + } void setInstanceBinding(ModuleInstance* boundToInstance) { m_boundInstance = boundToInstance; } @@ -122,6 +128,7 @@ class ModuleInstance : public ValuedComponentI { ModuleInstance* m_boundInstance = nullptr; bool m_elaborated = false; std::set m_overridenParams; + ModuleArrayModuleInstancesMap m_moduleArrayModuleInstancesMap; }; class ModuleInstanceFactory { diff --git a/include/Surelog/DesignCompile/CompileHelper.h b/include/Surelog/DesignCompile/CompileHelper.h index 29e57aa11b..404dee12be 100644 --- a/include/Surelog/DesignCompile/CompileHelper.h +++ b/include/Surelog/DesignCompile/CompileHelper.h @@ -134,7 +134,8 @@ class CompileHelper final { bool compileDataDeclaration(DesignComponent* component, const FileContent* fC, NodeId id, bool interface, - CompileDesign* compileDesign, bool reduce, UHDM::VectorOfattribute* attributes); + CompileDesign* compileDesign, bool reduce, + UHDM::VectorOfattribute* attributes); // ------------------------------------------------------------------------------------------ // UHDM modeling @@ -189,11 +190,13 @@ class CompileHelper final { bool compileTask(DesignComponent* component, const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign, - ValuedComponentI* instance, bool isMethod = false, bool reduce = false); + ValuedComponentI* instance, bool isMethod = false, + bool reduce = false); bool compileFunction(DesignComponent* component, const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign, - ValuedComponentI* instance, bool isMethod = false, bool reduce = false); + ValuedComponentI* instance, bool isMethod = false, + bool reduce = false); bool compileAssertionItem(DesignComponent* component, const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign); @@ -224,7 +227,8 @@ class CompileHelper final { const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign, UHDM::any* pstmt = nullptr, - ValuedComponentI* instance = nullptr, bool reduce = false); + ValuedComponentI* instance = nullptr, + bool reduce = false); UHDM::any* compileVariable(DesignComponent* component, const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign, @@ -426,6 +430,10 @@ class CompileHelper final { void compileLetDeclaration(DesignComponent* component, const FileContent* fC, NodeId nodeId, CompileDesign* compileDesign); + void compileInstantiation(ModuleDefinition* mod, const FileContent* fC, + CompileDesign* compileDesign, NodeId id, + ValuedComponentI* instance); + /** Variable is either a bit select or a range */ bool isSelected(const FileContent* fC, NodeId id); @@ -545,8 +553,9 @@ class CompileHelper final { ValuedComponentI* instance); std::string decompileHelper(const UHDM::any* sel); - + void setUnElabMode(bool on) { m_unElabMode = on; } + private: CompileHelper(const CompileHelper&) = delete; diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp index cd01404d3b..2ea6637207 100644 --- a/src/DesignCompile/CompileHelper.cpp +++ b/src/DesignCompile/CompileHelper.cpp @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -2256,6 +2257,74 @@ std::string CompileHelper::decompileHelper(const any* sel) { return path_name; } +void CompileHelper::compileInstantiation(ModuleDefinition* mod, + const FileContent* fC, + CompileDesign* compileDesign, + NodeId id, + ValuedComponentI* instance) { + UHDM::Serializer& s = compileDesign->getSerializer(); + auto subModuleArray = mod->getModuleArrays(); + + NodeId moduleName = fC->sl_collect(id, VObjectType::slStringConst); + std::string libName = fC->getLibrary()->getName(); + std::string mname = fC->SymName(moduleName); + std::string modName = libName + "@" + mname; + + Design* design = compileDesign->getCompiler()->getDesign(); + DesignComponent* def = design->getComponentDefinition(modName); + if (def == nullptr) return; + + NodeId typespecId = fC->Child(id); + NodeId hierInstId = fC->sl_collect(id, slHierarchical_instance); + while (hierInstId) { + NodeId instId = fC->sl_collect(hierInstId, slName_of_instance); + NodeId identifierId; + std::string instName; + if (instId) { + identifierId = fC->Child(instId); + instName = fC->SymName(identifierId); + } + + NodeId unpackedDimId = fC->Sibling(identifierId); + if (unpackedDimId) { + int unpackedSize = 0; + if (std::vector* unpackedDimensions = + compileRanges(mod, fC, unpackedDimId, compileDesign, nullptr, + instance, false, unpackedSize, false)) { + UHDM::module_array* mod_array = s.MakeModule_array(); + mod_array->Ranges(unpackedDimensions); + mod_array->VpiName(instName); + mod_array->VpiFullName(modName); + fC->populateCoreMembers(identifierId, identifierId, mod_array); + + module_typespec* tps = s.MakeModule_typespec(); + tps->VpiName(fC->SymName(typespecId)); + fC->populateCoreMembers(typespecId, typespecId, tps); + mod_array->Elem_typespec(tps); + + if (subModuleArray == nullptr) { + subModuleArray = s.MakeModule_arrayVec(); + mod->setModuleArrays(subModuleArray); + } + + subModuleArray->push_back(mod_array); + } + } + // } else { + // // Simple instance + // UHDM::module* m = s.MakeModule(); + // m->VpiName(instName); + // m->VpiDefName(modName); + // m->VpiDefLineNo(fC->Line(mod->getNodeIds()[0])); + // m->VpiDefFile(fC->getSymbolTable()->getSymbol( + // fC->GetDefinitionFile(mod->getNodeIds()[0]))); + // fC->populateCoreMembers(identifierId, identifierId, m); + // m->Instance(m); + + hierInstId = fC->Sibling(hierInstId); + } +} + bool CompileHelper::compileInitialBlock(DesignComponent* component, const FileContent* fC, NodeId initial_construct, diff --git a/src/DesignCompile/CompileModule.cpp b/src/DesignCompile/CompileModule.cpp index 2dff409b50..341d4166d2 100644 --- a/src/DesignCompile/CompileModule.cpp +++ b/src/DesignCompile/CompileModule.cpp @@ -768,7 +768,6 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) { case VObjectType::slN_output_gate_instance: case VObjectType::slUdp_instance: case VObjectType::slUdp_instantiation: - case VObjectType::slModule_instantiation: case VObjectType::slInterface_instantiation: case VObjectType::slGate_instantiation: case VObjectType::slConditional_generate_construct: @@ -783,6 +782,14 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) { m_module->addObject(type, fnid); break; } + case VObjectType::slModule_instantiation: { + if (collectType != CollectType::OTHER) break; + m_helper.compileInstantiation(m_module, fC, m_compileDesign, id, + m_instance); + FileCNodeId fnid(fC, id); + m_module->addObject(type, fnid); + break; + } case VObjectType::slInitial_construct: if (collectType != CollectType::OTHER) break; m_helper.compileInitialBlock(m_module, fC, id, m_compileDesign); diff --git a/src/DesignCompile/DesignElaboration.cpp b/src/DesignCompile/DesignElaboration.cpp index 77f1315623..ffd5e315f2 100644 --- a/src/DesignCompile/DesignElaboration.cpp +++ b/src/DesignCompile/DesignElaboration.cpp @@ -46,17 +46,8 @@ // UHDM #include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include +#include #include #include @@ -1442,10 +1433,6 @@ void DesignElaboration::elaborateInstance_( paramOverride = tmpId; } - std::vector from; - std::vector to; - std::vector index; - VObjectTypeUnorderedSet insttypes = { VObjectType::slHierarchical_instance, VObjectType::slN_input_gate_instance, @@ -1526,10 +1513,13 @@ void DesignElaboration::elaborateInstance_( } NodeId unpackedDimId; - if (identifierId) unpackedDimId = fC->Sibling(identifierId); if (unpackedDimId) { + std::vector from; + std::vector to; + std::vector index; + // Vector instances while (unpackedDimId) { if (fC->Type(unpackedDimId) == slUnpacked_dimension) { @@ -1563,9 +1553,39 @@ void DesignElaboration::elaborateInstance_( } unpackedDimId = fC->Sibling(unpackedDimId); } + + std::vector localSubInstances; recurseInstanceLoop_(from, to, index, 0, def, fC, subInstanceId, paramOverride, factory, parent, subConfig, - instName, modName, allSubInstances); + instName, modName, localSubInstances); + allSubInstances.insert(allSubInstances.end(), + localSubInstances.begin(), + localSubInstances.end()); + + // Create module array + if (type == VObjectType::slModule_instantiation) { + int unpackedSize = 0; + unpackedDimId = fC->Sibling(identifierId); + if (std::vector* unpackedDimensions = + m_helper.compileRanges(def, fC, unpackedDimId, + m_compileDesign, nullptr, parent, + false, unpackedSize, false)) { + UHDM::Serializer& s = m_compileDesign->getSerializer(); + UHDM::module_array* mod_array = s.MakeModule_array(); + mod_array->Ranges(unpackedDimensions); + mod_array->VpiName(instName); + mod_array->VpiFullName(modName); + fC->populateCoreMembers(identifierId, identifierId, mod_array); + + UHDM::module_typespec* tps = s.MakeModule_typespec(); + NodeId typespecId = fC->Child(subInstanceId); + tps->VpiName(fC->SymName(typespecId)); + fC->populateCoreMembers(typespecId, typespecId, tps); + mod_array->Elem_typespec(tps); + parent->getModuleArrayModuleInstancesMap().emplace( + mod_array, localSubInstances); + } + } } else { // Simple instance if (reuseInstance) { diff --git a/src/DesignCompile/NetlistElaboration.cpp b/src/DesignCompile/NetlistElaboration.cpp index ff88d5d40f..691b29f799 100644 --- a/src/DesignCompile/NetlistElaboration.cpp +++ b/src/DesignCompile/NetlistElaboration.cpp @@ -2020,6 +2020,8 @@ bool NetlistElaboration::elab_ports_nets_( array_int->Ranges(unpackedDimensions); array_int->VpiName(signame); array_int->VpiSize(unpackedSize); + fC->populateCoreMembers(sig->getNodeId(), sig->getNodeId(), + array_int); auto array = netlist->interface_arrays(); if (array == nullptr) { diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp index 67e4e3f3f9..d50f3a6f26 100644 --- a/src/DesignCompile/UhdmWriter.cpp +++ b/src/DesignCompile/UhdmWriter.cpp @@ -1216,6 +1216,53 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module* m, Serializer& s, ps->VpiParent(m); } } + // Module Instantiation + if (VectorOfmodule_array* subModuleArrays = mod->getModuleArrays()) { + m->Module_arrays(subModuleArrays); + for (auto subModArr : *subModuleArrays) { + subModArr->VpiParent(m); + } + } + // Interface instantiation + const std::vector& signals = mod->getSignals(); + if (!signals.empty()) { + VectorOfinterface_array* subInterfaceArrays = s.MakeInterface_arrayVec(); + m->Interface_arrays(subInterfaceArrays); + for (Signal* sig : signals) { + NodeId unpackedDimension = sig->getUnpackedDimension(); + if (unpackedDimension && sig->getInterfaceDef()) { + int unpackedSize = 0; + const FileContent* fC = sig->getFileContent(); + if (std::vector* unpackedDimensions = + m_helper.compileRanges(mod, fC, unpackedDimension, + m_compileDesign, nullptr, instance, + false, unpackedSize, false)) { + NodeId id = sig->getNodeId(); + const std::string typeName = sig->getInterfaceTypeName(); + interface_array* smarray = s.MakeInterface_array(); + smarray->Ranges(unpackedDimensions); + if (fC->Type(id) == slStringConst) { + smarray->VpiName(sig->getName()); + } + smarray->VpiFullName(typeName); + smarray->VpiParent(m); + fC->populateCoreMembers(id, id, smarray); + + NodeId typespecStart = sig->getInterfaceTypeNameId(); + NodeId typespecEnd = typespecStart; + while (fC->Sibling(typespecEnd)) { + typespecEnd = fC->Sibling(typespecEnd); + } + interface_typespec* tps = s.MakeInterface_typespec(); + tps->VpiName(typeName); + fC->populateCoreMembers(typespecStart, typespecEnd, tps); + smarray->Elem_typespec(tps); + + subInterfaceArrays->push_back(smarray); + } + } + } + } } void UhdmWriter::writeInterface(ModuleDefinition* mod, interface* m, @@ -3190,6 +3237,7 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, } } } + std::map tempInstanceMap; for (unsigned int i = 0; i < instance->getNbChildren(); i++) { ModuleInstance* child = instance->getChildren(i); DesignComponent* childDef = child->getDefinition(); @@ -3199,6 +3247,7 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, if (insttype == VObjectType::slModule_instantiation) { if (subModules == nullptr) subModules = s.MakeModuleVec(); module* sm = s.MakeModule(); + tempInstanceMap.emplace(child, sm); if (childDef && !childDef->getFileContents().empty() && compileDesign->getCompiler()->isLibraryFile( childDef->getFileContents()[0]->getSymbolId())) { @@ -3441,6 +3490,27 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance, instanceMap, exprBuilder); } } + + if (m->UhdmType() == uhdmmodule) { + const auto& moduleArrayModuleInstancesMap = + instance->getModuleArrayModuleInstancesMap(); + if (!moduleArrayModuleInstancesMap.empty()) { + ((module*)m)->Module_arrays(s.MakeModule_arrayVec()); + for (auto [modArray, modInstances] : moduleArrayModuleInstancesMap) { + if (!modInstances.empty()) { + modArray->Modules(s.MakeModuleVec()); + modArray->VpiParent(m); + ((module*)m)->Module_arrays()->push_back(modArray); + for (ModuleInstance* modInst : modInstances) { + auto it = tempInstanceMap.find(modInst); + if (it != tempInstanceMap.end()) { + modArray->Modules()->push_back(it->second); + } + } + } + } + } + } } vpiHandle UhdmWriter::write(const std::string& uhdmFile) { diff --git a/tests/ArrayInst/ArrayInst.log b/tests/ArrayInst/ArrayInst.log index 3296f45079..16414f6a2f 100644 --- a/tests/ArrayInst/ArrayInst.log +++ b/tests/ArrayInst/ArrayInst.log @@ -3,14 +3,14 @@ LIB: work FILE: dut.sv n<> u<0> t<_INVALID_> f<0> l<0:0> -n<> u<1> t p<64> s<63> l<1:1> el<1:0> +n<> u<1> t p<89> s<88> l<1:1> el<1:0> n<> u<2> t p<6> s<3> l<1:1> el<1:7> n u<3> t p<6> s<5> l<1:8> el<1:10> n<> u<4> t p<5> l<1:11> el<1:11> n<> u<5> t p<6> c<4> l<1:10> el<1:12> n<> u<6> t p<7> c<2> l<1:1> el<1:13> n<> u<7> t p<8> c<6> l<1:1> el<2:10> -n<> u<8> t p<63> c<7> s<35> l<1:1> el<2:10> +n<> u<8> t p<88> c<7> s<35> l<1:1> el<2:10> n<> u<9> t p<13> s<10> l<4:1> el<4:7> n u<10> t p<13> s<12> l<4:8> el<4:12> n<> u<11> t p<12> l<4:14> el<4:14> @@ -37,36 +37,61 @@ n<> u<31> t p<32> c<30> l<5:3> el<5:15> n<> u<32> t p<33> c<31> l<5:3> el<5:15> n<> u<33> t p<34> c<32> l<5:3> el<5:15> n<> u<34> t p<35> c<13> l<4:1> el<6:10> -n<> u<35> t p<63> c<34> s<62> l<4:1> el<6:10> +n<> u<35> t p<88> c<34> s<87> l<4:1> el<6:10> n<> u<36> t p<40> s<37> l<8:1> el<8:7> n u<37> t p<40> s<39> l<8:8> el<8:11> n<> u<38> t p<39> l<8:12> el<8:12> n<> u<39> t p<40> c<38> l<8:11> el<8:13> -n<> u<40> t p<61> c<36> s<60> l<8:1> el<8:14> -n u<41> t p<57> s<56> l<9:3> el<9:7> -n u<42> t p<53> s<52> l<9:8> el<9:22> -n<3> u<43> t p<44> l<9:23> el<9:24> -n<> u<44> t p<45> c<43> l<9:23> el<9:24> -n<> u<45> t p<46> c<44> l<9:23> el<9:24> -n<> u<46> t p<51> c<45> s<50> l<9:23> el<9:24> -n<0> u<47> t p<48> l<9:25> el<9:26> -n<> u<48> t p<49> c<47> l<9:25> el<9:26> -n<> u<49> t p<50> c<48> l<9:25> el<9:26> -n<> u<50> t p<51> c<49> l<9:25> el<9:26> -n<> u<51> t p<52> c<46> l<9:23> el<9:26> -n<> u<52> t p<53> c<51> l<9:22> el<9:27> -n<> u<53> t p<56> c<42> s<55> l<9:8> el<9:27> +n<> u<40> t p<86> c<36> s<85> l<8:1> el<8:14> +n u<41> t p<82> s<56> l<9:3> el<9:7> +n u<42> t p<53> s<52> l<9:8> el<9:23> +n<1> u<43> t p<44> l<9:24> el<9:25> +n<> u<44> t p<45> c<43> l<9:24> el<9:25> +n<> u<45> t p<46> c<44> l<9:24> el<9:25> +n<> u<46> t p<51> c<45> s<50> l<9:24> el<9:25> +n<0> u<47> t p<48> l<9:26> el<9:27> +n<> u<48> t p<49> c<47> l<9:26> el<9:27> +n<> u<49> t p<50> c<48> l<9:26> el<9:27> +n<> u<50> t p<51> c<49> l<9:26> el<9:27> +n<> u<51> t p<52> c<46> l<9:24> el<9:27> +n<> u<52> t p<53> c<51> l<9:23> el<9:28> +n<> u<53> t p<56> c<42> s<55> l<9:8> el<9:28> n<> u<54> t p<55> l<9:29> el<9:29> n<> u<55> t p<56> c<54> l<9:29> el<9:29> -n<> u<56> t p<57> c<53> l<9:8> el<9:30> -n<> u<57> t p<58> c<41> l<9:3> el<9:31> -n<> u<58> t p<59> c<57> l<9:3> el<9:31> -n<> u<59> t p<60> c<58> l<9:3> el<9:31> -n<> u<60> t p<61> c<59> l<9:3> el<9:31> -n<> u<61> t p<62> c<40> l<8:1> el<10:10> -n<> u<62> t p<63> c<61> l<8:1> el<10:10> -n<> u<63> t p<64> c<8> l<1:1> el<10:10> -n<> u<64> t c<1> l<1:1> el<11:1> +n<> u<56> t p<82> c<53> s<81> l<9:8> el<9:30> +n u<57> t p<78> s<67> l<9:32> el<9:47> +n<2> u<58> t p<59> l<9:48> el<9:49> +n<> u<59> t p<60> c<58> l<9:48> el<9:49> +n<> u<60> t p<61> c<59> l<9:48> el<9:49> +n<> u<61> t p<66> c<60> s<65> l<9:48> el<9:49> +n<0> u<62> t p<63> l<9:50> el<9:51> +n<> u<63> t p<64> c<62> l<9:50> el<9:51> +n<> u<64> t p<65> c<63> l<9:50> el<9:51> +n<> u<65> t p<66> c<64> l<9:50> el<9:51> +n<> u<66> t p<67> c<61> l<9:48> el<9:51> +n<> u<67> t p<78> c<66> s<77> l<9:47> el<9:52> +n<1> u<68> t p<69> l<9:53> el<9:54> +n<> u<69> t p<70> c<68> l<9:53> el<9:54> +n<> u<70> t p<71> c<69> l<9:53> el<9:54> +n<> u<71> t p<76> c<70> s<75> l<9:53> el<9:54> +n<0> u<72> t p<73> l<9:55> el<9:56> +n<> u<73> t p<74> c<72> l<9:55> el<9:56> +n<> u<74> t p<75> c<73> l<9:55> el<9:56> +n<> u<75> t p<76> c<74> l<9:55> el<9:56> +n<> u<76> t p<77> c<71> l<9:53> el<9:56> +n<> u<77> t p<78> c<76> l<9:52> el<9:57> +n<> u<78> t p<81> c<57> s<80> l<9:32> el<9:57> +n<> u<79> t p<80> l<9:58> el<9:58> +n<> u<80> t p<81> c<79> l<9:58> el<9:58> +n<> u<81> t p<82> c<78> l<9:32> el<9:59> +n<> u<82> t p<83> c<41> l<9:3> el<9:60> +n<> u<83> t p<84> c<82> l<9:3> el<9:60> +n<> u<84> t p<85> c<83> l<9:3> el<9:60> +n<> u<85> t p<86> c<84> l<9:3> el<9:60> +n<> u<86> t p<87> c<40> l<8:1> el<10:10> +n<> u<87> t p<88> c<86> l<8:1> el<10:10> +n<> u<88> t p<89> c<8> l<1:1> el<10:10> +n<> u<89> t c<1> l<1:1> el<11:1> [WRN:PA0205] dut.sv:1:1: No timescale set for "qq". [WRN:PA0205] dut.sv:4:1: No timescale set for "flop". @@ -89,25 +114,29 @@ n<> u<64> t c<1> l<1:1> el<11:1> [NTE:EL0509] Max instance depth: 3. -[NTE:EL0510] Nb instances: 13. +[NTE:EL0510] Nb instances: 25. -[NTE:EL0511] Nb leaf instances: 8. +[NTE:EL0511] Nb leaf instances: 16. [INF:UH0706] Creating UHDM Model... === UHDM Object Stats Begin (Non-Elaborated Model) === -constant 34 +constant 100 design 1 -module 29 -range 12 +module 53 +module_array 13 +module_typespec 13 +range 39 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -constant 34 +constant 100 design 1 -module 29 -range 12 +module 53 +module_array 13 +module_typespec 13 +range 39 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ../../build/regression/ArrayInst/slpp_all/surelog.uhdm ... @@ -127,6 +156,33 @@ design: (work@top) \_design: (work@top) |vpiFullName:work@flop |vpiDefName:work@flop + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@flop), file:dut.sv, line:4:1, endln:6:10 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq |uhdmallModules: \_module: work@qq (work@qq), file:dut.sv, line:1:1, endln:2:10 |vpiParent: @@ -139,6 +195,78 @@ design: (work@top) \_design: (work@top) |vpiFullName:work@top |vpiDefName:work@top + |vpiModuleArray: + \_module_array: (work@flop), line:9:8, endln:9:23 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances1 + |vpiFullName:work@flop + |vpiRange: + \_range: , line:9:23, endln:9:28 + |vpiLeftRange: + \_constant: , line:9:24, endln:9:25 + |vpiParent: + \_range: , line:9:23, endln:9:28 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:26, endln:9:27 + |vpiParent: + \_range: , line:9:23, endln:9:28 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_module_typespec: (flop), line:9:3, endln:9:7 + |vpiName:flop + |vpiModuleArray: + \_module_array: (work@flop), line:9:32, endln:9:47 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances2 + |vpiFullName:work@flop + |vpiRange: + \_range: , line:9:47, endln:9:52 + |vpiLeftRange: + \_constant: , line:9:48, endln:9:49 + |vpiParent: + \_range: , line:9:47, endln:9:52 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:50, endln:9:51 + |vpiParent: + \_range: , line:9:47, endln:9:52 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRange: + \_range: , line:9:52, endln:9:57 + |vpiLeftRange: + \_constant: , line:9:53, endln:9:54 + |vpiParent: + \_range: , line:9:52, endln:9:57 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:55, endln:9:56 + |vpiParent: + \_range: , line:9:52, endln:9:57 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_module_typespec: (flop), line:9:3, endln:9:7 + |vpiName:flop |uhdmtopModules: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 |vpiName:work@top @@ -146,137 +274,605 @@ design: (work@top) |vpiTop:1 |vpiTopModule:1 |vpiModule: - \_module: work@flop (work@top.flop_instances[0]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[0]), file:dut.sv, line:9:3, endln:9:60 |vpiParent: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 - |vpiName:flop_instances[0] - |vpiFullName:work@top.flop_instances[0] + |vpiName:flop_instances1[0] + |vpiFullName:work@top.flop_instances1[0] |vpiDefName:work@flop |vpiDefFile:dut.sv |vpiDefLineNo:4 |vpiInstance: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 |vpiModule: - \_module: work@qq (work@top.flop_instances[0].q[0]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances1[0].q[0]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[0]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[0]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[0] - |vpiFullName:work@top.flop_instances[0].q[0] + |vpiFullName:work@top.flop_instances1[0].q[0] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[0]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[0]), file:dut.sv, line:9:3, endln:9:60 |vpiModule: - \_module: work@qq (work@top.flop_instances[0].q[1]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances1[0].q[1]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[0]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[0]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[1] - |vpiFullName:work@top.flop_instances[0].q[1] + |vpiFullName:work@top.flop_instances1[0].q[1] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[0]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances1[0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances1[0].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances1[0].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq |vpiModule: - \_module: work@flop (work@top.flop_instances[1]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[1]), file:dut.sv, line:9:3, endln:9:60 |vpiParent: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 - |vpiName:flop_instances[1] - |vpiFullName:work@top.flop_instances[1] + |vpiName:flop_instances1[1] + |vpiFullName:work@top.flop_instances1[1] |vpiDefName:work@flop |vpiDefFile:dut.sv |vpiDefLineNo:4 |vpiInstance: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 |vpiModule: - \_module: work@qq (work@top.flop_instances[1].q[0]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances1[1].q[0]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[1]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[1]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[0] - |vpiFullName:work@top.flop_instances[1].q[0] + |vpiFullName:work@top.flop_instances1[1].q[0] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[1]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[1]), file:dut.sv, line:9:3, endln:9:60 |vpiModule: - \_module: work@qq (work@top.flop_instances[1].q[1]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances1[1].q[1]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[1]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[1]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[1] - |vpiFullName:work@top.flop_instances[1].q[1] + |vpiFullName:work@top.flop_instances1[1].q[1] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[1]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances1[1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances1[1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances1[1].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances1[1].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq |vpiModule: - \_module: work@flop (work@top.flop_instances[2]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][0]), file:dut.sv, line:9:3, endln:9:60 |vpiParent: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 - |vpiName:flop_instances[2] - |vpiFullName:work@top.flop_instances[2] + |vpiName:flop_instances2[0][0] + |vpiFullName:work@top.flop_instances2[0][0] |vpiDefName:work@flop |vpiDefFile:dut.sv |vpiDefLineNo:4 |vpiInstance: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 |vpiModule: - \_module: work@qq (work@top.flop_instances[2].q[0]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances2[0][0].q[0]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[2]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][0]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[0] - |vpiFullName:work@top.flop_instances[2].q[0] + |vpiFullName:work@top.flop_instances2[0][0].q[0] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[2]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][0]), file:dut.sv, line:9:3, endln:9:60 |vpiModule: - \_module: work@qq (work@top.flop_instances[2].q[1]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances2[0][0].q[1]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[2]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][0]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[1] - |vpiFullName:work@top.flop_instances[2].q[1] + |vpiFullName:work@top.flop_instances2[0][0].q[1] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[2]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[0][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[0][0].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[0][0].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq |vpiModule: - \_module: work@flop (work@top.flop_instances[3]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][1]), file:dut.sv, line:9:3, endln:9:60 |vpiParent: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 - |vpiName:flop_instances[3] - |vpiFullName:work@top.flop_instances[3] + |vpiName:flop_instances2[0][1] + |vpiFullName:work@top.flop_instances2[0][1] |vpiDefName:work@flop |vpiDefFile:dut.sv |vpiDefLineNo:4 |vpiInstance: \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 |vpiModule: - \_module: work@qq (work@top.flop_instances[3].q[0]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances2[0][1].q[0]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[3]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][1]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[0] - |vpiFullName:work@top.flop_instances[3].q[0] + |vpiFullName:work@top.flop_instances2[0][1].q[0] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[3]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][1]), file:dut.sv, line:9:3, endln:9:60 |vpiModule: - \_module: work@qq (work@top.flop_instances[3].q[1]), file:dut.sv, line:5:3, endln:5:15 + \_module: work@qq (work@top.flop_instances2[0][1].q[1]), file:dut.sv, line:5:3, endln:5:15 |vpiParent: - \_module: work@flop (work@top.flop_instances[3]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][1]), file:dut.sv, line:9:3, endln:9:60 |vpiName:q[1] - |vpiFullName:work@top.flop_instances[3].q[1] + |vpiFullName:work@top.flop_instances2[0][1].q[1] |vpiDefName:work@qq |vpiDefFile:dut.sv |vpiDefLineNo:1 |vpiInstance: - \_module: work@flop (work@top.flop_instances[3]), file:dut.sv, line:9:3, endln:9:31 + \_module: work@flop (work@top.flop_instances2[0][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[0][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[0][1].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[0][1].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq + |vpiModule: + \_module: work@flop (work@top.flop_instances2[1][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances2[1][0] + |vpiFullName:work@top.flop_instances2[1][0] + |vpiDefName:work@flop + |vpiDefFile:dut.sv + |vpiDefLineNo:4 + |vpiInstance: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][0].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[1][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[0] + |vpiFullName:work@top.flop_instances2[1][0].q[0] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[1][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][0].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[1][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[1] + |vpiFullName:work@top.flop_instances2[1][0].q[1] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[1][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[1][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][0].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][0].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq + |vpiModule: + \_module: work@flop (work@top.flop_instances2[1][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances2[1][1] + |vpiFullName:work@top.flop_instances2[1][1] + |vpiDefName:work@flop + |vpiDefFile:dut.sv + |vpiDefLineNo:4 + |vpiInstance: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][1].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[1][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[0] + |vpiFullName:work@top.flop_instances2[1][1].q[0] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[1][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][1].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[1][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[1] + |vpiFullName:work@top.flop_instances2[1][1].q[1] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[1][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[1][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][1].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[1][1].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq + |vpiModule: + \_module: work@flop (work@top.flop_instances2[2][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances2[2][0] + |vpiFullName:work@top.flop_instances2[2][0] + |vpiDefName:work@flop + |vpiDefFile:dut.sv + |vpiDefLineNo:4 + |vpiInstance: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][0].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[2][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[0] + |vpiFullName:work@top.flop_instances2[2][0].q[0] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[2][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][0].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[2][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[1] + |vpiFullName:work@top.flop_instances2[2][0].q[1] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[2][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[2][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][0].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][0].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq + |vpiModule: + \_module: work@flop (work@top.flop_instances2[2][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances2[2][1] + |vpiFullName:work@top.flop_instances2[2][1] + |vpiDefName:work@flop + |vpiDefFile:dut.sv + |vpiDefLineNo:4 + |vpiInstance: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][1].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[2][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[0] + |vpiFullName:work@top.flop_instances2[2][1].q[0] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[2][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][1].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[2][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q[1] + |vpiFullName:work@top.flop_instances2[2][1].q[1] + |vpiDefName:work@qq + |vpiDefFile:dut.sv + |vpiDefLineNo:1 + |vpiInstance: + \_module: work@flop (work@top.flop_instances2[2][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModuleArray: + \_module_array: (work@qq), line:5:6, endln:5:7 + |vpiParent: + \_module: work@flop (work@top.flop_instances2[2][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiName:q + |vpiFullName:work@qq + |vpiRange: + \_range: , line:5:7, endln:5:12 + |vpiLeftRange: + \_constant: , line:5:8, endln:5:9 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:5:10, endln:5:11 + |vpiParent: + \_range: , line:5:7, endln:5:12 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][1].q[0]), file:dut.sv, line:5:3, endln:5:15 + |vpiModule: + \_module: work@qq (work@top.flop_instances2[2][1].q[1]), file:dut.sv, line:5:3, endln:5:15 + |vpiElemTypespec: + \_module_typespec: (qq), line:5:3, endln:5:5 + |vpiName:qq + |vpiModuleArray: + \_module_array: (work@flop), line:9:8, endln:9:23 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances1 + |vpiFullName:work@flop + |vpiRange: + \_range: , line:9:23, endln:9:28 + |vpiLeftRange: + \_constant: , line:9:24, endln:9:25 + |vpiParent: + \_range: , line:9:23, endln:9:28 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:26, endln:9:27 + |vpiParent: + \_range: , line:9:23, endln:9:28 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@flop (work@top.flop_instances1[0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@flop (work@top.flop_instances1[1]), file:dut.sv, line:9:3, endln:9:60 + |vpiElemTypespec: + \_module_typespec: (flop), line:9:3, endln:9:7 + |vpiName:flop + |vpiModuleArray: + \_module_array: (work@flop), line:9:32, endln:9:47 + |vpiParent: + \_module: work@top (work@top), file:dut.sv, line:8:1, endln:10:10 + |vpiName:flop_instances2 + |vpiFullName:work@flop + |vpiRange: + \_range: , line:9:47, endln:9:52 + |vpiLeftRange: + \_constant: , line:9:48, endln:9:49 + |vpiParent: + \_range: , line:9:47, endln:9:52 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:50, endln:9:51 + |vpiParent: + \_range: , line:9:47, endln:9:52 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRange: + \_range: , line:9:52, endln:9:57 + |vpiLeftRange: + \_constant: , line:9:53, endln:9:54 + |vpiParent: + \_range: , line:9:52, endln:9:57 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:9:55, endln:9:56 + |vpiParent: + \_range: , line:9:52, endln:9:57 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@flop (work@top.flop_instances2[0][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@flop (work@top.flop_instances2[0][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@flop (work@top.flop_instances2[1][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@flop (work@top.flop_instances2[1][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@flop (work@top.flop_instances2[2][0]), file:dut.sv, line:9:3, endln:9:60 + |vpiModule: + \_module: work@flop (work@top.flop_instances2[2][1]), file:dut.sv, line:9:3, endln:9:60 + |vpiElemTypespec: + \_module_typespec: (flop), line:9:3, endln:9:7 + |vpiName:flop =================== [ FATAL] : 0 [ SYNTAX] : 0 diff --git a/tests/ArrayInst/dut.sv b/tests/ArrayInst/dut.sv index 94869d69a4..51bcfa46cb 100644 --- a/tests/ArrayInst/dut.sv +++ b/tests/ArrayInst/dut.sv @@ -6,5 +6,5 @@ module flop (); endmodule module top(); - flop flop_instances[3:0] (); + flop flop_instances1[1:0](), flop_instances2[2:0][1:0](); endmodule diff --git a/tests/LibraryIntercon/LibraryIntercon.log b/tests/LibraryIntercon/LibraryIntercon.log index 298a14fae0..428d65d5f6 100644 --- a/tests/LibraryIntercon/LibraryIntercon.log +++ b/tests/LibraryIntercon/LibraryIntercon.log @@ -13,9 +13,9 @@ LIB: realLib ${SURELOG_DIR}/tests/LibraryIntercon/driver.svr LIB: logicLib + ${SURELOG_DIR}/tests/LibraryIntercon/top.sv ${SURELOG_DIR}/tests/LibraryIntercon/driver.sv ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv - ${SURELOG_DIR}/tests/LibraryIntercon/top.sv [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". @@ -26,30 +26,30 @@ LIB: logicLib [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". + [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". - [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". + [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv". - [WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg". -[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp". - [WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top". +[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp". + [INF:CP0300] Compilation... [INF:CP0301] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: Compile package "NetsPkg". @@ -164,7 +164,7 @@ bit_select 10 class_defn 8 class_typespec 4 class_var 3 -constant 154 +constant 160 cont_assign 2 delay_control 3 design 1 @@ -185,12 +185,14 @@ logic_net 22 logic_typespec 23 logic_var 10 module 28 +module_array 3 +module_typespec 3 operation 11 package 5 param_assign 18 parameter 18 port 24 -range 42 +range 45 real_typespec 14 real_var 8 ref_obj 75 diff --git a/tests/ModPortArrayBind/ModPortArrayBind.log b/tests/ModPortArrayBind/ModPortArrayBind.log index 1d2d8bdacd..d7e21cecc8 100644 --- a/tests/ModPortArrayBind/ModPortArrayBind.log +++ b/tests/ModPortArrayBind/ModPortArrayBind.log @@ -189,7 +189,7 @@ n<> u<155> t c<1> l<2:1> el<30:1> === UHDM Object Stats Begin (Non-Elaborated Model) === array_typespec 1 bit_select 4 -constant 23 +constant 25 cont_assign 2 design 1 gen_scope 4 @@ -197,27 +197,27 @@ gen_scope_array 4 hier_path 2 int_typespec 4 interface 3 -interface_array 1 -interface_typespec 6 +interface_array 2 +interface_typespec 7 io_decl 3 logic_net 2 logic_typespec 2 logic_var 2 modport 3 module 5 -operation 7 +operation 8 param_assign 2 parameter 4 port 2 -range 2 -ref_obj 13 +range 3 +ref_obj 14 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === array_typespec 1 bit_select 8 -constant 23 +constant 25 cont_assign 4 design 1 gen_scope 6 @@ -225,20 +225,20 @@ gen_scope_array 6 hier_path 4 int_typespec 4 interface 3 -interface_array 1 -interface_typespec 6 +interface_array 2 +interface_typespec 7 io_decl 3 logic_net 2 logic_typespec 2 logic_var 2 modport 3 module 5 -operation 9 +operation 10 param_assign 2 parameter 4 port 3 -range 2 -ref_obj 24 +range 3 +ref_obj 25 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ../../build/regression/ModPortArrayBind/slpp_all/surelog.uhdm ... @@ -360,6 +360,43 @@ design: (work@r5p_bus_dec) \_interface_typespec: (r5p_bus_if), line:15:3, endln:15:13 |vpiName:man |vpiIsModPort:1 + |vpiInterfaceArray: + \_interface_array: (r5p_bus_if.man), line:15:18, endln:15:19 + |vpiParent: + \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:dut.sv, line:12:1, endln:29:10 + |vpiName:m + |vpiFullName:r5p_bus_if.man + |vpiRange: + \_range: , line:15:19, endln:15:27 + |vpiLeftRange: + \_operation: , line:15:20, endln:15:24 + |vpiParent: + \_range: , line:15:19, endln:15:27 + |vpiOpType:11 + |vpiOperand: + \_ref_obj: (BN), line:15:20, endln:15:22 + |vpiParent: + \_operation: , line:15:20, endln:15:24 + |vpiName:BN + |vpiOperand: + \_constant: , line:15:23, endln:15:24 + |vpiParent: + \_operation: , line:15:20, endln:15:24 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:15:25, endln:15:26 + |vpiParent: + \_range: , line:15:19, endln:15:27 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_interface_typespec: (r5p_bus_if.man), line:15:3, endln:15:17 + |vpiName:r5p_bus_if.man |uhdmtopModules: \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:dut.sv, line:12:1, endln:29:10 |vpiName:work@r5p_bus_dec @@ -403,7 +440,7 @@ design: (work@r5p_bus_dec) \_port: (m), line:15:18, endln:15:19 |vpiFullName:work@r5p_bus_dec.m |vpiActual: - \_interface_array: (work@r5p_bus_dec.m) + \_interface_array: (work@r5p_bus_dec.m), line:15:18, endln:15:19 |vpiTypedef: \_interface_typespec: (man), line:15:14, endln:15:17 |vpiParent: @@ -461,7 +498,7 @@ design: (work@r5p_bus_dec) |vpiInterface: \_interface: work@r5p_bus_if (work@r5p_bus_dec.m[1]), file:dut.sv, line:12:0 |vpiInterfaceArray: - \_interface_array: (work@r5p_bus_dec.m) + \_interface_array: (work@r5p_bus_dec.m), line:15:18, endln:15:19 |vpiParent: \_module: work@r5p_bus_dec (work@r5p_bus_dec), file:dut.sv, line:12:1, endln:29:10 |vpiName:m diff --git a/tests/ModPortRange/ModPortRange.log b/tests/ModPortRange/ModPortRange.log index c0933088a7..95e907a25d 100644 --- a/tests/ModPortRange/ModPortRange.log +++ b/tests/ModPortRange/ModPortRange.log @@ -57,11 +57,11 @@ === UHDM Object Stats Begin (Non-Elaborated Model) === array_net 1 array_typespec 5 -constant 28 +constant 36 design 1 interface 13 -interface_array 4 -interface_typespec 36 +interface_array 8 +interface_typespec 40 io_decl 13 logic_net 16 logic_typespec 16 @@ -69,7 +69,7 @@ logic_var 7 modport 13 module 11 port 23 -range 14 +range 18 ref_obj 23 === UHDM Object Stats End === [INF:UH0707] Elaborating UHDM... @@ -77,11 +77,11 @@ ref_obj 23 === UHDM Object Stats Begin (Elaborated Model) === array_net 1 array_typespec 5 -constant 28 +constant 36 design 1 interface 13 -interface_array 4 -interface_typespec 36 +interface_array 8 +interface_typespec 40 io_decl 13 logic_net 16 logic_typespec 16 @@ -89,7 +89,7 @@ logic_var 7 modport 13 module 11 port 32 -range 14 +range 18 ref_obj 32 === UHDM Object Stats End === [INF:UH0708] Writing UHDM DB: ../../build/regression/ModPortRange/slpp_unit/surelog.uhdm ... @@ -285,6 +285,33 @@ design: (work@range_itf_port) |vpiElemTypespec: \_interface_typespec: (ConnectTB), line:35:16, endln:35:25 |vpiName:ConnectTB + |vpiInterfaceArray: + \_interface_array: (ConnectTB), line:35:26, endln:35:31 + |vpiParent: + \_module: work@middle (work@middle), file:dut.sv, line:35:1, endln:36:10 + |vpiName:conn1 + |vpiFullName:ConnectTB + |vpiRange: + \_range: , line:35:32, endln:35:37 + |vpiLeftRange: + \_constant: , line:35:33, endln:35:34 + |vpiParent: + \_range: , line:35:32, endln:35:37 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:35:35, endln:35:36 + |vpiParent: + \_range: , line:35:32, endln:35:37 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_interface_typespec: (ConnectTB), line:35:16, endln:35:25 + |vpiName:ConnectTB |uhdmallModules: \_module: work@range_itf_port (work@range_itf_port), file:dut.sv, line:9:1, endln:13:10 |vpiParent: @@ -378,6 +405,33 @@ design: (work@range_itf_port) |vpiConstType:9 |vpiElemTypespec: \_logic_typespec: , line:11:11, endln:11:16 + |vpiInterfaceArray: + \_interface_array: (MyInterface.MyModPort), line:10:27, endln:10:35 + |vpiParent: + \_module: work@range_itf_port (work@range_itf_port), file:dut.sv, line:9:1, endln:13:10 + |vpiName:my_port1 + |vpiFullName:MyInterface.MyModPort + |vpiRange: + \_range: , line:10:35, endln:10:40 + |vpiLeftRange: + \_constant: , line:10:36, endln:10:37 + |vpiParent: + \_range: , line:10:35, endln:10:40 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:10:38, endln:10:39 + |vpiParent: + \_range: , line:10:35, endln:10:40 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_interface_typespec: (MyInterface.MyModPort), line:10:5, endln:10:26 + |vpiName:MyInterface.MyModPort |uhdmallModules: \_module: work@range_itf_port2 (work@range_itf_port2), file:dut.sv, line:39:1, endln:46:10 |vpiParent: @@ -512,6 +566,60 @@ design: (work@range_itf_port) |vpiElemTypespec: \_interface_typespec: (MyInterface), line:43:5, endln:43:16 |vpiName:MyInterface + |vpiInterfaceArray: + \_interface_array: (MyInterface.MyModPort), line:41:27, endln:41:35 + |vpiParent: + \_module: work@range_itf_port2 (work@range_itf_port2), file:dut.sv, line:39:1, endln:46:10 + |vpiName:my_port2 + |vpiFullName:MyInterface.MyModPort + |vpiRange: + \_range: , line:41:35, endln:41:40 + |vpiLeftRange: + \_constant: , line:41:36, endln:41:37 + |vpiParent: + \_range: , line:41:35, endln:41:40 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:41:38, endln:41:39 + |vpiParent: + \_range: , line:41:35, endln:41:40 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_interface_typespec: (MyInterface.MyModPort), line:41:5, endln:41:26 + |vpiName:MyInterface.MyModPort + |vpiInterfaceArray: + \_interface_array: (MyInterface), line:43:18, endln:43:26 + |vpiParent: + \_module: work@range_itf_port2 (work@range_itf_port2), file:dut.sv, line:39:1, endln:46:10 + |vpiName:my_port4 + |vpiFullName:MyInterface + |vpiRange: + \_range: , line:43:26, endln:43:31 + |vpiLeftRange: + \_constant: , line:43:27, endln:43:28 + |vpiParent: + \_range: , line:43:26, endln:43:31 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:43:29, endln:43:30 + |vpiParent: + \_range: , line:43:26, endln:43:31 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_interface_typespec: (MyInterface), line:43:5, endln:43:16 + |vpiName:MyInterface |uhdmtopModules: \_module: work@range_itf_port (work@range_itf_port), file:dut.sv, line:9:1, endln:13:10 |vpiName:work@range_itf_port @@ -563,7 +671,7 @@ design: (work@range_itf_port) \_port: (my_port1), line:10:27, endln:10:35 |vpiFullName:work@range_itf_port.my_port1 |vpiActual: - \_interface_array: (work@range_itf_port.my_port1) + \_interface_array: (work@range_itf_port.my_port1), line:10:27, endln:10:35 |vpiTypedef: \_interface_typespec: (MyModPort), line:10:17, endln:10:26 |vpiParent: @@ -639,7 +747,7 @@ design: (work@range_itf_port) |vpiInterface: \_interface: work@MyInterface (work@range_itf_port.my_port1[1]), file:dut.sv, line:9:0 |vpiInterfaceArray: - \_interface_array: (work@range_itf_port.my_port1) + \_interface_array: (work@range_itf_port.my_port1), line:10:27, endln:10:35 |vpiParent: \_module: work@range_itf_port (work@range_itf_port), file:dut.sv, line:9:1, endln:13:10 |vpiName:my_port1 @@ -872,7 +980,7 @@ design: (work@range_itf_port) \_port: (my_port2), line:41:27, endln:41:35 |vpiFullName:work@range_itf_port2.my_port2 |vpiActual: - \_interface_array: (work@range_itf_port2.my_port2) + \_interface_array: (work@range_itf_port2.my_port2), line:41:27, endln:41:35 |vpiTypedef: \_interface_typespec: (MyModPort), line:41:17, endln:41:26 |vpiParent: @@ -1040,7 +1148,7 @@ design: (work@range_itf_port) |vpiInterface: \_interface: work@MyInterface (work@range_itf_port2.my_port4), file:dut.sv, line:39:0 |vpiInterfaceArray: - \_interface_array: (work@range_itf_port2.my_port2) + \_interface_array: (work@range_itf_port2.my_port2), line:41:27, endln:41:35 |vpiParent: \_module: work@range_itf_port2 (work@range_itf_port2), file:dut.sv, line:39:1, endln:46:10 |vpiName:my_port2 diff --git a/tests/UnitElab/UnitElab.log b/tests/UnitElab/UnitElab.log index 76767c3a0e..ad26626598 100644 --- a/tests/UnitElab/UnitElab.log +++ b/tests/UnitElab/UnitElab.log @@ -13568,7 +13568,7 @@ Instance tree: class_defn 8 class_typespec 4 class_var 3 -constant 4323 +constant 4329 cont_assign 1 design 1 enum_const 5 @@ -13585,13 +13585,15 @@ logic_net 105 logic_typespec 134 logic_var 1 module 1274 +module_array 1 +module_typespec 1 operation 1335 package 2 param_assign 10 parameter 1210 port 115 prim_term 11 -range 86 +range 89 ref_obj 197 task 9 === UHDM Object Stats End === @@ -17362,6 +17364,117 @@ design: (work@bottom1) \_logic_net: (work@top.inst1.c), line:20:25, endln:20:26 |vpiTypedef: \_logic_typespec: , line:22:8, endln:22:8 + |vpiModuleArray: + \_module_array: (work@my_module), line:29:13, endln:29:17 + |vpiParent: + \_module: work@top (work@top), file:top.v, line:26:1, endln:31:10 + |vpiName:inst + |vpiFullName:work@my_module + |vpiRange: + \_range: , line:29:18, endln:29:23 + |vpiLeftRange: + \_constant: , line:29:19, endln:29:20 + |vpiParent: + \_range: , line:29:18, endln:29:23 + |vpiDecompile:3 + |vpiSize:64 + |UINT:3 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:29:21, endln:29:22 + |vpiParent: + \_range: , line:29:18, endln:29:23 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRange: + \_range: , line:29:23, endln:29:28 + |vpiLeftRange: + \_constant: , line:29:24, endln:29:25 + |vpiParent: + \_range: , line:29:23, endln:29:28 + |vpiDecompile:2 + |vpiSize:64 + |UINT:2 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:29:26, endln:29:27 + |vpiParent: + \_range: , line:29:23, endln:29:28 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiRange: + \_range: , line:29:28, endln:29:33 + |vpiLeftRange: + \_constant: , line:29:29, endln:29:30 + |vpiParent: + \_range: , line:29:28, endln:29:33 + |vpiDecompile:1 + |vpiSize:64 + |UINT:1 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:29:31, endln:29:32 + |vpiParent: + \_range: , line:29:28, endln:29:33 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@my_module (work@top.inst[0][0][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[0][0][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[0][1][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[0][1][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[0][2][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[0][2][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[1][0][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[1][0][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[1][1][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[1][1][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[1][2][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[1][2][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[2][0][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[2][0][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[2][1][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[2][1][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[2][2][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[2][2][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[3][0][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[3][0][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[3][1][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[3][1][1]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[3][2][0]), file:top.v, line:29:3, endln:29:44 + |vpiModule: + \_module: work@my_module (work@top.inst[3][2][1]), file:top.v, line:29:3, endln:29:44 + |vpiElemTypespec: + \_module_typespec: (my_module), line:29:3, endln:29:12 + |vpiName:my_module |uhdmtopModules: \_module: work@test (work@test), file:top.v, line:35:1, endln:76:10 |vpiName:work@test diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log index fd1d0e3a57..1c93179621 100644 --- a/third_party/tests/NyuziProcessor/NyuziProcessor.log +++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log @@ -20,123 +20,123 @@ [INF:PP0122] Preprocessing source file "hardware/testbench/sim_sdram.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". + [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". + [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". + [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". @@ -156,123 +156,123 @@ [INF:PA0201] Parsing source file "hardware/testbench/sim_sdram.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". + [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". + [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv". + [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv". @@ -1489,7 +1489,7 @@ case_stmt 137 class_defn 8 class_typespec 4 class_var 3 -constant 59835 +constant 59839 cont_assign 1886 design 1 enum_const 674 @@ -1514,8 +1514,8 @@ int_var 92 integer_typespec 97 integer_var 1 interface 48 -interface_array 2 -interface_typespec 116 +interface_array 4 +interface_typespec 118 io_decl 831 logic_net 3873 logic_typespec 9604 @@ -1530,7 +1530,7 @@ param_assign 24316 parameter 36057 part_select 356 port 2951 -range 7848 +range 7850 ref_obj 34767 string_typespec 83 string_var 1 @@ -1561,7 +1561,7 @@ case_stmt 379 class_defn 8 class_typespec 4 class_var 3 -constant 59932 +constant 59936 cont_assign 4903 design 1 enum_const 679 @@ -1586,8 +1586,8 @@ int_var 209 integer_typespec 97 integer_var 1 interface 48 -interface_array 2 -interface_typespec 116 +interface_array 4 +interface_typespec 118 io_decl 845 logic_net 3873 logic_typespec 9604 @@ -1602,7 +1602,7 @@ param_assign 40298 parameter 36057 part_select 970 port 6533 -range 8938 +range 8940 ref_obj 94296 string_typespec 83 string_var 1 diff --git a/third_party/tests/Rp32/rp32.log b/third_party/tests/Rp32/rp32.log index 6e4a9c4c35..2a080d51de 100644 --- a/third_party/tests/Rp32/rp32.log +++ b/third_party/tests/Rp32/rp32.log @@ -409,7 +409,7 @@ case_stmt 44 class_defn 8 class_typespec 4 class_var 3 -constant 6129 +constant 6133 cont_assign 84 design 1 enum_const 412 @@ -428,24 +428,26 @@ int_typespec 167 int_var 17 integer_typespec 22 interface 13 -interface_array 1 -interface_typespec 20 +interface_array 2 +interface_typespec 21 io_decl 235 logic_net 417 logic_typespec 886 logic_var 203 modport 22 module 85 +module_array 1 +module_typespec 1 named_begin 1 -operation 1945 +operation 1946 package 8 packed_array_typespec 2 param_assign 156 parameter 161 part_select 57 port 217 -range 791 -ref_obj 4991 +range 793 +ref_obj 4992 return_stmt 2 string_typespec 350 struct_net 28 @@ -474,7 +476,7 @@ case_stmt 243 class_defn 8 class_typespec 4 class_var 3 -constant 6190 +constant 6194 cont_assign 159 design 1 enum_const 417 @@ -493,24 +495,26 @@ int_typespec 167 int_var 18 integer_typespec 22 interface 13 -interface_array 1 -interface_typespec 20 +interface_array 2 +interface_typespec 21 io_decl 428 logic_net 417 logic_typespec 886 logic_var 207 modport 22 module 89 +module_array 1 +module_typespec 1 named_begin 2 -operation 5616 +operation 5617 package 8 packed_array_typespec 2 param_assign 156 parameter 161 part_select 194 port 321 -range 795 -ref_obj 19741 +range 797 +ref_obj 19742 return_stmt 16 string_typespec 350 struct_net 28 diff --git a/third_party/tests/Tnoc/Tnoc.log b/third_party/tests/Tnoc/Tnoc.log index 37c77b8a53..8f717b9d1e 100644 --- a/third_party/tests/Tnoc/Tnoc.log +++ b/third_party/tests/Tnoc/Tnoc.log @@ -9230,7 +9230,7 @@ case_stmt 5 class_defn 8 class_typespec 4 class_var 3 -constant 691362 +constant 691432 cont_assign 1568 design 1 enum_const 7563 @@ -9250,8 +9250,8 @@ indexed_part_select 2 int_typespec 143849 int_var 105 interface 10798 -interface_array 434 -interface_typespec 16045 +interface_array 461 +interface_typespec 16072 io_decl 47700 logic_net 2150 logic_typespec 24576 @@ -9259,7 +9259,7 @@ logic_var 22084 method_func_call 447 modport 11155 module 21203 -operation 130596 +operation 130623 package 8 packed_array_typespec 3729 packed_array_var 3710 @@ -9267,8 +9267,8 @@ param_assign 50980 parameter 58497 part_select 342 port 8086 -range 50969 -ref_obj 134779 +range 50996 +ref_obj 134790 ref_var 11 return_stmt 326 short_int_typespec 433808 diff --git a/third_party/tests/YosysIce40/YosysIce40.log b/third_party/tests/YosysIce40/YosysIce40.log index d1a182b259..d1a4430b1a 100644 --- a/third_party/tests/YosysIce40/YosysIce40.log +++ b/third_party/tests/YosysIce40/YosysIce40.log @@ -625,7 +625,7 @@ case_stmt 117 class_defn 8 class_typespec 4 class_var 3 -constant 16850 +constant 16852 cont_assign 513 design 1 enum_const 5 @@ -649,13 +649,15 @@ logic_net 4197 logic_typespec 3290 logic_var 1 module 204 +module_array 1 +module_typespec 1 operation 2943 package 2 param_assign 346 parameter 346 part_select 906 port 1804 -range 2634 +range 2635 ref_obj 12442 ref_var 2 sys_func_call 71 diff --git a/third_party/tests/YosysMarlann/YosysMarlann.log b/third_party/tests/YosysMarlann/YosysMarlann.log index ae7c082779..0c5b7b1b4e 100644 --- a/third_party/tests/YosysMarlann/YosysMarlann.log +++ b/third_party/tests/YosysMarlann/YosysMarlann.log @@ -48,7 +48,7 @@ case_stmt 5 class_defn 8 class_typespec 4 class_var 3 -constant 1145 +constant 1152 cont_assign 21 design 1 enum_const 5 @@ -61,21 +61,23 @@ if_stmt 26 indexed_part_select 76 int_typespec 9 int_var 4 -integer_typespec 7 +integer_typespec 8 integer_var 1 io_decl 11 logic_net 273 logic_typespec 182 logic_var 1 module 22 -operation 315 +module_array 2 +module_typespec 2 +operation 319 package 2 param_assign 6 parameter 6 part_select 60 port 62 -range 262 -ref_obj 516 +range 264 +ref_obj 517 sys_func_call 52 task 9 var_select 2 diff --git a/third_party/tests/oh/BasicOh.log b/third_party/tests/oh/BasicOh.log index 84216a54c2..8495b1910b 100644 --- a/third_party/tests/oh/BasicOh.log +++ b/third_party/tests/oh/BasicOh.log @@ -2,563 +2,563 @@ [INF:PP0122] Preprocessing source file "stdlib/hdl/oh_fifo_async.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". + +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". [INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". - -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". -[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". +[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". [INF:PA0201] Parsing source file "stdlib/hdl/oh_fifo_async.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". + +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v". [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v". - -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg0.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v". -[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v". +[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v". [INF:CM0029] Using global timescale: "1ns/1ns". @@ -1270,7 +1270,7 @@ bit_select 58 class_defn 8 class_typespec 4 class_var 3 -constant 2970 +constant 2976 cont_assign 148 design 1 enum_const 5 @@ -1292,14 +1292,16 @@ logic_net 1063 logic_typespec 1096 logic_var 1 module 330 +module_array 4 +module_typespec 4 operation 1836 package 2 param_assign 323 parameter 323 part_select 308 port 962 -range 767 -ref_obj 3051 +range 771 +ref_obj 3053 ref_var 4 string_typespec 114 sys_func_call 12 @@ -1309,27 +1311,27 @@ var_select 1 [INF:UH0707] Elaborating UHDM... === UHDM Object Stats Begin (Elaborated Model) === -always 79 +always 91 array_net 1 assign_stmt 7 -assignment 170 +assignment 194 begin 11 -bit_select 99 +bit_select 123 class_defn 8 class_typespec 4 class_var 3 -constant 2988 -cont_assign 171 +constant 3006 +cont_assign 183 design 1 enum_const 10 enum_typespec 2 enum_var 1 -event_control 77 +event_control 89 for_stmt 7 function 18 -gen_scope 45 -gen_scope_array 45 -if_else 71 +gen_scope 57 +gen_scope_array 57 +if_else 83 if_stmt 21 int_typespec 305 int_var 4 @@ -1340,14 +1342,16 @@ logic_net 1063 logic_typespec 1096 logic_var 1 module 330 -operation 2048 +module_array 4 +module_typespec 4 +operation 2180 package 2 param_assign 323 parameter 323 -part_select 413 -port 1065 -range 767 -ref_obj 3471 +part_select 473 +port 1113 +range 771 +ref_obj 3689 ref_var 7 string_typespec 114 sys_func_call 12 @@ -23912,6 +23916,54 @@ design: (work@oh_fifo_async) |UINT:0 |vpiConstType:9 |vpiAlwaysType:1 + |vpiModuleArray: + \_module_array: (work@oh_dsync), line:121:4, endln:121:11 + |vpiParent: + \_module: work@oh_fifo_async (work@oh_fifo_async), file:stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + |vpiName:wr_sync + |vpiFullName:work@oh_dsync + |vpiRange: + \_range: , line:121:11, endln:121:17 + |vpiLeftRange: + \_ref_obj: (AW), line:121:12, endln:121:14 + |vpiParent: + \_range: , line:121:11, endln:121:17 + |vpiName:AW + |vpiRightRange: + \_constant: , line:121:15, endln:121:16 + |vpiParent: + \_range: , line:121:11, endln:121:17 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_module_typespec: (oh_dsync), line:119:4, endln:119:12 + |vpiName:oh_dsync + |vpiModuleArray: + \_module_array: (work@oh_dsync), line:137:4, endln:137:11 + |vpiParent: + \_module: work@oh_fifo_async (work@oh_fifo_async), file:stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + |vpiName:rd_sync + |vpiFullName:work@oh_dsync + |vpiRange: + \_range: , line:137:11, endln:137:17 + |vpiLeftRange: + \_ref_obj: (AW), line:137:12, endln:137:14 + |vpiParent: + \_range: , line:137:11, endln:137:17 + |vpiName:AW + |vpiRightRange: + \_constant: , line:137:15, endln:137:16 + |vpiParent: + \_range: , line:137:11, endln:137:17 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiElemTypespec: + \_module_typespec: (oh_dsync), line:135:4, endln:135:12 + |vpiName:oh_dsync |vpiContAssign: \_cont_assign: , line:88:11, endln:88:40 |vpiParent: @@ -73882,6 +73934,84 @@ design: (work@oh_fifo_async) |vpiSize:64 |UINT:0 |vpiConstType:9 + |vpiModuleArray: + \_module_array: (work@oh_dsync), line:121:4, endln:121:11 + |vpiParent: + \_module: work@oh_fifo_async (work@oh_fifo_async), file:stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + |vpiName:wr_sync + |vpiFullName:work@oh_dsync + |vpiRange: + \_range: , line:121:11, endln:121:17 + |vpiLeftRange: + \_constant: , line:121:12, endln:121:14 + |vpiParent: + \_range: , line:121:11, endln:121:17 + |vpiDecompile:5 + |vpiSize:64 + |UINT:5 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:121:15, endln:121:16 + |vpiParent: + \_range: , line:121:11, endln:121:17 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[0]), file:stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[1]), file:stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[2]), file:stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[3]), file:stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[4]), file:stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.wr_sync[5]), file:stdlib/hdl/oh_fifo_async.v, line:119:4, endln:124:35 + |vpiElemTypespec: + \_module_typespec: (oh_dsync), line:119:4, endln:119:12 + |vpiName:oh_dsync + |vpiModuleArray: + \_module_array: (work@oh_dsync), line:137:4, endln:137:11 + |vpiParent: + \_module: work@oh_fifo_async (work@oh_fifo_async), file:stdlib/hdl/oh_fifo_async.v, line:11:1, endln:186:10 + |vpiName:rd_sync + |vpiFullName:work@oh_dsync + |vpiRange: + \_range: , line:137:11, endln:137:17 + |vpiLeftRange: + \_constant: , line:137:12, endln:137:14 + |vpiParent: + \_range: , line:137:11, endln:137:17 + |vpiDecompile:5 + |vpiSize:64 + |UINT:5 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:137:15, endln:137:16 + |vpiParent: + \_range: , line:137:11, endln:137:17 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[0]), file:stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[1]), file:stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[2]), file:stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[3]), file:stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[4]), file:stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiModule: + \_module: work@oh_dsync (work@oh_fifo_async.rd_sync[5]), file:stdlib/hdl/oh_fifo_async.v, line:135:4, endln:140:35 + |vpiElemTypespec: + \_module_typespec: (oh_dsync), line:135:4, endln:135:12 + |vpiName:oh_dsync |vpiContAssign: \_cont_assign: , line:88:11, endln:88:40 |vpiParent: