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Hi all,
I found a very wired behaviour in preprocessor:
case1.sv
`define FOO(n) n // comment `define BAR 10'h03E module top(); wire [9:0] a; assign a = `BAR; endmodule
With surelog surelog -nobuiltin -nocache -writeppfile /dev/stdout case1.sv:
surelog -nobuiltin -nocache -writeppfile /dev/stdout case1.sv
[INF:CM0023] Creating log file "/***/slpp_all/surelog.log". [ERR:PP0102] /***/case1.sv:8:14: Unknown macro "BAR". module top(); wire [9:0] a; assign a = SURELOG_MACRO_NOT_DEFINED:BAR!!! ; endmodule [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 1 [WARNING] : 0 [ NOTE] : 0
Verilator verilator -E ./case1.sv :
verilator -E ./case1.sv
`line 1 "case1.sv" 1 `line 4 "case1.sv" 0 module top(); wire [9:0] a; assign a = 10'h03E; endmodule `line 10 "case1.sv" 0
For context:
surelog --version VERSION: 1.84 BUILT : Dec 8 2024
Any idea what's going on here?
Thanks!
The text was updated successfully, but these errors were encountered:
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Hi all,
I found a very wired behaviour in preprocessor:
case1.sv
With surelog
surelog -nobuiltin -nocache -writeppfile /dev/stdout case1.sv
:Verilator
verilator -E ./case1.sv
:For context:
Any idea what's going on here?
Thanks!
The text was updated successfully, but these errors were encountered: