diff --git a/chipfail-glitcher-artix-7.srcs/constrs_1/Arty_Master.xdc b/chipfail-glitcher-artix-7.srcs/constrs_1/Arty_Master.xdc new file mode 100644 index 0000000..84aba20 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/constrs_1/Arty_Master.xdc @@ -0,0 +1,232 @@ +## This file is a general .xdc for the ARTY Rev. B +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal + +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports sys_clk]; +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clk]; + +##Switches + +#set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}] +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1] +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2] +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3] + +##RGB LEDs + +set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports { rgb[0] }]; #led0_b +set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { rgb[1] }]; #led0_g IO_L19N_T3_VREF_35 Sch=led0_g +set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { rgb[2] }]; #led0_r IO_L19P_T3_35 Sch=led0_r +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports led1_g] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b +#set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports led2_g] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b +#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r + +##LEDs + +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports { led[0] }]; +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports { led[1] }]; +#set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led_debug}] +#set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {leds[1]}] + +##Buttons + +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0] +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10] + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { glitch_out }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2] +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { power_out }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2] closest to GND/POWER n.4 +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3] +#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4] +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4] + +##Pmod Header JC +# +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { mux_out }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1] mux_enable +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { enable_c }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1] emable_c +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { glitch_out }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2] enable_b +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { power_out }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2] enable_a +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3] +#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4] + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10] + +##USB-UART Interface + +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out]; # This is the TX output +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in]; + +##ChipKit Single Ended Analog Inputs +##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). +## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19]. + +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] + +##ChipKit Digital I/O Low + +#set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {debug_header[0]}] +#set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {debug_header[1]}] +#set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {debug_header[2]}] +#set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {debug_header[3]}] +#set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {debug_header[4]}] +#set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {debug_header[5]}] +#set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {debug_header[6]}] +#set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {debug_header[7]}] +#set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {debug_header[8]}] +#set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {debug_header[9]}] +#set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {debug_header[10]}] +#set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {debug_header[11]}] +#set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {debug_header[12]}] +#set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {debug_header[13]}] + +##ChipKit Digital I/O On Outer Analog Header +##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19) + +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_0_35 Sch=ck_a[0] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L4P_T0_35 Sch=ck_a[1] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L4N_T0_35 Sch=ck_a[2] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L6P_T0_35 Sch=ck_a[3] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] + +##ChipKit Digital I/O On Inner Analog Header +##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11) + +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] + +##ChipKit Digital I/O High + +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports { gpio[0] }]; +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports { gpio[1] }]; +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports { gpio[2] }]; +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { gpio[3] }]; #IO_25_14 Sch=ck_io[29] +set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { gpio[4] }]; #IO_0_14 Sch=ck_io[30] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { gpio[5] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { gpio[6] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { gpio[7] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports { trigger_in } ]; # Sch=ck_io[33] +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] +#set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports vout_pwr] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38] +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41] + +## ChipKit SPI + +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss + +## ChipKit I2C + +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup + +##Misc. ChipKit signals + +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3] +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3] + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] + +##Power Measurements + +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2] +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1] +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1] +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10] + + + + + diff --git a/chipfail-glitcher-artix-7.srcs/sim_1/new/top_tb.v b/chipfail-glitcher-artix-7.srcs/sim_1/new/top_tb.v new file mode 100644 index 0000000..66ff06e --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sim_1/new/top_tb.v @@ -0,0 +1,62 @@ +`timescale 1ns / 1ps + + +module top_tb( + input sys_clk +); + + +reg clk; +reg [7:0] data = 8'd64; +reg enable = 1'b1; +reg rst = 1'b0; +always + begin + clk = 1'b1; + #10; + clk = 1'b0; + #10; + end + +wire [1:0] led; +wire uart_tx; + +//top t1( +// .sys_clk(clk), +// .led(led), +// .uart_txd_in(uart_tx) +//); + +//module top( +// input sys_clk, +// output [1:0]led, // Led outputs +// output uart_txd_in // UART TX (strange txd_in name by Digilent) +// ); + + + + + +uart_tx tx1( + .clk(sys_clk), + .reset(rst), + .data(data), + .enable(enable), + .tx(uart_tx) +); + +top t( + .sys_clk(clk), + .uart_txd_in(uart_tx) +); + + + + +//uart_rx rx1( +// .clk(clk), +// .reset(rst), +// .rx(tx1.tx) +//); + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp new file mode 100644 index 0000000..ee0e6f5 Binary files /dev/null and b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp differ diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v new file mode 100644 index 0000000..6273730 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -0,0 +1,86 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// main_clk___100.000______0.000______50.0______479.872____668.310 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary__________12.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_3_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=83.333,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) + +module clk_wiz_0 + ( + // Clock out ports + output main_clk, + // Clock in ports + input clk_in1 + ); + + clk_wiz_0_clk_wiz inst + ( + // Clock out ports + .main_clk(main_clk), + // Clock in ports + .clk_in1(clk_in1) + ); + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo new file mode 100644 index 0000000..22047bd --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -0,0 +1,77 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// main_clk___100.000______0.000______50.0______479.872____668.310 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary__________12.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + clk_wiz_0 instance_name + ( + // Clock out ports + .main_clk(main_clk), // output main_clk + // Clock in ports + .clk_in1(clk_in1)); // input clk_in1 +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci new file mode 100644 index 0000000..0a6380a --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,700 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 833.33 + 100.0 + 0000 + 0000 + 100.000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + main_clk + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + 1.0 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary__________12.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 62.500 + 0.000 + FALSE + 83.333 + 10.0 + 7.500 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 1 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + main_clk___100.000______0.000______50.0______479.872____668.310 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 12.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + clk_wiz_0 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 833.33 + 0.010 + 100.0 + 0.010 + BUFG + 479.872 + false + 668.310 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + sys_clock + Custom + clk_in_sel + main_clk + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 62.500 + 0.000 + false + 83.333 + 10.0 + 7.500 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 12.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + artix7 + digilentinc.com:cmod_a7-35t:part0:1.1 + + xc7a35t + cpg236 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc new file mode 100644 index 0000000..870fd67 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc @@ -0,0 +1,60 @@ + +# file: clk_wiz_0.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system. If required +# commented constraints can be used in the top level xdc +#---------------------------------------------------------------- +# Connect to input port when clock capable pin is selected for input +create_clock -period 83.333 [get_ports clk_in1] +set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.83333 + + +set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml new file mode 100644 index 0000000..1a896cc --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -0,0 +1,4890 @@ + + + xilinx.com + customized_ip + clk_wiz_0 + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + 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CLK_IN2_D + Differential Clock input + + + + + + + CLK_N + + + clk_in2_n + + + + + CLK_P + + + clk_in2_p + + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN2_BOARD_INTERFACE + + + + required + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_IN_D + CLKFB_IN_D + Differential Feedback Clock input + + + + + + + CLK_N + + + clkfb_in_n + + + + + CLK_P + + + clkfb_in_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + CLKFB_OUT_D + CLKFB_OUT_D + Differential Feeback Clock Output + + + + + + + CLK_N + + + clkfb_out_n + + + + + CLK_P + + + clkfb_out_p + + + + + + CAN_DEBUG + false + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + + + + false + + + + + + reset + reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + resetn + resetn + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + clock_CLK_IN1 + + + + + + + CLK_IN1 + + + clk_in1 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + BOARD.ASSOCIATED_PARAM + CLK_IN1_BOARD_INTERFACE + + + + + clock_CLK_OUT1 + + + + + + + CLK_OUT1 + + + main_clk + + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + + + xilinx_elaborateports + Elaborate Ports + :vivado.xilinx.com:elaborate.ports + + + outputProductCRC + 9:826d923d + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + clk_wiz_v6_0_3 + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Thu Aug 01 10:34:45 UTC 2019 + + + outputProductCRC + 9:fe6a3171 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + clk_wiz_v6_0_3 + + xilinx_anylanguagesynthesis_view_fileset + + + + GENtimestamp + Thu Aug 01 10:34:55 UTC 2019 + + + outputProductCRC + 9:fe6a3171 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + + outputProductCRC + 9:fe6a3171 + + + + + xilinx_anylanguagesynthesiswrapper + Synthesis Wrapper + :vivado.xilinx.com:synthesis.wrapper + clk_wiz_0 + + xilinx_anylanguagesynthesiswrapper_view_fileset + + + + GENtimestamp + Thu Aug 01 10:34:55 UTC 2019 + + + outputProductCRC + 9:fe6a3171 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + clk_wiz_v6_0_3 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + GENtimestamp + Thu Aug 01 10:34:55 UTC 2019 + + + outputProductCRC + 9:a3708ad0 + + + + + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper + clk_wiz_0 + + xilinx_anylanguagesimulationwrapper_view_fileset + + + + GENtimestamp + Thu Aug 01 10:34:55 UTC 2019 + + + outputProductCRC + 9:a3708ad0 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Thu Aug 01 10:34:56 UTC 2019 + + + outputProductCRC + 9:fe6a3171 + + + + + xilinx_versioninformation + Version Information + :vivado.xilinx.com:docs.versioninfo + + xilinx_versioninformation_view_fileset + + + + GENtimestamp + Thu Aug 01 10:34:56 UTC 2019 + + + outputProductCRC + 9:fe6a3171 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Sat Aug 03 15:03:39 UTC 2019 + + + outputProductCRC + 9:fe6a3171 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awaddr + + in + + 10 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + 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C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 100.000 + + + C_CLKOUT2_OUT_FREQ + 100.000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 62.500 + + + C_MMCM_CLKIN1_PERIOD + 83.333 + + + C_MMCM_CLKIN2_PERIOD + 10.0 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + ZHOLD + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 7.500 + + + C_MMCM_CLKOUT1_DIVIDE + 1 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + main_clk + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 833.33 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 1.0 + + + C_DIVIDE3_AUTO + 1.0 + + + C_DIVIDE4_AUTO + 1.0 + + + C_DIVIDE5_AUTO + 1.0 + + + C_DIVIDE6_AUTO + 1.0 + + + C_DIVIDE7_AUTO + 1.0 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 100.000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_ce26ebdb + Custom + reset + + + choice_list_e099fe6c + MMCM + PLL + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_502d9f23 + ZHOLD + EXTERNAL + INTERNAL + BUF_IN + + + choice_pairs_66e4c81f + BUFG + BUFH + BUFGCE + BUFHCE + No_buffer + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_c6542ce1 + Custom + sys_clock + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + clk_wiz_0.veo + verilogTemplate + + + + xilinx_anylanguagesynthesis_view_fileset + + clk_wiz_0.xdc + xdc + + processing_order + early + + + + clk_wiz_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + true + clk_wiz_v6_0_3 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesynthesiswrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + mmcm_pll_drp_func_7s_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_7s_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_pll.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + mmcm_pll_drp_func_us_plus_mmcm.vh + verilogSource + USED_IN_ipstatic + true + clk_wiz_v6_0_3 + + + clk_wiz_0_clk_wiz.v + verilogSource + + + + xilinx_anylanguagesimulationwrapper_view_fileset + + clk_wiz_0.v + verilogSource + + + + xilinx_implementation_view_fileset + + clk_wiz_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + xilinx_versioninformation_view_fileset + + doc/clk_wiz_v6_0_changelog.txt + text + + + + xilinx_externalfiles_view_fileset + + clk_wiz_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + clk_wiz_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + clk_wiz_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + clk_wiz_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_0 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + true + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 12.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 833.33 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + false + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 1 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + main_clk + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Single_ended_clock_capable_pin + + + CLKOUT1_DRIVES + BUFG + + + CLKOUT2_DRIVES + BUFG + + + CLKOUT3_DRIVES + BUFG + + + CLKOUT4_DRIVES + BUFG + + + CLKOUT5_DRIVES + BUFG + + + CLKOUT6_DRIVES + BUFG + + + CLKOUT7_DRIVES + BUFG + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + false + + + CALC_DONE + empty + + + USE_RESET + false + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 62.500 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 83.333 + + + MMCM_CLKIN2_PERIOD + 10.0 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + ZHOLD + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 7.500 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 1 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + sys_clock + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 479.872 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 668.310 + + + CLKOUT2_JITTER + Clkout2 Jitter + 0.0 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 0.0 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.1 + + + + + + + + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc new file mode 100644 index 0000000..1be7760 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc @@ -0,0 +1,3 @@ +#--------------------Physical Constraints----------------- + +set_property BOARD_PIN {clk} [get_ports clk_in1] diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v new file mode 100644 index 0000000..c18f1cc --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -0,0 +1,198 @@ + +// file: clk_wiz_0.v +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// main_clk___100.000______0.000______50.0______479.872____668.310 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary__________12.000____________0.010 + +`timescale 1ps/1ps + +module clk_wiz_0_clk_wiz + + (// Clock in ports + // Clock out ports + output main_clk, + input clk_in1 + ); + // Input buffering + //------------------------------------ +wire clk_in1_clk_wiz_0; +wire clk_in2_clk_wiz_0; + IBUF clkin1_ibufg + (.O (clk_in1_clk_wiz_0), + .I (clk_in1)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire main_clk_clk_wiz_0; + wire clk_out2_clk_wiz_0; + wire clk_out3_clk_wiz_0; + wire clk_out4_clk_wiz_0; + wire clk_out5_clk_wiz_0; + wire clk_out6_clk_wiz_0; + wire clk_out7_clk_wiz_0; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (62.500), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (7.500), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (83.333)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_clk_wiz_0), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (main_clk_clk_wiz_0), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_clk_wiz_0), + .CLKIN1 (clk_in1_clk_wiz_0), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (1'b0)); + +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_clk_wiz_0), + .I (clkfbout_clk_wiz_0)); + + + + + + + BUFG clkout1_buf + (.O (main_clk), + .I (main_clk_clk_wiz_0)); + + + + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc new file mode 100644 index 0000000..435a1d7 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc @@ -0,0 +1,58 @@ + +# file: clk_wiz_0_ooc.xdc +# +# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +################# +#DEFAULT CLOCK CONSTRAINTS + +############################################################ +# Clock Period Constraints # +############################################################ +#create_clock -period 83.333 [get_ports clk_in1] + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v new file mode 100644 index 0000000..2ba9d3a --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -0,0 +1,232 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Sat Aug 3 17:03:39 2019 +// Host : DESKTOP-TFPC34Q running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// C:/Users/Thomas/Documents/GitHub/chipfail-glitcher/chipfail-glitcher.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +// Design : clk_wiz_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module clk_wiz_0 + (main_clk, + clk_in1); + output main_clk; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire main_clk; + + clk_wiz_0_clk_wiz_0_clk_wiz inst + (.clk_in1(clk_in1), + .main_clk(main_clk)); +endmodule + +(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *) +module clk_wiz_0_clk_wiz_0_clk_wiz + (main_clk, + clk_in1); + output main_clk; + input clk_in1; + + wire clk_in1; + wire clk_in1_clk_wiz_0; + wire clkfbout_buf_clk_wiz_0; + wire clkfbout_clk_wiz_0; + wire main_clk; + wire main_clk_clk_wiz_0; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_clk_wiz_0), + .O(clkfbout_buf_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_clk_wiz_0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(main_clk_clk_wiz_0), + .O(main_clk)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(62.500000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(83.333000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(7.500000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_clk_wiz_0), + .CLKFBOUT(clkfbout_clk_wiz_0), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_clk_wiz_0), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(main_clk_clk_wiz_0), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl new file mode 100644 index 0000000..4e82910 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -0,0 +1,185 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Sat Aug 3 17:03:39 2019 +-- Host : DESKTOP-TFPC34Q running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- C:/Users/Thomas/Documents/GitHub/chipfail-glitcher/chipfail-glitcher.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +-- Design : clk_wiz_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0_clk_wiz_0_clk_wiz is + port ( + main_clk : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz"; +end clk_wiz_0_clk_wiz_0_clk_wiz; + +architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is + signal clk_in1_clk_wiz_0 : STD_LOGIC; + signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; + signal clkfbout_clk_wiz_0 : STD_LOGIC; + signal main_clk_clk_wiz_0 : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_clk_wiz_0, + O => clkfbout_buf_clk_wiz_0 + ); +clkin1_ibufg: unisim.vcomponents.IBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1, + O => clk_in1_clk_wiz_0 + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => main_clk_clk_wiz_0, + O => main_clk + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 62.500000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 83.333000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 7.500000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_clk_wiz_0, + CLKFBOUT => clkfbout_clk_wiz_0, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_clk_wiz_0, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => main_clk_clk_wiz_0, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity clk_wiz_0 is + port ( + main_clk : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of clk_wiz_0 : entity is true; +end clk_wiz_0; + +architecture STRUCTURE of clk_wiz_0 is +begin +inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz + port map ( + clk_in1 => clk_in1, + main_clk => main_clk + ); +end STRUCTURE; diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v new file mode 100644 index 0000000..289633a --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -0,0 +1,20 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +// Date : Sat Aug 3 17:03:39 2019 +// Host : DESKTOP-TFPC34Q running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// C:/Users/Thomas/Documents/GitHub/chipfail-glitcher/chipfail-glitcher.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Design : clk_wiz_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module clk_wiz_0(main_clk, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="main_clk,clk_in1" */; + output main_clk; + input clk_in1; +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl new file mode 100644 index 0000000..dbafc14 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -0,0 +1,29 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +-- Date : Sat Aug 3 17:03:39 2019 +-- Host : DESKTOP-TFPC34Q running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- C:/Users/Thomas/Documents/GitHub/chipfail-glitcher/chipfail-glitcher.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Design : clk_wiz_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tcpg236-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity clk_wiz_0 is + Port ( + main_clk : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end clk_wiz_0; + +architecture stub of clk_wiz_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "main_clk,clk_in1"; +begin +end; diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt new file mode 100644 index 0000000..ed75ccb --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt @@ -0,0 +1,194 @@ +2019.1: + * Version 6.0 (Rev. 3) + * Bug Fix: Internal GUI fixes + * Other: New family support added + +2018.3.1: + * Version 6.0 (Rev. 2) + * No changes + +2018.3: + * Version 6.0 (Rev. 2) + * Bug Fix: Made input source independent for primary and secondary clock + * Other: New family support added + +2018.2: + * Version 6.0 (Rev. 1) + * Bug Fix: Removed vco freq check when Primitive is None + * Other: New family support added + +2018.1: + * Version 6.0 + * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature + * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI + * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. + * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support + * Other: DRCs added for invalid input values in Override mode + +2017.4: + * Version 5.4 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL + * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 + +2017.3: + * Version 5.4 (Rev. 2) + * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices + +2017.2: + * Version 5.4 (Rev. 1) + * General: Internal GUI changes. No effect on the customer design. + +2017.1: + * Version 5.4 + * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. + * Other: Added support for new zynq ultrascale plus devices. + +2016.4: + * Version 5.3 (Rev. 3) + * Bug Fix: Internal GUI issues are fixed. + +2016.3: + * Version 5.3 (Rev. 2) + * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. + * Feature Enhancement: Added Matched Routing Option for better timing solutions. + * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. + * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user + * Other: Added support for Spartan7 devices. + +2016.2: + * Version 5.3 (Rev. 1) + * Internal register bit update, no effect on customer designs. + +2016.1: + * Version 5.3 + * Added Clock Monitor Feature as part of clocking wizard + * DRP registers can be directly written through AXI without resource utilization + * Changes to HDL library management to support Vivado IP simulation library + +2015.4.2: + * Version 5.2 (Rev. 1) + * No changes + +2015.4.1: + * Version 5.2 (Rev. 1) + * No changes + +2015.4: + * Version 5.2 (Rev. 1) + * Internal device family change, no functional changes + +2015.3: + * Version 5.2 + * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances + * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported + * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature + * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format + * Example design and simulation files are delivered in verilog only + +2015.2.1: + * Version 5.1 (Rev. 6) + * No changes + +2015.2: + * Version 5.1 (Rev. 6) + * No changes + +2015.1: + * Version 5.1 (Rev. 6) + * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices + * Supported devices and production status are now determined automatically, to simplify support for future devices + +2014.4.1: + * Version 5.1 (Rev. 5) + * No changes + +2014.4: + * Version 5.1 (Rev. 5) + * Internal device family change, no functional changes + * updates related to the source selection based on board interface for zed board + +2014.3: + * Version 5.1 (Rev. 4) + * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface + +2014.2: + * Version 5.1 (Rev. 3) + * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 + +2014.1: + * Version 5.1 (Rev. 2) + * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock + * Internal device family name change, no functional changes + +2013.4: + * Version 5.1 (Rev. 1) + * Added support for Ultrascale devices + * Updated Board Flow GUI to select the clock interfaces + * Fixed issue with Stub file parameter error for BUFR output driver + +2013.3: + * Version 5.1 + * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL + * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies + * Fixed precision issues between displayed and actual frequencies + * Added tool tips to GUI + * Added Jitter and Phase error values to IP properties + * Added support for Cadence IES and Synopsys VCS simulators + * Reduced warnings in synthesis and simulation + * Enhanced support for IP Integrator + +2013.2: + * Version 5.0 (Rev. 1) + * Fixed issue with clock constraints for multiple instances of clocking wizard + * Updated Life-Cycle status of devices + +2013.1: + * Version 5.0 + * Lower case ports for Verilog + * Added Safe Clock Startup and Clock Sequencing + +(c) Copyright 2008 - 2019 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh new file mode 100644 index 0000000..652d7d1 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: 7 Series || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1011_00, + 10'b0010_1101_00, + 10'b0010_0011_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0100_1111_00, + 10'b0101_1011_00, + 10'b0111_0111_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_1001_00, + 10'b1101_0001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_1001_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0111_0001_00, + 10'b0111_0001_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0110_0001_00, + 10'b0110_0001_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0101_0110_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0100_1010_00, + 10'b0011_1100_00, + 10'b0011_1100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh new file mode 100644 index 0000000..6a3e7c0 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh @@ -0,0 +1,531 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing +// Date: 7/30/2014 +// Design Name: PLLE2 DRP +// Module Name: plle2_drp_func.h +// Version: 2.00 +// Target Devices: 7 Series || PLL +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// Updated for CR663854. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_00, + 10'b0010_1111_00, + 10'b0010_0111_00, + 10'b0010_1101_00, + 10'b0010_0101_00, + 10'b0010_0101_00, + 10'b0010_1001_00, + 10'b0010_1110_00, + 10'b0010_1110_00, + 10'b0010_0001_00, + 10'b0010_0001_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_0110_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1010_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_1100_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0010_0010_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0011_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0011_0111_00, + 10'b0011_0111_00, + 10'b0101_1111_00, + 10'b0111_1111_00, + 10'b0111_1011_00, + 10'b1101_0111_00, + 10'b1110_1011_00, + 10'b1110_1101_00, + 10'b1111_1101_00, + 10'b1111_0111_00, + 10'b1111_1011_00, + 10'b1111_1101_00, + 10'b1111_0011_00, + 10'b1110_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b1111_0101_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0111_0110_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b0101_1100_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b1100_0001_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0100_0010_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0011_0100_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0010_1000_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0100_1100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00, + 10'b0010_0100_00 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); +`endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh new file mode 100644 index 0000000..2cffa9a --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh @@ -0,0 +1,671 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 7/30/2014 +// Design Name: MMCME2 DRP +// Module Name: mmcme2_drp_func.h +// Version: 1.04 +// Target Devices: UltraScale Architecture || MMCM +// Tool versions: 2014.3 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [639:0] lookup_low; + reg [639:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_0111_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_1101_11, + 10'b0010_0011_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_0101_11, + 10'b0010_1001_11, + 10'b0010_1001_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_1110_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0001_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_0110_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1010_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11, + 10'b0010_1100_11 + }; + + lookup_high = { + // CP_RES_LFHF + 10'b0010_1111_11, + 10'b0010_1111_11, + 10'b0010_1011_11, + 10'b0011_1111_11, + 10'b0100_1111_11, + 10'b0100_1111_11, + 10'b0101_1111_11, + 10'b0110_1111_11, + 10'b0111_1111_11, + 10'b0111_1111_11, + 10'b1100_1111_11, + 10'b1101_1111_11, + 10'b1110_1111_11, + 10'b1111_1111_11, + 10'b1111_1111_11, + 10'b1110_0111_11, + 10'b1110_1011_11, + 10'b1111_0111_11, + 10'b1111_1011_11, + 10'b1111_1011_11, + 10'b1110_1101_11, + 10'b1111_1101_11, + 10'b1111_1101_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1111_0011_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1110_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1111_1110_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1110_0001_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_0110_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11, + 10'b1100_1010_11 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh new file mode 100644 index 0000000..9439f23 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh @@ -0,0 +1,530 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa +// Date: 6/15/2015 +// Design Name: PLLE3 DRP +// Module Name: plle3_drp_func.h +// Version: 1.10 +// Target Devices: UltraScale Architecture +// Tool versions: 2015.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// PM_Rise bits have been removed for PLLE3 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2010 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [759:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001 //19 + + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 19 + ); + + reg [639:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0010_1111_01, //1 + 10'b0010_0011_11, //2 + 10'b0011_0011_11, //3 + 10'b0010_0001_11, //4 + 10'b0010_0110_11, //5 + 10'b0010_1010_11, //6 + 10'b0010_1010_11, //7 + 10'b0011_0110_11, //8 + 10'b0010_1100_11, //9 + 10'b0010_1100_11, //10 + 10'b0010_1100_11, //11 + 10'b0010_0010_11, //12 + 10'b0011_1100_11, //13 + 10'b0011_1100_11, //14 + 10'b0011_1100_11, //15 + 10'b0011_1100_11, //16 + 10'b0011_0010_11, //17 + 10'b0011_0010_11, //18 + 10'b0011_0010_11 //19 + }; + + mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits +// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh new file mode 100644 index 0000000..61edf85 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh @@ -0,0 +1,861 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa. Updated by Ralf Krueger +// Date: 7/30/2014 +// Design Name: MMCME4 DRP +// Module Name: mmcme4_drp_func.h +// Version: 1.31 +// Target Devices: UltraScale Plus Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for UltraScal+ MMCM. +// +// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) +// 4/13 - Fractional divide function in mmcm_frac_count_calc function +// 2/28/17 - Updated for Ultrascale Plus +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages during elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("mmcm_phase-divide:%d,phase:%d", divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [7:0] divide // Max M divide is 128 in UltrascalePlus + ); + + reg [5119:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed) + 40'b00110_00110_1111101000_1111101001_0000000001, // M=2 + 40'b01000_01000_1111101000_1111101001_0000000001, // M=3 + 40'b01011_01011_1111101000_1111101001_0000000001, // M=4 + 40'b01110_01110_1111101000_1111101001_0000000001, // M=5 + 40'b10001_10001_1111101000_1111101001_0000000001, // M=6 + 40'b10011_10011_1111101000_1111101001_0000000001, // M=7 + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, // M=127 + 40'b11111_11111_0011111010_1111101001_0000000001 // M=128 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", mmcm_pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the MMCM +// and outputs the digital filter settings necessary. +function [9:0] mmcm_pll_filter_lookup + ( + input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup_low; + reg [1279:0] lookup_high; + + reg [9:0] lookup_entry; + + begin + lookup_low = { + // CP_RES_LFHF + 10'b0011_1111_11, // M=1 - not legal + 10'b0011_1111_11, // M=2 + 10'b0011_1101_11, // M=3 + 10'b0011_0101_11, // M=4 + 10'b0011_1001_11, // M=5 + 10'b0011_1110_11, // M=6 + 10'b0011_1110_11, // M=7 + 10'b0011_0001_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_0110_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0011_1010_11, + 10'b0100_0110_11, + 10'b0011_1100_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, // M=127 + 10'b1101_1000_11 // M=128 +}; + + lookup_high = { + // CP_RES_LFHF + 10'b0111_1111_11, // M=1 - not legal + 10'b0111_1111_11, // M=2 + 10'b1110_1111_11, // M=3 + 10'b1111_1111_11, // M=4 + 10'b1111_1011_11, // M=5 + 10'b1111_1101_11, // M=6 + 10'b1111_0011_11, // M=7 + 10'b1110_0101_11, + 10'b1111_1001_11, + 10'b1111_1001_11, + 10'b1110_1110_11, + 10'b1111_1110_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1111_0001_11, + 10'b1110_0110_11, + 10'b1110_0110_11, + 10'b1111_0110_11, + 10'b1110_1010_11, + 10'b1110_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1111_1010_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1101_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1110_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1111_1100_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1110_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1111_0010_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1100_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1101_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1110_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1111_0100_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11, + 10'b1101_1000_11 // M=128 +}; + + // Set lookup_entry with the explicit bits from lookup with a part select + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10]; + end else begin + // High or optimized bandwidth + mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10]; + end + + `ifdef DEBUG + $display("filter_lookup: %b", mmcm_pll_filter_lookup); + `endif + end +endfunction + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], + pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh new file mode 100644 index 0000000..1d2dc69 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh @@ -0,0 +1,536 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ +// Date: 6/15/2015 +// Design Name: PLLE4 DRP +// Module Name: plle4_drp_func.h +// Version: 2.0 +// Target Devices: UltraScale+ Architecture +// Tool versions: 2017.1 +// Description: This header provides the functions necessary to +// calculate the DRP register values for the V6 PLL. +// +// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 +// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19 +// M_Rise bits have been removed for PLLE3 +// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for +// Ultrascale+ and for max M of 21 +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2009-2017 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +// These are user functions that should not be modified. Changes to the defines +// or code within the functions may alter the accuracy of the calculations. + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. These should not be modified, they are for development +// only +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + + `ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); + `endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end + `ifdef DEBUG + $display("round_frac: %h", round_frac); + `endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] mmcm_pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin +`ifndef SYNTHESIS + $display("ERROR: duty_cycle: %d is invalid", duty_cycle); + `endif + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + + `ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); + `endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates mx, delay_time, and phase_mux +// of a non-fractional counter based on the divide and phase +// +// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux +// is used. +function [10:0] mmcm_pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [1:0] mx; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); +`endif + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + + temp = round_frac(phase_in_cycles, 3); + + // set mx to 2'b00 that the phase mux from the VCO is enabled + mx = 2'b00; + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + + `ifdef DEBUG + $display("temp: %h", temp); + `endif + + // Setup the return value + mmcm_pll_phase={mx, phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] mmcm_pll_lock_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [839:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+ + 40'b00110_00110_1111101000_1111101001_0000000001, //2 + 40'b01000_01000_1111101000_1111101001_0000000001, //3 + 40'b01011_01011_1111101000_1111101001_0000000001, //4 + 40'b01110_01110_1111101000_1111101001_0000000001, //5 + 40'b10001_10001_1111101000_1111101001_0000000001, //6 + 40'b10011_10011_1111101000_1111101001_0000000001, //7 + 40'b10110_10110_1111101000_1111101001_0000000001, //8 + 40'b11001_11001_1111101000_1111101001_0000000001, //9 + 40'b11100_11100_1111101000_1111101001_0000000001, //10 + 40'b11111_11111_1110000100_1111101001_0000000001, //11 + 40'b11111_11111_1100111001_1111101001_0000000001, //12 + 40'b11111_11111_1011101110_1111101001_0000000001, //13 + 40'b11111_11111_1010111100_1111101001_0000000001, //14 + 40'b11111_11111_1010001010_1111101001_0000000001, //15 + 40'b11111_11111_1001110001_1111101001_0000000001, //16 + 40'b11111_11111_1000111111_1111101001_0000000001, //17 + 40'b11111_11111_1000100110_1111101001_0000000001, //18 + 40'b11111_11111_1000001101_1111101001_0000000001, //19 + 40'b11111_11111_0111110100_1111101001_0000000001, //20 + 40'b11111_11111_0111011011_1111101001_0000000001 //21 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40]; + `ifdef DEBUG + $display("lock_lookup: %b", pll_lock_lookup); + `endif + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. +function [9:0] mmcm_pll_filter_lookup + ( + input [6:0] divide // Max divide is 21 + ); + + reg [209:0] lookup; + reg [9:0] lookup_entry; + + begin + + lookup = { + // CP_RES_LFHF + 10'b0011_0111_11, //1 not legal in Ultrascale+ + 10'b0011_0111_11, //2 + 10'b0011_0011_11, //3 + 10'b0011_1001_11, //4 + 10'b0011_0001_11, //5 + 10'b0100_1110_11, //6 + 10'b0011_0110_11, //7 + 10'b0011_1010_11, //8 + 10'b0111_1001_11, //9 + 10'b0111_1001_11, //10 + 10'b0101_0110_11, //11 + 10'b1100_0101_11, //12 + 10'b0101_1010_11, //13 + 10'b0110_0110_11, //14 + 10'b0110_1010_11, //15 + 10'b0111_0110_11, //16 + 10'b1111_0101_11, //17 + 10'b1100_0110_11, //18 + 10'b1110_0001_11, //19 + 10'b1101_0110_11, //20 + 10'b1111_0001_11 //21 + }; + + mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10]; + + `ifdef DEBUG + $display("filter_lookup: %b", pll_filter_lookup); + `endif + end +endfunction + +// This function set the CLKOUTPHY divide settings to match +// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then +// the CLKOUTPHY will be set to 2'b00 since the VCO is internally +// doubled and 2'b00 will represent divide by 1. Similarly "VCO" +// will need to divide the doubled clock VCO clock frequency by +// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will +// need to divide the doubled VCO by 4, therefore 2'b10 +function [9:0] mmcm_pll_clkoutphy_calc + ( + input [8*9:0] CLKOUTPHY_MODE + ); + + if(CLKOUTPHY_MODE == "VCO_X2") begin + mmcm_pll_clkoutphy_calc= 2'b00; + end else if(CLKOUTPHY_MODE == "VCO") begin + mmcm_pll_clkoutphy_calc= 2'b01; + end else if(CLKOUTPHY_MODE == "CLKIN") begin + mmcm_pll_clkoutphy_calc= 2'b11; + end else begin // Assume "VCO_HALF" + mmcm_pll_clkoutphy_calc= 2'b10; + end + +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +function [37:0] mmcm_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = mmcm_pll_divider(divide, duty_cycle); + // mx[10:9], pm[8:6], dt[5:0] + phase_calc = mmcm_pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + `ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], + phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits + `endif + + mmcm_pll_count_calc = + { + // Upper Address + 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + + +// This function takes in the divide, phase, and duty cycle +// setting to calculate the upper and lower counter registers. +// for fractional multiply/divide functions. +// +// +function [37:0] mmcm_pll_frac_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle, // Multiplied by 1,000 + input [9:0] frac // Multiplied by 1000 + ); + + //Required for fractional divide calculations + reg [7:0] lt_frac; + reg [7:0] ht_frac; + + reg /*[7:0]*/ wf_fall_frac; + reg /*[7:0]*/ wf_rise_frac; + + reg [31:0] a; + reg [7:0] pm_rise_frac_filtered ; + reg [7:0] pm_fall_frac_filtered ; + reg [7:0] clkout0_divide_int; + reg [2:0] clkout0_divide_frac; + reg [7:0] even_part_high; + reg [7:0] even_part_low; + + reg [7:0] odd; + reg [7:0] odd_and_frac; + + reg [7:0] pm_fall; + reg [7:0] pm_rise; + reg [7:0] dt; + reg [7:0] dt_int; + reg [63:0] dt_calc; + + reg [7:0] pm_rise_frac; + reg [7:0] pm_fall_frac; + + reg [31:0] a_per_in_octets; + reg [31:0] a_phase_in_cycles; + + parameter precision = 0.125; + + reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 + reg [31: 0] phase_pos; + reg [31: 0] phase_vco; + reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin + `ifdef DEBUG + $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); + `endif + + //convert phase to fixed + if ((phase < -360000) || (phase > 360000)) begin +`ifndef SYNTHESIS + $display("ERROR: phase of $phase is not between -360000 and 360000"); + `endif + $finish; + end + + + // Return value is + // Transfer data + // RESERVED [37:36] + // FRAC_TIME [35:33] + // FRAC_WF_FALL [32] + // Upper address is: + // RESERVED [31:26] + // MX [25:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + + + + clkout0_divide_frac = frac / 125; + clkout0_divide_int = divide; + + even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); + even_part_low = even_part_high; + + odd = clkout0_divide_int - even_part_high - even_part_low; + odd_and_frac = (8*odd) + clkout0_divide_frac; + + lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) + ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) + + pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 + pm_rise = 0; //0 + + wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) + wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) + + + + //Calculate phase in fractional cycles + a_per_in_octets = (8 * divide) + (frac / 125) ; + a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors + pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; + + dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) + dt = dt_calc[7:0]; + + pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; + + dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) + pm_fall_frac = pm_fall + pm_rise_frac; + pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; + + div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] + phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} + + mmcm_pll_frac_count_calc[37:0] = + { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, + 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], + 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits + } ; + + `ifdef DEBUG + $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); + `endif + + end +endfunction + diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/delay.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/delay.v new file mode 100644 index 0000000..9272324 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/delay.v @@ -0,0 +1,55 @@ +`timescale 1ns / 1ps + + +module delay( + input clk, + input reset, + input enable, + input [31:0] length, + output reg done, + output reg [1:0] state = 4'd0 + ); + +parameter STATE_IDLE = 2'd0; +parameter STATE_DELAY = 2'd1; + +reg [31:0] counter = 32'd0; + + +always @(posedge clk) +begin + // default assignments + state <= state; + counter <= counter; + done <= 1'd0; + + if(reset) + begin + counter <= 32'd0; + state <= STATE_IDLE; + end + else + begin + case(state) + STATE_IDLE: + begin + if(enable) + begin + counter <= 32'd0; + state <= STATE_DELAY; + end + end + STATE_DELAY: + begin + counter <= counter + 1; + if(counter == length) + begin + done <= 1'd1; + state <= STATE_IDLE; + end + end + endcase + end +end + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/pulse.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/pulse.v new file mode 100644 index 0000000..cd9939a --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/pulse.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps + + +module pulse( + input clk, + input reset, + input enable, + input [31:0] length, + output reg pulse = 1'd0, + output reg done = 1'd0, + output reg [1:0] state = 2'd0 + ); + +reg [31:0] counter = 32'd0; + +parameter STATE_IDLE = 2'd0; +parameter STATE_PULSE = 2'd1; + +always @(posedge clk) +begin + // default assignments + state <= state; + counter <= counter; + pulse <= 1'd0; + done <= 1'd0; + + if(reset) + begin + counter <= 32'd0; + state <= STATE_IDLE; + end + else + begin + case(state) + STATE_IDLE: + begin + if(enable) + begin + counter <= 32'd0; + state <= STATE_PULSE; + pulse <= 1'd1; + end + end + STATE_PULSE: + begin + counter <= counter + 1; + pulse <= 1'd1; + if(counter == length) + begin + done <= 1'd1; + state <= STATE_IDLE; + end + end + endcase + end +end + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/top.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/top.v new file mode 100644 index 0000000..a2d2295 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/top.v @@ -0,0 +1,314 @@ +`timescale 1ns / 1ps + +module top( + input sys_clk, + output [1:0] led, // Led outputs + output [2:0] rgb, // RGB led + input [1:0] btn, // buttons + input [7:0] gpio, // GPIOs + input uart_txd_in, // This is the RX input.. thanks for the naming digilent :D + output uart_rxd_out, // This is the TX output + input trigger_in, + output power_out, + output glitch_out, + output mux_out + ); + + +assign mux_out = 1'b0; + +// deal with fucking meta stability +reg uart_rxd_stable = 1'd0; +always @(posedge sys_clk) +begin + uart_rxd_stable <= uart_txd_in; +end + +// Used to reset all modules (not fully functional currently) +// TODO add debouncer for button +reg reset = 1'd0; + +// Main UART transmitter +reg tx_enable = 1'd0; +reg [7:0] tx_data = 8'd67; +wire tx_ready; +uart_tx tx1( + .clk(sys_clk), + .reset(reset), + .data(tx_data), + .enable(tx_enable), + .tx(uart_rxd_out), + .ready(tx_ready) +); + + + + +// Main UART receiver +wire [7:0] rx_data; +wire rx_valid; +uart_rx rx1( + .clk(sys_clk), + .reset(reset), + .data(rx_data), + .rx(uart_rxd_stable), + .valid(rx_valid) +); + +// COMMANDS +// power cycle the target (B) +parameter CMD_POWER_CYCLE = 8'd66; +// set the duration of the glitch pulse (uint32) (C) +parameter CMD_SET_GLITCH_PULSE = 8'd67; +// set the duration of the delay between the trigger input and the glitch (uint32) (D) +parameter CMD_SET_DELAY = 8'd68; +// set the duration of the pulse used to reset the device (uint32) (E) +parameter CMD_SET_POWER_PULSE = 8'd69; +// execute glitch (wait for trigger, wait for $delay, send glitch pulse) (F) +parameter CMD_GLITCH = 8'd70; +// read the 8 gpio pins. returns a single byte with the states of the IOs (G) +parameter CMD_READ_GPIO = 8'd71; +// enable or disable the powercycle before glitching. (bool/single byte 0 or 1) (H) +parameter CMD_ENABLE_GLITCH_POWER_CYCLE = 8'd72; +// returns the state of power pulse, trigger, delay, glitch pulse +parameter CMD_GET_STATE = 8'd73; + + +// STATES +// Wait for a single command on UART +// white +parameter STATE_WAIT_COMMAND = 8'd0; +// Wait for 4 bytes on UART that set the glitch pulse +// purple +parameter STATE_SET_GLITCH_PULSE = 8'd2; +// Wait for 4 bytes on UART that set the delay +// red +parameter STATE_SET_DELAY = 8'd3; +// Wait for 4 bytes on UART that set the power cycle duration +// cyan +parameter STATE_SET_POWER_PULSE = 8'd4; +// Wait for 1 byte on UART that sets whether the target is power cycled before glitch +// green +parameter STATE_ENABLE_GLITCH_POWER_CYCLE = 8'd5; +// Wait for the power cycle to be over. +// blue +parameter STATE_WAIT_POWER_CYCLE = 8'd6; + +reg [7:0] state = STATE_WAIT_COMMAND; + +// Receiver for receiving uint32 via serial +reg u32_rec_enable = 1'd0; +wire u32_rec_valid; +wire [31:0] u32_rec_data; +uint32_receiver u32_rec( + .clk(sys_clk), + .reset(reset), + .uart_data(rx_data), + .uart_valid(rx_valid), + .data(u32_rec_data), + .data_valid(u32_rec_valid), + .enable(u32_rec_enable) +); + +// Variables used by the glitcher +reg [31:0] glitch_pulse_length = 32'd0; +reg [31:0] glitch_delay_length = 32'd0; +reg [31:0] power_pulse_length = 32'd0; +// whether the device should be powercycled before glitching +reg glitch_power_cycle = 1'd0; +// Indicate current state on RGB led +assign rgb = state[2:0]; + + +// power pulse +// only used in glitch chain if glitch_power_cycle is 1 +reg power_pulse_enable = 1'd0; +wire power_pulse_pulse; +wire power_pulse_done; +// Used to output diagnostics via UART +wire [1:0] power_pulse_state; +pulse power_pulse( + .clk(sys_clk), + .reset(reset), + .enable(power_pulse_enable), + .length(power_pulse_length), + .pulse(power_pulse_pulse), + .done(power_pulse_done), + .state(power_pulse_state) +); + +// trigger +reg glitch_trigger_enable = 1'b0; +// Used to disable the entire trigger during a power-cycle-only +reg disable_trigger = 1'b0; +wire glitch_trigger_enable_mixed = ((power_pulse_done && glitch_power_cycle) || glitch_trigger_enable) && ~disable_trigger; +reg [31:0] glitch_trigger_length = 32'd255; +wire glitch_trigger_triggered; +wire [1:0] glitch_trigger_state; + +trigger glitch_trigger( + .clk(sys_clk), + .reset(reset), + .enable(glitch_trigger_enable_mixed), + .in(trigger_in), + .trigger_length(glitch_trigger_length), + .triggered(glitch_trigger_triggered), + .state(glitch_trigger_state) + ); + +// glitch delay +wire glitch_delay_done; +wire [1:0] glitch_delay_state; +delay glitch_delay( + .clk(sys_clk), + .reset(reset), + .enable(glitch_trigger_triggered), + .length(glitch_delay_length), + .done(glitch_delay_done), + .state(glitch_delay_state) +); + + +// glitch pulse +// mix our manual glitch enable with the output from the delay +wire glitch_pulse_pulse; +wire glitch_pulse_done; +wire [1:0] glitch_pulse_state; +pulse glitch_pulse( + .clk(sys_clk), + .reset(reset), + .enable(glitch_delay_done), + .length(glitch_pulse_length), + .pulse(glitch_pulse_pulse), + .done(glitch_pulse_done), + .state(glitch_pulse_state) +); + +assign led[0] = power_pulse_pulse; +assign led[1] = glitch_pulse_pulse; +assign power_out = power_pulse_pulse; +// We also pull glitch high when power resetting to make sure we don't accidentally keep the core on +assign glitch_out = power_pulse_pulse || glitch_pulse_pulse; + +always @(posedge sys_clk) +begin + // default assignments + u32_rec_enable <= 1'd0; + glitch_pulse_length <= glitch_pulse_length; + glitch_delay_length <= glitch_delay_length; + power_pulse_length <= power_pulse_length; + power_pulse_enable <= 1'd0; + glitch_power_cycle <= glitch_power_cycle; + + glitch_trigger_enable <= 1'd0; + disable_trigger <= disable_trigger; + + state <= state; + tx_enable <= 1'b0; + + case(state) + STATE_WAIT_COMMAND: + begin + if(rx_valid) + begin + case(rx_data) + CMD_SET_GLITCH_PULSE: + begin + state <= STATE_SET_GLITCH_PULSE; + u32_rec_enable <= 1'd1; + end + CMD_SET_DELAY: + begin + state <= STATE_SET_DELAY; + u32_rec_enable <= 1'd1; + end + CMD_SET_POWER_PULSE: + begin + state <= STATE_SET_POWER_PULSE; + u32_rec_enable <= 1'd1; + end + CMD_READ_GPIO: + begin + tx_data <= gpio; + tx_enable <= 1'b1; + end + CMD_ENABLE_GLITCH_POWER_CYCLE: + begin + state <= STATE_ENABLE_GLITCH_POWER_CYCLE; + end + CMD_GLITCH: + begin + // If glitch with power cycle is enabled we + // use the power pulse to start the glitch + // (which will then in turn start the trigger) + if(glitch_power_cycle == 1'b1) + begin + power_pulse_enable <= 1'b1; + end + else + // Otherwise we directly enable the trigger + begin + glitch_trigger_enable <= 1'b1; + end + end + CMD_POWER_CYCLE: + begin + power_pulse_enable <= 1'b1; + disable_trigger <= 1'b1; + state <= STATE_WAIT_POWER_CYCLE; + end + CMD_GET_STATE: + begin + tx_data <= {power_pulse_state, glitch_trigger_state, glitch_delay_state, glitch_pulse_state}; + tx_enable <= 1'b1; + end + + endcase + end + + end + STATE_SET_GLITCH_PULSE: + begin + if(u32_rec_valid) + begin + glitch_pulse_length <= u32_rec_data; + state <= STATE_WAIT_COMMAND; + end + end + STATE_SET_DELAY: + begin + if(u32_rec_valid) + begin + glitch_delay_length <= u32_rec_data; + state <= STATE_WAIT_COMMAND; + end + end + STATE_SET_POWER_PULSE: + begin + if(u32_rec_valid) + begin + power_pulse_length <= u32_rec_data; + state <= STATE_WAIT_COMMAND; + end + end + STATE_ENABLE_GLITCH_POWER_CYCLE: + begin + if(rx_valid) + begin + glitch_power_cycle <= rx_data[0]; + state <= STATE_WAIT_COMMAND; + end + end + STATE_WAIT_POWER_CYCLE: + begin + if(power_pulse_done) + begin + disable_trigger <= 1'b0; + state <= STATE_WAIT_COMMAND; + end + end + endcase +end + + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/trigger.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/trigger.v new file mode 100644 index 0000000..4dd4d55 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/trigger.v @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps + +module trigger( + input clk, + input reset, + input enable, + input in, + input [31:0] trigger_length, + output reg triggered = 1'd0, + output reg [1:0] state = 2'd0 + ); + +parameter STATE_IDLE = 2'd0; +parameter STATE_WAIT_LOW = 2'd1; +parameter STATE_TRIGGERING = 2'd2; + +reg [31:0] counter; + +always @(posedge clk) +begin + triggered <= 1'd0; + counter <= counter; + state <= state; + if(reset) + begin + counter <= 1'd0; + state <= STATE_IDLE; + end + else + begin + case(state) + STATE_IDLE: + begin + if(enable) + begin + state <= STATE_WAIT_LOW; + end + end + STATE_WAIT_LOW: + begin + if(in == 1'b0) + begin + state <= STATE_TRIGGERING; + end + end + STATE_TRIGGERING: + begin + if(in) + begin + counter <= counter + 1; + if(counter == trigger_length) + begin + triggered <= 1'd1; + state <= STATE_IDLE; + end + end + else + begin + counter <= 0; + end + end + endcase + + end +end + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_definitions.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_definitions.v new file mode 100644 index 0000000..a82d9af --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_definitions.v @@ -0,0 +1,8 @@ +`timescale 1ns / 1ps + +// Definitons for the UART clockings +`define SYSTEM_CLOCK 100_000_000 + +// 115200 8N1 +`define UART_FULL_ETU (`SYSTEM_CLOCK/115200) +`define UART_HALF_ETU ((`SYSTEM_CLOCK/115200)/2) diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_rx.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_rx.v new file mode 100644 index 0000000..1d4a1bd --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_rx.v @@ -0,0 +1,107 @@ +`timescale 1ns / 1ps +`include "uart_definitions.v" + + +module uart_rx( + // System clock + input wire clk, + // Data input + output reg [7:0] data, + // Resets the entire module + input wire reset, + + // The data line + input wire rx, + + // Indicates the module is ready to receive + output reg valid + ); + +// States +parameter STATE_IDLE = 4'd0; +parameter STATE_START_BIT = 4'd1; +parameter STATE_DATA_BITS = 4'd2; +parameter STATE_STOP_BIT = 4'd3; + +// Hold state in this +reg [3:0] state = STATE_IDLE; + +// The bit we are sending currently +reg [3:0] current_bit = 4'd0; + +// Counter for baudrate +reg [31:0] etu_counter = 32'd0; + + +wire etu_full; +wire etu_half; + +assign etu_full = (etu_counter == `UART_FULL_ETU); +assign etu_half = (etu_counter == `UART_HALF_ETU); + +always @(posedge clk) +begin + if(reset == 1'b1) + begin + state <= STATE_IDLE; + current_bit <= 4'd0; + data <= 8'd0; + end + else // not resetting + begin + // default assignments + valid <= 1'd0; + data <= data; + current_bit <= current_bit; + state <= state; + + etu_counter <= etu_counter + 1; + + case(state) + STATE_IDLE: + begin + // Start condition detected + if(rx == 1'd0) + begin + state <= STATE_START_BIT; + etu_counter <= 32'd0; + current_bit <= 4'd0; + end + end + STATE_START_BIT: + begin + if(etu_half) + begin + state <= STATE_DATA_BITS; + etu_counter <= 32'd0; + current_bit <= 32'd0; + end + end + STATE_DATA_BITS: + begin + if(etu_full) + begin + + data <= {rx, data[7:1]}; + current_bit <= current_bit + 1; + etu_counter <= 32'd0; + if(current_bit == 4'd7) + begin + state <= STATE_STOP_BIT; + end + end + end + STATE_STOP_BIT: + begin + if(etu_full) + begin + valid <= 1'b1; + state <= STATE_IDLE; + etu_counter <= 32'd0; + end + end + endcase + end +end + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_tx.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_tx.v new file mode 100644 index 0000000..438bd7a --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/uart_tx.v @@ -0,0 +1,130 @@ +`timescale 1ns / 1ps +`include "uart_definitions.v" + +module uart_tx( + // System clock + input wire clk, + // Data input + input wire [7:0] data, + // Enable, pull high for one cycle to start sending + input wire enable, + // Resets the entire module + input wire reset, + + // The data line + output reg tx, + // Indicates the module is ready to receive + output reg ready = 1'b1 + ); + + + +// States +parameter STATE_IDLE = 4'd0; +parameter STATE_START_BIT = 4'd1; +parameter STATE_DATA_BITS = 4'd2; +parameter STATE_STOP_BIT = 4'd3; +parameter STATE_DONE = 4'd5; + +// Hold state in this +reg [3:0] state = STATE_IDLE; + +// The bit we are sending currently +reg [3:0] current_bit = 4'd0; + +// Counter for baudrate +reg [31:0] etu_counter = 32'd0; + +wire etu_full; +wire etu_half; + +assign etu_full = (etu_counter == `UART_FULL_ETU); +assign etu_half = (etu_counter == `UART_HALF_ETU); + +reg [7:0] data_local; + +always @(posedge clk) +begin + if(reset == 1'b1) + begin + state <= STATE_IDLE; + current_bit <= 8'd0; + tx <= 1'b1; + end + else + begin + // Default assignments + tx <= tx; + ready <= ready; + state <= state; + current_bit <= current_bit; + data_local <= data_local; + + // Always count up the ETU counter + etu_counter <= etu_counter + 1'd1; + + case(state) + STATE_IDLE: + begin + // Our state is idle, but we just got an enable signal. Start sending! + if(enable) + begin + data_local <= data; + state <= STATE_DATA_BITS; + tx <= 1'b0; + ready <= 1'b0; + current_bit <= 4'd0; + // Start etu_counter + etu_counter <= 32'd0; + end + else + begin + tx <= 1'b1; + ready <= 1'b1; + end + end + STATE_START_BIT: + begin + state <= STATE_DATA_BITS; + etu_counter <= 32'd0; + end + STATE_DATA_BITS: + begin + if(etu_full) + begin + etu_counter <= 32'd0; + tx <= data_local[0]; + data_local <= {data_local[0], data_local[7:1]}; + current_bit <= current_bit + 1'd1; + if(current_bit == 3'd7) + begin + state <= STATE_STOP_BIT; + end + end + end + STATE_STOP_BIT: + begin + if(etu_full) + begin + tx <= 1'd1; + etu_counter <= 32'd0; + state <= STATE_DONE; + end + end + STATE_DONE: + begin + if(etu_full) + begin + ready <= 1'b1; + state <= STATE_IDLE; + end + end + endcase + end + +end + + + + +endmodule diff --git a/chipfail-glitcher-artix-7.srcs/sources_1/new/uint32_receiver.v b/chipfail-glitcher-artix-7.srcs/sources_1/new/uint32_receiver.v new file mode 100644 index 0000000..5de10c7 --- /dev/null +++ b/chipfail-glitcher-artix-7.srcs/sources_1/new/uint32_receiver.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps + +module uint32_receiver( + input clk, + input reset, + input enable, + + // UART data + input [7:0] uart_data, + input uart_valid, + + // The data received + output reg [31:0] data, + // Whether the current output on data is valid + output reg data_valid = 1'b0 + ); + +parameter STATE_IDLE = 4'd0; +parameter STATE_RECEIVING = 4'd1; + +reg [3:0] state = STATE_IDLE; + +reg [3:0] received_bytes = 4'd0; + +always @(posedge clk) +begin + // default assignments + received_bytes <= received_bytes; + state <= state; + data_valid <= 1'b0; + data <= data; + if(reset) + begin + received_bytes <= 4'd0; + state <= STATE_IDLE; + end + else + begin + case(state) + STATE_IDLE: + begin + if(enable) + begin + received_bytes <= 4'd0; + data_valid <= 4'd0; + state <= STATE_RECEIVING; + end + end + STATE_RECEIVING: + begin + if(uart_valid) + begin + data <= {data[23:0], uart_data}; + received_bytes <= received_bytes + 1; + if(received_bytes == 3) + begin + state <= STATE_IDLE; + data_valid <= 1'b1; + end + end + end + endcase + end +end + +endmodule