Various 386 models

[Torinde]

Which of the discontinued 386 and 387 instructions are emulated by Bochs? (mostly System Management Mode related)

• i386
• Am386
• C&T 386
• Cyrix 386
• ALi 386
• Intel 387/287XL
• IIT 387
• Cyrix 387

[stlintel]

None of them

[Torinde]

FWIW, two of those are present in Intel 386/486/Quark and Cyrix CPUs. Intel Quark was discontinued only recently.

• MOV r32,TRx 0F 24 /r Move from test register
• MOV TRx,r32 0F 26 /r Move to test register

[Torinde]

Thanks for the quick response!

Separately, looking at cpuid.cc and CHANGES

1. MONITORX is mentioned as implemented in CHANGES, but I don't see it in cpuid.cc?
2. MCOMMIT, INVLPGB, PTWRITE, PREFETCHWT1, TDX/SEAM, SEV-ES/VMGEXIT, SEV-SNP/RMP - I didn't find them - are some of those implemented?
3. VIA PadLock (multiple extensions) - I think it'll be good to mention those as "not implemented" in cpuid.cc, on the correct place for add VIA PadLock emulation #304
4. CL1INVMB (SCC Single-chip Cloud Computer), LRBni (Larrabee/Knights Ferry KNF), LRBni2 (Knights Corner KNC) - I assume you don't plan on adding those

[stlintel]

MONITORX is AMD feature and AMD's CPUID are quite behind.
It should be enabled in some corresponding CPUID model - the newest we have for AMD is Ryzen.
As I understood Ryzen yet has no MONITORX so for MONITORX a new model has to be introduced.

MCOMMIT, INVLPGB, PTWRITE, PREFETCHWT1, TDX/SEAM, SEV-ES/VMGEXIT, SEV-SNP/RMP - None of these AMD extensions are implemented or planned to be implemented. Mainly because of lack of testing. I have no AMD machine or reference simulator which implements them correctly already.
Also security/encryption stuff like TDX, SGX and similar won't be implemented because I am not dealing with secure firmware these things come with.

VIA PadLock - relevant only for VIA CPU. If we want to add some VIA CPU model to Bochs (which one?) you may try to list all the gaps and we might build a plan how to close them. Not all the gaps have to be closed immediately, even for most recent Intel models there are blindspots which are not urgent or necessary.

Yes, I am not planning to do LRB and related stuff yet.

[Torinde]

I understand that most of those are not a priority.
My point was just that the bits for all of those (and other known) instruction (sets) to be mentioned/commented in cpuid.cc, either as:

• implemented
• not implemented

MONITORX: According what's in Wikipedia those are supported from Excavator onwards. I think it's present for example on Ryzen 5 1500X, which has CPUID 80000001: 00800F11-20000000-35C233FF-2FD3FBFF (third group, bit29 in reverse order?). It's already implemented in Bochs 2.6.9

MCOMMIT (Zen2), INVLPGB (Zen3) - which is your Ryzen model?
PTWRITE - it's an Intel one - and I think you have a note about it: "No plans for ..., Intel Processor Trace"
PREFETCHWT1 (Knights Landing, YongFeng), TDX/SEAM (Sapphire Rapids), probably you don't have any of those yet.

VIA PadLock - I try to list the gaps on its Issue: #312