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r8180_core.c
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r8180_core.c
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/*
This is part of rtl818x pci OpenSource driver - v 0.1
Copyright (C) Andrea Merello 2004-2005 <[email protected]>
Released under the terms of GPL (General Public License)
Parts of this driver are based on the GPL part of the official
Realtek driver.
Parts of this driver are based on the rtl8180 driver skeleton
from Patric Schenke & Andres Salomon.
Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
Parts of BB/RF code are derived from David Young rtl8180 netbsd driver.
RSSI calc function from 'The Deuce'
Some ideas borrowed from the 8139too.c driver included in linux kernel.
We (I?) want to thanks the Authors of those projecs and also the
Ndiswrapper's project Authors.
A big big thanks goes also to Realtek corp. for their help in my attempt to
add RTL8185 and RTL8225 support, and to David Young also.
Power management interface routines.
Written by Mariusz Matuszek.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#undef RX_DONT_PASS_UL
#undef DUMMY_RX
#include <linux/slab.h>
#include <linux/syscalls.h>
#include <linux/eeprom_93cx6.h>
#include <linux/interrupt.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include "r8180_hw.h"
#include "r8180.h"
#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
#include "r8180_93cx6.h" /* Card EEPROM */
#include "r8180_wx.h"
#include "r8180_dm.h"
#include "ieee80211/dot11d.h"
static struct pci_device_id rtl8180_pci_id_tbl[] = {
{
.vendor = PCI_VENDOR_ID_REALTEK,
.device = 0x8199,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.driver_data = 0,
},
{
.vendor = 0,
.device = 0,
.subvendor = 0,
.subdevice = 0,
.driver_data = 0,
}
};
static char ifname[IFNAMSIZ] = "wlan%d";
static int hwwep;
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl);
MODULE_AUTHOR("Andrea Merello <[email protected]>");
MODULE_DESCRIPTION("Linux driver for Realtek RTL8187SE WiFi cards");
module_param_string(ifname, ifname, sizeof(ifname), S_IRUGO|S_IWUSR);
module_param(hwwep, int, S_IRUGO|S_IWUSR);
MODULE_PARM_DESC(hwwep, " Try to use hardware WEP support. Still broken and not available on all cards");
static int rtl8180_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id);
static void rtl8180_pci_remove(struct pci_dev *pdev);
static void rtl8180_shutdown(struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
if (dev->netdev_ops->ndo_stop)
dev->netdev_ops->ndo_stop(dev);
pci_disable_device(pdev);
}
static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pdev);
if (!netif_running(dev))
goto out_pci_suspend;
if (dev->netdev_ops->ndo_stop)
dev->netdev_ops->ndo_stop(dev);
netif_device_detach(dev);
out_pci_suspend:
pci_save_state(pdev);
pci_disable_device(pdev);
pci_set_power_state(pdev, pci_choose_state(pdev, state));
return 0;
}
static int rtl8180_resume(struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
int err;
u32 val;
pci_set_power_state(pdev, PCI_D0);
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "pci_enable_device failed on resume\n");
return err;
}
pci_restore_state(pdev);
/*
* Suspend/Resume resets the PCI configuration space, so we have to
* re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
* from interfering with C3 CPU state. pci_restore_state won't help
* here since it only restores the first 64 bytes pci config header.
*/
pci_read_config_dword(pdev, 0x40, &val);
if ((val & 0x0000ff00) != 0)
pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
if (!netif_running(dev))
goto out;
if (dev->netdev_ops->ndo_open)
dev->netdev_ops->ndo_open(dev);
netif_device_attach(dev);
out:
return 0;
}
static struct pci_driver rtl8180_pci_driver = {
.name = RTL8180_MODULE_NAME,
.id_table = rtl8180_pci_id_tbl,
.probe = rtl8180_pci_probe,
.remove = rtl8180_pci_remove,
.suspend = rtl8180_suspend,
.resume = rtl8180_resume,
.shutdown = rtl8180_shutdown,
};
u8 read_nic_byte(struct net_device *dev, int x)
{
return 0xff&readb((u8 __iomem *)dev->mem_start + x);
}
u32 read_nic_dword(struct net_device *dev, int x)
{
return readl((u8 __iomem *)dev->mem_start + x);
}
u16 read_nic_word(struct net_device *dev, int x)
{
return readw((u8 __iomem *)dev->mem_start + x);
}
void write_nic_byte(struct net_device *dev, int x, u8 y)
{
writeb(y, (u8 __iomem *)dev->mem_start + x);
udelay(20);
}
void write_nic_dword(struct net_device *dev, int x, u32 y)
{
writel(y, (u8 __iomem *)dev->mem_start + x);
udelay(20);
}
void write_nic_word(struct net_device *dev, int x, u16 y)
{
writew(y, (u8 __iomem *)dev->mem_start + x);
udelay(20);
}
inline void force_pci_posting(struct net_device *dev)
{
read_nic_byte(dev, EPROM_CMD);
mb();
}
static irqreturn_t rtl8180_interrupt(int irq, void *netdev);
void set_nic_rxring(struct net_device *dev);
void set_nic_txring(struct net_device *dev);
static struct net_device_stats *rtl8180_stats(struct net_device *dev);
void rtl8180_commit(struct net_device *dev);
void rtl8180_start_tx_beacon(struct net_device *dev);
static struct proc_dir_entry *rtl8180_proc;
static int proc_get_registers(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
int i, n, max = 0xff;
/* This dump the current register page */
for (n = 0; n <= max;) {
seq_printf(m, "\nD: %2x > ", n);
for (i = 0; i < 16 && n <= max; i++, n++)
seq_printf(m, "%2x ", read_nic_byte(dev, n));
}
seq_putc(m, '\n');
return 0;
}
int get_curr_tx_free_desc(struct net_device *dev, int priority);
static int proc_get_stats_hw(struct seq_file *m, void *v)
{
return 0;
}
static int proc_get_stats_rx(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
seq_printf(m,
"RX OK: %lu\n"
"RX Retry: %lu\n"
"RX CRC Error(0-500): %lu\n"
"RX CRC Error(500-1000): %lu\n"
"RX CRC Error(>1000): %lu\n"
"RX ICV Error: %lu\n",
priv->stats.rxint,
priv->stats.rxerr,
priv->stats.rxcrcerrmin,
priv->stats.rxcrcerrmid,
priv->stats.rxcrcerrmax,
priv->stats.rxicverr
);
return 0;
}
static int proc_get_stats_tx(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
unsigned long totalOK;
totalOK = priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint;
seq_printf(m,
"TX OK: %lu\n"
"TX Error: %lu\n"
"TX Retry: %lu\n"
"TX beacon OK: %lu\n"
"TX beacon error: %lu\n",
totalOK,
priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr,
priv->stats.txretry,
priv->stats.txbeacon,
priv->stats.txbeaconerr
);
return 0;
}
static void rtl8180_proc_module_init(void)
{
DMESG("Initializing proc filesystem");
rtl8180_proc = proc_mkdir(RTL8180_MODULE_NAME, init_net.proc_net);
}
static void rtl8180_proc_module_remove(void)
{
remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net);
}
static void rtl8180_proc_remove_one(struct net_device *dev)
{
remove_proc_subtree(dev->name, rtl8180_proc);
}
/*
* seq_file wrappers for procfile show routines.
*/
static int rtl8180_proc_open(struct inode *inode, struct file *file)
{
struct net_device *dev = proc_get_parent_data(inode);
int (*show)(struct seq_file *, void *) = PDE_DATA(inode);
return single_open(file, show, dev);
}
static const struct file_operations rtl8180_proc_fops = {
.open = rtl8180_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
/*
* Table of proc files we need to create.
*/
struct rtl8180_proc_file {
char name[12];
int (*show)(struct seq_file *, void *);
};
static const struct rtl8180_proc_file rtl8180_proc_files[] = {
{ "stats-hw", &proc_get_stats_hw },
{ "stats-rx", &proc_get_stats_rx },
{ "stats-tx", &proc_get_stats_tx },
{ "registers", &proc_get_registers },
{ "" }
};
static void rtl8180_proc_init_one(struct net_device *dev)
{
const struct rtl8180_proc_file *f;
struct proc_dir_entry *dir;
dir = proc_mkdir_data(dev->name, 0, rtl8180_proc, dev);
if (!dir) {
DMESGE("Unable to initialize /proc/net/r8180/%s\n", dev->name);
return;
}
for (f = rtl8180_proc_files; f->name[0]; f++) {
if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir,
&rtl8180_proc_fops, f->show)) {
DMESGE("Unable to initialize /proc/net/r8180/%s/%s\n",
dev->name, f->name);
return;
}
}
}
/*
FIXME: check if we can use some standard already-existent
data type+functions in kernel
*/
static short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma,
struct buffer **bufferhead)
{
struct buffer *tmp;
if (!*buffer) {
*buffer = kmalloc(sizeof(struct buffer), GFP_KERNEL);
if (*buffer == NULL) {
DMESGE("Failed to kmalloc head of TX/RX struct");
return -1;
}
(*buffer)->next = *buffer;
(*buffer)->buf = buf;
(*buffer)->dma = dma;
if (bufferhead != NULL)
(*bufferhead) = (*buffer);
return 0;
}
tmp = *buffer;
while (tmp->next != (*buffer))
tmp = tmp->next;
tmp->next = kmalloc(sizeof(struct buffer), GFP_KERNEL);
if (tmp->next == NULL) {
DMESGE("Failed to kmalloc TX/RX struct");
return -1;
}
tmp->next->buf = buf;
tmp->next->dma = dma;
tmp->next->next = *buffer;
return 0;
}
static void buffer_free(struct net_device *dev, struct buffer **buffer, int len,
short consistent)
{
struct buffer *tmp, *next;
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct pci_dev *pdev = priv->pdev;
if (!*buffer)
return;
tmp = *buffer;
do {
next = tmp->next;
if (consistent) {
pci_free_consistent(pdev, len,
tmp->buf, tmp->dma);
} else {
pci_unmap_single(pdev, tmp->dma,
len, PCI_DMA_FROMDEVICE);
kfree(tmp->buf);
}
kfree(tmp);
tmp = next;
} while (next != *buffer);
*buffer = NULL;
}
int get_curr_tx_free_desc(struct net_device *dev, int priority)
{
struct r8180_priv *priv = ieee80211_priv(dev);
u32 *tail;
u32 *head;
int ret;
switch (priority) {
case MANAGE_PRIORITY:
head = priv->txmapringhead;
tail = priv->txmapringtail;
break;
case BK_PRIORITY:
head = priv->txbkpringhead;
tail = priv->txbkpringtail;
break;
case BE_PRIORITY:
head = priv->txbepringhead;
tail = priv->txbepringtail;
break;
case VI_PRIORITY:
head = priv->txvipringhead;
tail = priv->txvipringtail;
break;
case VO_PRIORITY:
head = priv->txvopringhead;
tail = priv->txvopringtail;
break;
case HI_PRIORITY:
head = priv->txhpringhead;
tail = priv->txhpringtail;
break;
default:
return -1;
}
if (head <= tail)
ret = priv->txringcount - (tail - head)/8;
else
ret = (head - tail)/8;
if (ret > priv->txringcount)
DMESG("BUG");
return ret;
}
static short check_nic_enought_desc(struct net_device *dev, int priority)
{
struct r8180_priv *priv = ieee80211_priv(dev);
struct ieee80211_device *ieee = netdev_priv(dev);
int requiredbyte, required;
requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data);
if (ieee->current_network.QoS_Enable)
requiredbyte += 2;
required = requiredbyte / (priv->txbuffsize-4);
if (requiredbyte % priv->txbuffsize)
required++;
/* for now we keep two free descriptor as a safety boundary
* between the tail and the head
*/
return (required+2 < get_curr_tx_free_desc(dev, priority));
}
void fix_tx_fifo(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
u32 *tmp;
int i;
for (tmp = priv->txmapring, i = 0;
i < priv->txringcount;
tmp += 8, i++) {
*tmp = *tmp & ~(1<<31);
}
for (tmp = priv->txbkpring, i = 0;
i < priv->txringcount;
tmp += 8, i++) {
*tmp = *tmp & ~(1<<31);
}
for (tmp = priv->txbepring, i = 0;
i < priv->txringcount;
tmp += 8, i++) {
*tmp = *tmp & ~(1<<31);
}
for (tmp = priv->txvipring, i = 0;
i < priv->txringcount;
tmp += 8, i++) {
*tmp = *tmp & ~(1<<31);
}
for (tmp = priv->txvopring, i = 0;
i < priv->txringcount;
tmp += 8, i++) {
*tmp = *tmp & ~(1<<31);
}
for (tmp = priv->txhpring, i = 0;
i < priv->txringcount;
tmp += 8, i++) {
*tmp = *tmp & ~(1<<31);
}
for (tmp = priv->txbeaconring, i = 0;
i < priv->txbeaconcount;
tmp += 8, i++) {
*tmp = *tmp & ~(1<<31);
}
priv->txmapringtail = priv->txmapring;
priv->txmapringhead = priv->txmapring;
priv->txmapbufstail = priv->txmapbufs;
priv->txbkpringtail = priv->txbkpring;
priv->txbkpringhead = priv->txbkpring;
priv->txbkpbufstail = priv->txbkpbufs;
priv->txbepringtail = priv->txbepring;
priv->txbepringhead = priv->txbepring;
priv->txbepbufstail = priv->txbepbufs;
priv->txvipringtail = priv->txvipring;
priv->txvipringhead = priv->txvipring;
priv->txvipbufstail = priv->txvipbufs;
priv->txvopringtail = priv->txvopring;
priv->txvopringhead = priv->txvopring;
priv->txvopbufstail = priv->txvopbufs;
priv->txhpringtail = priv->txhpring;
priv->txhpringhead = priv->txhpring;
priv->txhpbufstail = priv->txhpbufs;
priv->txbeaconringtail = priv->txbeaconring;
priv->txbeaconbufstail = priv->txbeaconbufs;
set_nic_txring(dev);
ieee80211_reset_queue(priv->ieee80211);
priv->ack_tx_to_ieee = 0;
}
void fix_rx_fifo(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
u32 *tmp;
struct buffer *rxbuf;
u8 rx_desc_size;
rx_desc_size = 8; /* 4*8 = 32 bytes */
for (tmp = priv->rxring, rxbuf = priv->rxbufferhead;
(tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size);
tmp += rx_desc_size, rxbuf = rxbuf->next) {
*(tmp+2) = rxbuf->dma;
*tmp = *tmp & ~0xfff;
*tmp = *tmp | priv->rxbuffersize;
*tmp |= (1<<31);
}
priv->rxringtail = priv->rxring;
priv->rxbuffer = priv->rxbufferhead;
priv->rx_skb_complete = 1;
set_nic_rxring(dev);
}
static void rtl8180_irq_disable(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
write_nic_dword(dev, IMR, 0);
force_pci_posting(dev);
priv->irq_enabled = 0;
}
void rtl8180_set_mode(struct net_device *dev, int mode)
{
u8 ecmd;
ecmd = read_nic_byte(dev, EPROM_CMD);
ecmd = ecmd & ~EPROM_CMD_OPERATING_MODE_MASK;
ecmd = ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
ecmd = ecmd & ~(1<<EPROM_CS_SHIFT);
ecmd = ecmd & ~(1<<EPROM_CK_SHIFT);
write_nic_byte(dev, EPROM_CMD, ecmd);
}
void rtl8180_beacon_tx_enable(struct net_device *dev);
void rtl8180_update_msr(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
u8 msr;
u32 rxconf;
msr = read_nic_byte(dev, MSR);
msr &= ~MSR_LINK_MASK;
rxconf = read_nic_dword(dev, RX_CONF);
if (priv->ieee80211->state == IEEE80211_LINKED) {
if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
else if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
else
msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
rxconf |= (1<<RX_CHECK_BSSID_SHIFT);
} else {
msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT);
}
write_nic_byte(dev, MSR, msr);
write_nic_dword(dev, RX_CONF, rxconf);
}
void rtl8180_set_chan(struct net_device *dev, short ch)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
if ((ch > 14) || (ch < 1)) {
printk("In %s: Invalid chnanel %d\n", __func__, ch);
return;
}
priv->chan = ch;
priv->rf_set_chan(dev, priv->chan);
}
void set_nic_txring(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma);
write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma);
write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma);
write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma);
write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma);
write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma);
write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma);
}
void rtl8180_beacon_tx_enable(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);
write_nic_byte(dev, TPPollStop, priv->dma_poll_mask);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
}
void rtl8180_beacon_tx_disable(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ;
write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
}
void rtl8180_rtx_disable(struct net_device *dev)
{
u8 cmd;
struct r8180_priv *priv = ieee80211_priv(dev);
cmd = read_nic_byte(dev, CMD);
write_nic_byte(dev, CMD, cmd &
~((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT)));
force_pci_posting(dev);
mdelay(10);
if (!priv->rx_skb_complete)
dev_kfree_skb_any(priv->rx_skb);
}
static short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count,
int addr)
{
int i;
u32 *desc;
u32 *tmp;
dma_addr_t dma_desc, dma_tmp;
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct pci_dev *pdev = priv->pdev;
void *buf;
if ((bufsize & 0xfff) != bufsize) {
DMESGE("TX buffer allocation too large");
return 0;
}
desc = (u32 *)pci_alloc_consistent(pdev,
sizeof(u32)*8*count+256, &dma_desc);
if (desc == NULL)
return -1;
if (dma_desc & 0xff)
/*
* descriptor's buffer must be 256 byte aligned
* we shouldn't be here, since we set DMA mask !
*/
WARN(1, "DMA buffer is not aligned\n");
tmp = desc;
for (i = 0; i < count; i++) {
buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp);
if (buf == NULL)
return -ENOMEM;
switch (addr) {
case TX_MANAGEPRIORITY_RING_ADDR:
if (-1 == buffer_add(&(priv->txmapbufs), buf, dma_tmp, NULL)) {
DMESGE("Unable to allocate mem for buffer NP");
return -ENOMEM;
}
break;
case TX_BKPRIORITY_RING_ADDR:
if (-1 == buffer_add(&(priv->txbkpbufs), buf, dma_tmp, NULL)) {
DMESGE("Unable to allocate mem for buffer LP");
return -ENOMEM;
}
break;
case TX_BEPRIORITY_RING_ADDR:
if (-1 == buffer_add(&(priv->txbepbufs), buf, dma_tmp, NULL)) {
DMESGE("Unable to allocate mem for buffer NP");
return -ENOMEM;
}
break;
case TX_VIPRIORITY_RING_ADDR:
if (-1 == buffer_add(&(priv->txvipbufs), buf, dma_tmp, NULL)) {
DMESGE("Unable to allocate mem for buffer LP");
return -ENOMEM;
}
break;
case TX_VOPRIORITY_RING_ADDR:
if (-1 == buffer_add(&(priv->txvopbufs), buf, dma_tmp, NULL)) {
DMESGE("Unable to allocate mem for buffer NP");
return -ENOMEM;
}
break;
case TX_HIGHPRIORITY_RING_ADDR:
if (-1 == buffer_add(&(priv->txhpbufs), buf, dma_tmp, NULL)) {
DMESGE("Unable to allocate mem for buffer HP");
return -ENOMEM;
}
break;
case TX_BEACON_RING_ADDR:
if (-1 == buffer_add(&(priv->txbeaconbufs), buf, dma_tmp, NULL)) {
DMESGE("Unable to allocate mem for buffer BP");
return -ENOMEM;
}
break;
}
*tmp = *tmp & ~(1<<31); /* descriptor empty, owned by the drv */
*(tmp+2) = (u32)dma_tmp;
*(tmp+3) = bufsize;
if (i+1 < count)
*(tmp+4) = (u32)dma_desc+((i+1)*8*4);
else
*(tmp+4) = (u32)dma_desc;
tmp = tmp+8;
}
switch (addr) {
case TX_MANAGEPRIORITY_RING_ADDR:
priv->txmapringdma = dma_desc;
priv->txmapring = desc;
break;
case TX_BKPRIORITY_RING_ADDR:
priv->txbkpringdma = dma_desc;
priv->txbkpring = desc;
break;
case TX_BEPRIORITY_RING_ADDR:
priv->txbepringdma = dma_desc;
priv->txbepring = desc;
break;
case TX_VIPRIORITY_RING_ADDR:
priv->txvipringdma = dma_desc;
priv->txvipring = desc;
break;
case TX_VOPRIORITY_RING_ADDR:
priv->txvopringdma = dma_desc;
priv->txvopring = desc;
break;
case TX_HIGHPRIORITY_RING_ADDR:
priv->txhpringdma = dma_desc;
priv->txhpring = desc;
break;
case TX_BEACON_RING_ADDR:
priv->txbeaconringdma = dma_desc;
priv->txbeaconring = desc;
break;
}
return 0;
}
static void free_tx_desc_rings(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct pci_dev *pdev = priv->pdev;
int count = priv->txringcount;
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->txmapring, priv->txmapringdma);
buffer_free(dev, &(priv->txmapbufs), priv->txbuffsize, 1);
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->txbkpring, priv->txbkpringdma);
buffer_free(dev, &(priv->txbkpbufs), priv->txbuffsize, 1);
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->txbepring, priv->txbepringdma);
buffer_free(dev, &(priv->txbepbufs), priv->txbuffsize, 1);
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->txvipring, priv->txvipringdma);
buffer_free(dev, &(priv->txvipbufs), priv->txbuffsize, 1);
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->txvopring, priv->txvopringdma);
buffer_free(dev, &(priv->txvopbufs), priv->txbuffsize, 1);
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->txhpring, priv->txhpringdma);
buffer_free(dev, &(priv->txhpbufs), priv->txbuffsize, 1);
count = priv->txbeaconcount;
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->txbeaconring, priv->txbeaconringdma);
buffer_free(dev, &(priv->txbeaconbufs), priv->txbuffsize, 1);
}
static void free_rx_desc_ring(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct pci_dev *pdev = priv->pdev;
int count = priv->rxringcount;
pci_free_consistent(pdev, sizeof(u32)*8*count+256,
priv->rxring, priv->rxringdma);
buffer_free(dev, &(priv->rxbuffer), priv->rxbuffersize, 0);
}
static short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count)
{
int i;
u32 *desc;
u32 *tmp;
dma_addr_t dma_desc, dma_tmp;
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct pci_dev *pdev = priv->pdev;
void *buf;
u8 rx_desc_size;
rx_desc_size = 8; /* 4*8 = 32 bytes */
if ((bufsize & 0xfff) != bufsize) {
DMESGE("RX buffer allocation too large");
return -1;
}
desc = (u32 *)pci_alloc_consistent(pdev, sizeof(u32)*rx_desc_size*count+256,
&dma_desc);
if (dma_desc & 0xff)
/*
* descriptor's buffer must be 256 byte aligned
* should never happen since we specify the DMA mask
*/
WARN(1, "DMA buffer is not aligned\n");
priv->rxring = desc;
priv->rxringdma = dma_desc;
tmp = desc;
for (i = 0; i < count; i++) {
buf = kmalloc(bufsize * sizeof(u8), GFP_ATOMIC);
if (buf == NULL) {
DMESGE("Failed to kmalloc RX buffer");
return -1;
}
dma_tmp = pci_map_single(pdev, buf, bufsize * sizeof(u8),
PCI_DMA_FROMDEVICE);
if (pci_dma_mapping_error(pdev, dma_tmp))
return -1;
if (-1 == buffer_add(&(priv->rxbuffer), buf, dma_tmp,
&(priv->rxbufferhead))) {
DMESGE("Unable to allocate mem RX buf");
return -1;
}
*tmp = 0; /* zero pads the header of the descriptor */
*tmp = *tmp | (bufsize&0xfff);
*(tmp+2) = (u32)dma_tmp;
*tmp = *tmp | (1<<31); /* descriptor void, owned by the NIC */
tmp = tmp+rx_desc_size;
}
*(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); /* this is the last descriptor */
return 0;
}
void set_nic_rxring(struct net_device *dev)
{
u8 pgreg;
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
pgreg = read_nic_byte(dev, PGSELECT);
write_nic_byte(dev, PGSELECT, pgreg & ~(1<<PGSELECT_PG_SHIFT));
write_nic_dword(dev, RXRING_ADDR, priv->rxringdma);
}
void rtl8180_reset(struct net_device *dev)
{
u8 cr;
rtl8180_irq_disable(dev);
cr = read_nic_byte(dev, CMD);
cr = cr & 2;
cr = cr | (1<<CMD_RST_SHIFT);
write_nic_byte(dev, CMD, cr);
force_pci_posting(dev);
mdelay(200);
if (read_nic_byte(dev, CMD) & (1<<CMD_RST_SHIFT))
DMESGW("Card reset timeout!");
else
DMESG("Card successfully reset");
rtl8180_set_mode(dev, EPROM_CMD_LOAD);
force_pci_posting(dev);
mdelay(200);
}
inline u16 ieeerate2rtlrate(int rate)
{
switch (rate) {
case 10:
return 0;
case 20:
return 1;
case 55:
return 2;
case 110:
return 3;
case 60:
return 4;
case 90:
return 5;
case 120:
return 6;
case 180:
return 7;
case 240:
return 8;